mirror of https://github.com/YosysHQ/yosys.git
Add tests for ECP5 architecture
This commit is contained in:
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1
Makefile
1
Makefile
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@ -710,6 +710,7 @@ test: $(TARGETS) $(EXTRA_TARGETS)
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+cd tests/aiger && bash run-test.sh $(ABCOPT)
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+cd tests/arch && bash run-test.sh
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+cd tests/ice40 && bash run-test.sh $(SEEDOPT)
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+cd tests/ecp5 && bash run-test.sh $(SEEDOPT)
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@echo ""
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@echo " Passed \"make test\"."
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@echo ""
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@ -0,0 +1,2 @@
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*.log
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/run-test.mk
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@ -0,0 +1,13 @@
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module top
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(
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input [3:0] x,
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input [3:0] y,
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output [3:0] A,
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output [3:0] B
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);
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assign A = x + y;
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assign B = x - y;
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endmodule
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@ -0,0 +1,8 @@
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read_verilog add_sub.v
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hierarchy -top top
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equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 10 t:LUT4
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select -assert-none t:LUT4 %% t:* %D
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@ -0,0 +1,91 @@
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module adff
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( input d, clk, clr, output reg q );
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initial begin
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q = 0;
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end
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always @( posedge clk, posedge clr )
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if ( clr )
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q <= 1'b0;
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else
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q <= d;
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endmodule
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module adffn
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( input d, clk, clr, output reg q );
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initial begin
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q = 0;
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end
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always @( posedge clk, negedge clr )
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if ( !clr )
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q <= 1'b0;
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else
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q <= d;
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endmodule
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module dffsr
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( input d, clk, pre, clr, output reg q );
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initial begin
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q = 0;
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end
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always @( posedge clk, posedge pre, posedge clr )
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if ( clr )
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q <= 1'b0;
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else if ( pre )
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q <= 1'b1;
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else
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q <= d;
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endmodule
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module ndffnsnr
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( input d, clk, pre, clr, output reg q );
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initial begin
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q = 0;
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end
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always @( negedge clk, negedge pre, negedge clr )
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if ( !clr )
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q <= 1'b0;
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else if ( !pre )
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q <= 1'b1;
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else
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q <= d;
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endmodule
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module top (
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input clk,
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input clr,
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input pre,
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input a,
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output b,b1,b2,b3
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);
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dffsr u_dffsr (
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.clk (clk ),
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.clr (clr),
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.pre (pre),
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.d (a ),
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.q (b )
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);
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ndffnsnr u_ndffnsnr (
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.clk (clk ),
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.clr (clr),
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.pre (pre),
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.d (a ),
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.q (b1 )
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);
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adff u_adff (
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.clk (clk ),
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.clr (clr),
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.d (a ),
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.q (b2 )
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);
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adffn u_adffn (
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.clk (clk ),
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.clr (clr),
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.d (a ),
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.q (b3 )
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);
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endmodule
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@ -0,0 +1,10 @@
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read_verilog adffs.v
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proc
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async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock
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flatten
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equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 4 t:TRELLIS_FF
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select -assert-count 7 t:LUT4
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select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
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@ -0,0 +1,19 @@
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module top (
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input clock,
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input [31:0] dinA, dinB,
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input [2:0] opcode,
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output reg [31:0] dout
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);
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always @(posedge clock) begin
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case (opcode)
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0: dout <= dinA + dinB;
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1: dout <= dinA - dinB;
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2: dout <= dinA >> dinB;
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3: dout <= $signed(dinA) >>> dinB;
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4: dout <= dinA << dinB;
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5: dout <= dinA & dinB;
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6: dout <= dinA | dinB;
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7: dout <= dinA ^ dinB;
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endcase
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end
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endmodule
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@ -0,0 +1,11 @@
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read_verilog alu.v
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hierarchy -top top
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proc
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flatten
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equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 62 t:SB_CARRY
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select -assert-count 32 t:SB_DFF
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select -assert-count 655 t:SB_LUT4
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select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D
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@ -0,0 +1,17 @@
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module top (
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out,
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clk,
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reset
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);
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output [7:0] out;
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input clk, reset;
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reg [7:0] out;
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always @(posedge clk, posedge reset)
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if (reset) begin
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out <= 8'b0 ;
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end else
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out <= out + 1;
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endmodule
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@ -0,0 +1,11 @@
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read_verilog counter.v
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hierarchy -top top
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proc
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flatten
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equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 6 t:SB_CARRY
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select -assert-count 8 t:SB_DFFR
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select -assert-count 8 t:SB_LUT4
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select -assert-none t:SB_CARRY t:SB_DFFR t:SB_LUT4 %% t:* %D
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@ -0,0 +1,37 @@
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module dff
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( input d, clk, output reg q );
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always @( posedge clk )
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q <= d;
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endmodule
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module dffe
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( input d, clk, en, output reg q );
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initial begin
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q = 0;
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end
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always @( posedge clk )
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if ( en )
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q <= d;
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endmodule
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module top (
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input clk,
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input en,
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input a,
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output b,b1,
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);
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dff u_dff (
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.clk (clk ),
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.d (a ),
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.q (b )
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);
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dffe u_ndffe (
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.clk (clk ),
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.en (en),
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.d (a ),
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.q (b1 )
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);
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endmodule
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@ -0,0 +1,9 @@
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read_verilog dffs.v
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hierarchy -top top
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proc
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flatten
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equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 2 t:TRELLIS_FF
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select -assert-none t:TRELLIS_FF %% t:* %D
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@ -0,0 +1,13 @@
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module top
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(
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input [3:0] x,
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input [3:0] y,
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output [3:0] A,
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output [3:0] B
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);
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assign A = x % y;
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assign B = x / y;
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endmodule
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@ -0,0 +1,12 @@
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read_verilog div_mod.v
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hierarchy -top top
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flatten
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equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 28 t:CCU2C
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select -assert-count 48 t:L6MUX21
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select -assert-count 194 t:LUT4
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select -assert-count 84 t:PFUMX
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select -assert-none t:LUT4 t:CCU2C t:L6MUX21 t:PFUMX %% t:* %D
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@ -0,0 +1,23 @@
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/*
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Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72].
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*/
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module top (din, write_en, waddr, wclk, raddr, rclk, dout);
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parameter addr_width = 8;
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parameter data_width = 8;
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input [addr_width-1:0] waddr, raddr;
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input [data_width-1:0] din;
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input write_en, wclk, rclk;
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output [data_width-1:0] dout;
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reg [data_width-1:0] dout;
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reg [data_width-1:0] mem [(1<<addr_width)-1:0]
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/* synthesis syn_ramstyle = "no_rw_check" */ ;
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always @(posedge wclk) // Write memory.
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begin
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if (write_en)
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mem[waddr] <= din; // Using write address bus.
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end
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always @(posedge rclk) // Read memory.
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begin
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dout <= mem[raddr]; // Using read address bus.
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end
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endmodule
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@ -0,0 +1,18 @@
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read_verilog dpram.v
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hierarchy -top top
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proc
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memory -nomap
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equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5
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memory
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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#ERROR: Failed to import cell gate.mem.0.0.0 (type DP16KD) to SAT database.
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#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd top
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select -assert-count 1 t:DP16KD
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select -assert-none t:DP16KD %% t:* %D
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write_verilog dpram_synth.v
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@ -0,0 +1,165 @@
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/* Generated by Yosys 0.9+36 (git sha1 7e8f7f4c, gcc 8.3.0-6ubuntu1 -Og -fPIC) */
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(* dynports = 1 *)
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(* top = 1 *)
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(* src = "dpram.v:4" *)
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module top(din, write_en, waddr, wclk, raddr, rclk, dout);
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(* unused_bits = "8" *)
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wire [8:0] _0_;
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(* src = "dpram.v:8" *)
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input [7:0] din;
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(* src = "dpram.v:10" *)
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output [7:0] dout;
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(* src = "dpram.v:7" *)
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input [7:0] raddr;
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(* src = "dpram.v:9" *)
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input rclk;
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(* src = "dpram.v:7" *)
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input [7:0] waddr;
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(* src = "dpram.v:9" *)
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input wclk;
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(* src = "dpram.v:9" *)
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input write_en;
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(* module_not_derived = 32'd1 *)
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(* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/brams_map.v:79" *)
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DP16KD #(
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.CLKAMUX("CLKA"),
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.CLKBMUX("CLKB"),
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.DATA_WIDTH_A(32'sd9),
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.DATA_WIDTH_B(32'sd9),
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.GSR("DISABLED"),
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.INITVAL_00(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_01(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_02(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_03(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_04(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_05(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_06(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_07(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_08(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_09(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_0A(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_0B(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_0C(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_0D(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_0E(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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.INITVAL_0F(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_10(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_11(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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||||
.INITVAL_12(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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||||
.INITVAL_13(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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||||
.INITVAL_14(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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||||
.INITVAL_15(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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||||
.INITVAL_16(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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||||
.INITVAL_17(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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||||
.INITVAL_18(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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||||
.INITVAL_19(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
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||||
.INITVAL_1A(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_1B(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_1C(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_1D(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_1E(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_1F(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_20(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_21(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_22(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_23(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_24(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_25(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_26(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_27(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_28(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_29(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_2A(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_2B(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_2C(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_2D(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_2E(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_2F(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_30(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_31(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_32(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_33(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_34(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_35(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_36(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_37(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_38(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_39(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_3A(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_3B(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_3C(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_3D(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_3E(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.INITVAL_3F(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx),
|
||||
.WRITEMODE_A("READBEFOREWRITE"),
|
||||
.WRITEMODE_B("READBEFOREWRITE")
|
||||
) \mem.0.0.0 (
|
||||
.ADA0(1'h0),
|
||||
.ADA1(1'h0),
|
||||
.ADA10(waddr[7]),
|
||||
.ADA11(1'h0),
|
||||
.ADA12(1'h0),
|
||||
.ADA13(1'h0),
|
||||
.ADA2(1'h0),
|
||||
.ADA3(waddr[0]),
|
||||
.ADA4(waddr[1]),
|
||||
.ADA5(waddr[2]),
|
||||
.ADA6(waddr[3]),
|
||||
.ADA7(waddr[4]),
|
||||
.ADA8(waddr[5]),
|
||||
.ADA9(waddr[6]),
|
||||
.ADB0(1'h0),
|
||||
.ADB1(1'h0),
|
||||
.ADB10(raddr[7]),
|
||||
.ADB11(1'h0),
|
||||
.ADB12(1'h0),
|
||||
.ADB13(1'h0),
|
||||
.ADB2(1'h0),
|
||||
.ADB3(raddr[0]),
|
||||
.ADB4(raddr[1]),
|
||||
.ADB5(raddr[2]),
|
||||
.ADB6(raddr[3]),
|
||||
.ADB7(raddr[4]),
|
||||
.ADB8(raddr[5]),
|
||||
.ADB9(raddr[6]),
|
||||
.CEA(1'h1),
|
||||
.CEB(1'h1),
|
||||
.CLKA(wclk),
|
||||
.CLKB(rclk),
|
||||
.DIA0(din[0]),
|
||||
.DIA1(din[1]),
|
||||
.DIA10(1'h0),
|
||||
.DIA11(1'h0),
|
||||
.DIA12(1'h0),
|
||||
.DIA13(1'h0),
|
||||
.DIA14(1'h0),
|
||||
.DIA15(1'h0),
|
||||
.DIA16(1'h0),
|
||||
.DIA17(1'h0),
|
||||
.DIA2(din[2]),
|
||||
.DIA3(din[3]),
|
||||
.DIA4(din[4]),
|
||||
.DIA5(din[5]),
|
||||
.DIA6(din[6]),
|
||||
.DIA7(din[7]),
|
||||
.DIA8(1'h0),
|
||||
.DIA9(1'h0),
|
||||
.DOB0(dout[0]),
|
||||
.DOB1(dout[1]),
|
||||
.DOB2(dout[2]),
|
||||
.DOB3(dout[3]),
|
||||
.DOB4(dout[4]),
|
||||
.DOB5(dout[5]),
|
||||
.DOB6(dout[6]),
|
||||
.DOB7(dout[7]),
|
||||
.DOB8(_0_[8]),
|
||||
.OCEA(1'h1),
|
||||
.OCEB(1'h1),
|
||||
.RSTA(1'h0),
|
||||
.RSTB(1'h0),
|
||||
.WEA(write_en),
|
||||
.WEB(1'h0)
|
||||
);
|
||||
assign _0_[7:0] = dout;
|
||||
endmodule
|
|
@ -0,0 +1,73 @@
|
|||
module fsm (
|
||||
clock,
|
||||
reset,
|
||||
req_0,
|
||||
req_1,
|
||||
gnt_0,
|
||||
gnt_1
|
||||
);
|
||||
input clock,reset,req_0,req_1;
|
||||
output gnt_0,gnt_1;
|
||||
wire clock,reset,req_0,req_1;
|
||||
reg gnt_0,gnt_1;
|
||||
|
||||
parameter SIZE = 3 ;
|
||||
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
|
||||
|
||||
reg [SIZE-1:0] state;
|
||||
reg [SIZE-1:0] next_state;
|
||||
|
||||
always @ (posedge clock)
|
||||
begin : FSM
|
||||
if (reset == 1'b1) begin
|
||||
state <= #1 IDLE;
|
||||
gnt_0 <= 0;
|
||||
gnt_1 <= 0;
|
||||
end else
|
||||
case(state)
|
||||
IDLE : if (req_0 == 1'b1) begin
|
||||
state <= #1 GNT0;
|
||||
gnt_0 <= 1;
|
||||
end else if (req_1 == 1'b1) begin
|
||||
gnt_1 <= 1;
|
||||
state <= #1 GNT0;
|
||||
end else begin
|
||||
state <= #1 IDLE;
|
||||
end
|
||||
GNT0 : if (req_0 == 1'b1) begin
|
||||
state <= #1 GNT0;
|
||||
end else begin
|
||||
gnt_0 <= 0;
|
||||
state <= #1 IDLE;
|
||||
end
|
||||
GNT1 : if (req_1 == 1'b1) begin
|
||||
state <= #1 GNT2;
|
||||
gnt_1 <= req_0;
|
||||
end
|
||||
GNT2 : if (req_0 == 1'b1) begin
|
||||
state <= #1 GNT1;
|
||||
gnt_1 <= req_1;
|
||||
end
|
||||
default : state <= #1 IDLE;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module top (
|
||||
input clk,
|
||||
input rst,
|
||||
input a,
|
||||
input b,
|
||||
output g0,
|
||||
output g1
|
||||
);
|
||||
|
||||
fsm u_fsm ( .clock(clk),
|
||||
.reset(rst),
|
||||
.req_0(a),
|
||||
.req_1(b),
|
||||
.gnt_0(g0),
|
||||
.gnt_1(g1));
|
||||
|
||||
endmodule
|
|
@ -0,0 +1,13 @@
|
|||
read_verilog fsm.v
|
||||
hierarchy -top top
|
||||
proc
|
||||
flatten
|
||||
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
|
||||
select -assert-count 2 t:SB_DFFESR
|
||||
select -assert-count 2 t:SB_DFFSR
|
||||
select -assert-count 1 t:SB_DFFSS
|
||||
select -assert-count 13 t:SB_LUT4
|
||||
select -assert-none t:SB_DFFESR t:SB_DFFSR t:SB_DFFSS t:SB_LUT4 %% t:* %D
|
|
@ -0,0 +1,58 @@
|
|||
module latchp
|
||||
( input d, clk, en, output reg q );
|
||||
always @*
|
||||
if ( en )
|
||||
q <= d;
|
||||
endmodule
|
||||
|
||||
module latchn
|
||||
( input d, clk, en, output reg q );
|
||||
always @*
|
||||
if ( !en )
|
||||
q <= d;
|
||||
endmodule
|
||||
|
||||
module latchsr
|
||||
( input d, clk, en, clr, pre, output reg q );
|
||||
always @*
|
||||
if ( clr )
|
||||
q <= 1'b0;
|
||||
else if ( pre )
|
||||
q <= 1'b1;
|
||||
else if ( en )
|
||||
q <= d;
|
||||
endmodule
|
||||
|
||||
|
||||
module top (
|
||||
input clk,
|
||||
input clr,
|
||||
input pre,
|
||||
input a,
|
||||
output b,b1,b2
|
||||
);
|
||||
|
||||
|
||||
latchp u_latchp (
|
||||
.en (clk ),
|
||||
.d (a ),
|
||||
.q (b )
|
||||
);
|
||||
|
||||
|
||||
latchn u_latchn (
|
||||
.en (clk ),
|
||||
.d (a ),
|
||||
.q (b1 )
|
||||
);
|
||||
|
||||
|
||||
latchsr u_latchsr (
|
||||
.en (clk ),
|
||||
.clr (clr),
|
||||
.pre (pre),
|
||||
.d (a ),
|
||||
.q (b2 )
|
||||
);
|
||||
|
||||
endmodule
|
|
@ -0,0 +1,17 @@
|
|||
read_verilog latches.v
|
||||
design -save read
|
||||
|
||||
proc
|
||||
async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock
|
||||
flatten
|
||||
synth_ecp5
|
||||
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
|
||||
design -load read
|
||||
synth_ecp5
|
||||
cd top
|
||||
select -assert-count 4 t:LUT4
|
||||
select -assert-count 1 t:PFUMX
|
||||
select -assert-none t:LUT4 t:PFUMX %% t:* %D
|
||||
write_verilog latches_synth.v
|
|
@ -0,0 +1,109 @@
|
|||
/* Generated by Yosys 0.9+36 (git sha1 7e8f7f4c, gcc 8.3.0-6ubuntu1 -Og -fPIC) */
|
||||
|
||||
(* top = 1 *)
|
||||
(* src = "latches.v:27" *)
|
||||
module top(clk, clr, pre, a, b, b1, b2);
|
||||
(* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:105" *)
|
||||
wire _0_;
|
||||
(* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:105" *)
|
||||
wire _1_;
|
||||
(* src = "latches.v:31" *)
|
||||
input a;
|
||||
(* src = "latches.v:32" *)
|
||||
output b;
|
||||
(* src = "latches.v:32" *)
|
||||
output b1;
|
||||
(* src = "latches.v:32" *)
|
||||
output b2;
|
||||
(* src = "latches.v:28" *)
|
||||
input clk;
|
||||
(* src = "latches.v:29" *)
|
||||
input clr;
|
||||
(* src = "latches.v:30" *)
|
||||
input pre;
|
||||
(* src = "latches.v:43|latches.v:9" *)
|
||||
wire \u_latchn.d ;
|
||||
(* src = "latches.v:43|latches.v:9" *)
|
||||
wire \u_latchn.en ;
|
||||
(* src = "latches.v:43|latches.v:9" *)
|
||||
wire \u_latchn.q ;
|
||||
(* src = "latches.v:36|latches.v:2" *)
|
||||
wire \u_latchp.d ;
|
||||
(* src = "latches.v:36|latches.v:2" *)
|
||||
wire \u_latchp.en ;
|
||||
(* src = "latches.v:36|latches.v:2" *)
|
||||
wire \u_latchp.q ;
|
||||
(* src = "latches.v:50|latches.v:16" *)
|
||||
wire \u_latchsr.clr ;
|
||||
(* src = "latches.v:50|latches.v:16" *)
|
||||
wire \u_latchsr.d ;
|
||||
(* src = "latches.v:50|latches.v:16" *)
|
||||
wire \u_latchsr.en ;
|
||||
(* src = "latches.v:50|latches.v:16" *)
|
||||
wire \u_latchsr.pre ;
|
||||
(* src = "latches.v:50|latches.v:16" *)
|
||||
wire \u_latchsr.q ;
|
||||
(* module_not_derived = 32'd1 *)
|
||||
(* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:106" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h5150)
|
||||
) _2_ (
|
||||
.A(clr),
|
||||
.B(clk),
|
||||
.C(pre),
|
||||
.D(b2),
|
||||
.Z(_0_)
|
||||
);
|
||||
(* module_not_derived = 32'd1 *)
|
||||
(* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:108" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h5554)
|
||||
) _3_ (
|
||||
.A(clr),
|
||||
.B(clk),
|
||||
.C(pre),
|
||||
.D(b2),
|
||||
.Z(_1_)
|
||||
);
|
||||
(* module_not_derived = 32'd1 *)
|
||||
(* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:110" *)
|
||||
PFUMX _4_ (
|
||||
.ALUT(_1_),
|
||||
.BLUT(_0_),
|
||||
.C0(a),
|
||||
.Z(b2)
|
||||
);
|
||||
(* module_not_derived = 32'd1 *)
|
||||
(* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *)
|
||||
LUT4 #(
|
||||
.INIT(16'bx1x1x1x0x0x1x0x0)
|
||||
) _5_ (
|
||||
.A(1'h0),
|
||||
.B(clk),
|
||||
.C(b),
|
||||
.D(a),
|
||||
.Z(b)
|
||||
);
|
||||
(* module_not_derived = 32'd1 *)
|
||||
(* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *)
|
||||
LUT4 #(
|
||||
.INIT(16'bx1x1x0x1x1x0x0x0)
|
||||
) _6_ (
|
||||
.A(1'h0),
|
||||
.B(clk),
|
||||
.C(b1),
|
||||
.D(a),
|
||||
.Z(b1)
|
||||
);
|
||||
assign \u_latchn.d = a;
|
||||
assign \u_latchn.en = clk;
|
||||
assign \u_latchn.q = b1;
|
||||
assign \u_latchp.d = a;
|
||||
assign \u_latchp.en = clk;
|
||||
assign \u_latchp.q = b;
|
||||
assign \u_latchsr.clr = clr;
|
||||
assign \u_latchsr.d = a;
|
||||
assign \u_latchsr.en = clk;
|
||||
assign \u_latchsr.pre = pre;
|
||||
assign \u_latchsr.q = b2;
|
||||
endmodule
|
|
@ -0,0 +1,18 @@
|
|||
module top
|
||||
(
|
||||
input [0:7] in,
|
||||
output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
|
||||
);
|
||||
|
||||
assign B1 = in[0] & in[1];
|
||||
assign B2 = in[0] | in[1];
|
||||
assign B3 = in[0] ~& in[1];
|
||||
assign B4 = in[0] ~| in[1];
|
||||
assign B5 = in[0] ^ in[1];
|
||||
assign B6 = in[0] ~^ in[1];
|
||||
assign B7 = ~in[0];
|
||||
assign B8 = in[0];
|
||||
assign B9 = in[0:1] && in [2:3];
|
||||
assign B10 = in[0:1] || in [2:3];
|
||||
|
||||
endmodule
|
|
@ -0,0 +1,7 @@
|
|||
read_verilog logic.v
|
||||
hierarchy -top top
|
||||
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
select -assert-count 9 t:SB_LUT4
|
||||
select -assert-none t:SB_LUT4 %% t:* %D
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 77].
|
||||
*/
|
||||
module top(clk,a,b,c,set);
|
||||
parameter A_WIDTH = 4;
|
||||
parameter B_WIDTH = 3;
|
||||
input set;
|
||||
input clk;
|
||||
input signed [(A_WIDTH - 1):0] a;
|
||||
input signed [(B_WIDTH - 1):0] b;
|
||||
output signed [(A_WIDTH + B_WIDTH - 1):0] c;
|
||||
reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c;
|
||||
assign c = reg_tmp_c;
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if(set)
|
||||
begin
|
||||
reg_tmp_c <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
reg_tmp_c <= a * b + c;
|
||||
end
|
||||
end
|
||||
endmodule
|
|
@ -0,0 +1,15 @@
|
|||
read_verilog macc.v
|
||||
proc
|
||||
hierarchy -top top
|
||||
#Failed because of 14 unproven cells.
|
||||
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
|
||||
#equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
select -assert-count 4 t:CCU2C
|
||||
select -assert-count 6 t:L6MUX21
|
||||
select -assert-count 49 t:LUT4
|
||||
select -assert-count 19 t:PFUMX
|
||||
select -assert-count 7 t:TRELLIS_FF
|
||||
|
||||
select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D
|
|
@ -0,0 +1,21 @@
|
|||
module top
|
||||
(
|
||||
input [7:0] data_a,
|
||||
input [6:1] addr_a,
|
||||
input we_a, clk,
|
||||
output reg [7:0] q_a
|
||||
);
|
||||
// Declare the RAM variable
|
||||
reg [7:0] ram[63:0];
|
||||
|
||||
// Port A
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (we_a)
|
||||
begin
|
||||
ram[addr_a] <= data_a;
|
||||
q_a <= data_a;
|
||||
end
|
||||
q_a <= ram[addr_a];
|
||||
end
|
||||
endmodule
|
|
@ -0,0 +1,21 @@
|
|||
read_verilog memory.v
|
||||
hierarchy -top top
|
||||
proc
|
||||
memory -nomap
|
||||
equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5
|
||||
memory
|
||||
opt -full
|
||||
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
#ERROR: Called with -verify and proof did fail!
|
||||
#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
|
||||
|
||||
design -load postopt
|
||||
cd top
|
||||
select -assert-count 24 t:L6MUX21
|
||||
select -assert-count 71 t:LUT4
|
||||
select -assert-count 32 t:PFUMX
|
||||
select -assert-count 8 t:TRELLIS_DPR16X4
|
||||
select -assert-count 35 t:TRELLIS_FF
|
||||
select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D
|
||||
write_verilog memory_synth.v
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,11 @@
|
|||
module top
|
||||
(
|
||||
input [5:0] x,
|
||||
input [5:0] y,
|
||||
|
||||
output [11:0] A,
|
||||
);
|
||||
|
||||
assign A = x * y;
|
||||
|
||||
endmodule
|
|
@ -0,0 +1,11 @@
|
|||
read_verilog mul.v
|
||||
hierarchy -top top
|
||||
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
select -assert-count 6 t:CCU2C
|
||||
select -assert-count 46 t:L6MUX21
|
||||
select -assert-count 169 t:LUT4
|
||||
select -assert-count 72 t:PFUMX
|
||||
|
||||
select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX %% t:* %D
|
|
@ -0,0 +1,100 @@
|
|||
module mux2 (S,A,B,Y);
|
||||
input S;
|
||||
input A,B;
|
||||
output reg Y;
|
||||
|
||||
always @(*)
|
||||
Y = (S)? B : A;
|
||||
endmodule
|
||||
|
||||
module mux4 ( S, D, Y );
|
||||
|
||||
input[1:0] S;
|
||||
input[3:0] D;
|
||||
output Y;
|
||||
|
||||
reg Y;
|
||||
wire[1:0] S;
|
||||
wire[3:0] D;
|
||||
|
||||
always @*
|
||||
begin
|
||||
case( S )
|
||||
0 : Y = D[0];
|
||||
1 : Y = D[1];
|
||||
2 : Y = D[2];
|
||||
3 : Y = D[3];
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module mux8 ( S, D, Y );
|
||||
|
||||
input[2:0] S;
|
||||
input[7:0] D;
|
||||
output Y;
|
||||
|
||||
reg Y;
|
||||
wire[2:0] S;
|
||||
wire[7:0] D;
|
||||
|
||||
always @*
|
||||
begin
|
||||
case( S )
|
||||
0 : Y = D[0];
|
||||
1 : Y = D[1];
|
||||
2 : Y = D[2];
|
||||
3 : Y = D[3];
|
||||
4 : Y = D[4];
|
||||
5 : Y = D[5];
|
||||
6 : Y = D[6];
|
||||
7 : Y = D[7];
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module mux16 (D, S, Y);
|
||||
input [15:0] D;
|
||||
input [3:0] S;
|
||||
output Y;
|
||||
|
||||
assign Y = D[S];
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module top (
|
||||
input [3:0] S,
|
||||
input [15:0] D,
|
||||
output M2,M4,M8,M16
|
||||
);
|
||||
|
||||
mux2 u_mux2 (
|
||||
.S (S[0]),
|
||||
.A (D[0]),
|
||||
.B (D[1]),
|
||||
.Y (M2)
|
||||
);
|
||||
|
||||
|
||||
mux4 u_mux4 (
|
||||
.S (S[1:0]),
|
||||
.D (D[3:0]),
|
||||
.Y (M4)
|
||||
);
|
||||
|
||||
mux8 u_mux8 (
|
||||
.S (S[2:0]),
|
||||
.D (D[7:0]),
|
||||
.Y (M8)
|
||||
);
|
||||
|
||||
mux16 u_mux16 (
|
||||
.S (S[3:0]),
|
||||
.D (D[15:0]),
|
||||
.Y (M16)
|
||||
);
|
||||
|
||||
endmodule
|
|
@ -0,0 +1,11 @@
|
|||
read_verilog mux.v
|
||||
proc
|
||||
flatten
|
||||
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
select -assert-count 32 t:LUT4
|
||||
select -assert-count 8 t:L6MUX21
|
||||
select -assert-count 14 t:PFUMX
|
||||
|
||||
select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
|
|
@ -0,0 +1,18 @@
|
|||
/*
|
||||
Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 74].
|
||||
*/
|
||||
module top(data, addr);
|
||||
output [3:0] data;
|
||||
input [4:0] addr;
|
||||
always @(addr) begin
|
||||
case (addr)
|
||||
0 : data = 'h4;
|
||||
1 : data = 'h9;
|
||||
2 : data = 'h1;
|
||||
15 : data = 'h8;
|
||||
16 : data = 'h1;
|
||||
17 : data = 'h0;
|
||||
default : data = 'h0;
|
||||
endcase
|
||||
end
|
||||
endmodule
|
|
@ -0,0 +1,9 @@
|
|||
read_verilog rom.v
|
||||
proc
|
||||
flatten
|
||||
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
select -assert-count 6 t:LUT4
|
||||
select -assert-count 3 t:PFUMX
|
||||
select -assert-none t:LUT4 t:PFUMX %% t:* %D
|
|
@ -0,0 +1,20 @@
|
|||
#!/usr/bin/env bash
|
||||
set -e
|
||||
{
|
||||
echo "all::"
|
||||
for x in *.ys; do
|
||||
echo "all:: run-$x"
|
||||
echo "run-$x:"
|
||||
echo " @echo 'Running $x..'"
|
||||
echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'"
|
||||
done
|
||||
for s in *.sh; do
|
||||
if [ "$s" != "run-test.sh" ]; then
|
||||
echo "all:: run-$s"
|
||||
echo "run-$s:"
|
||||
echo " @echo 'Running $s..'"
|
||||
echo " @bash $s"
|
||||
fi
|
||||
done
|
||||
} > run-test.mk
|
||||
exec ${MAKE:-make} -f run-test.mk
|
|
@ -0,0 +1,22 @@
|
|||
module top (
|
||||
out,
|
||||
clk,
|
||||
in
|
||||
);
|
||||
output [7:0] out;
|
||||
input signed clk, in;
|
||||
reg signed [7:0] out = 0;
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
`ifndef BUG
|
||||
out <= out >> 1;
|
||||
out[7] <= in;
|
||||
`else
|
||||
|
||||
out <= out << 1;
|
||||
out[7] <= in;
|
||||
`endif
|
||||
end
|
||||
|
||||
endmodule
|
|
@ -0,0 +1,9 @@
|
|||
read_verilog shifter.v
|
||||
hierarchy -top top
|
||||
proc
|
||||
flatten
|
||||
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
select -assert-count 8 t:SB_DFF
|
||||
select -assert-none t:SB_DFF %% t:* %D
|
|
@ -0,0 +1,23 @@
|
|||
module tristate (en, i, o);
|
||||
input en;
|
||||
input i;
|
||||
output o;
|
||||
|
||||
assign o = en ? i : 1'bz;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module top (
|
||||
input en,
|
||||
input a,
|
||||
output b
|
||||
);
|
||||
|
||||
tristate u_tri (
|
||||
.en (en ),
|
||||
.i (a ),
|
||||
.o (b )
|
||||
);
|
||||
|
||||
endmodule
|
|
@ -0,0 +1,9 @@
|
|||
read_verilog tribuf.v
|
||||
hierarchy -top top
|
||||
proc
|
||||
flatten
|
||||
equiv_opt -assert -map +/ecp5/cells_sim.v -map +/simcells.v synth_ecp5 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:$_TBUF_
|
||||
select -assert-none t:$_TBUF_ %% t:* %D
|
Loading…
Reference in New Issue