mirror of https://github.com/YosysHQ/yosys.git
Add nonexcl case test, comment out two others
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@ -179,3 +179,21 @@ module cliffordwolf_freduce (
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if (s == 2) o = d;
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end
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endmodule
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module case_nonexclusive_select (
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input wire [1:0] x, y,
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input wire a, b, c, d, e,
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output reg o
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);
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always @* begin
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case (x)
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0, 2: o = b;
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1: o = c;
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default: begin
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o = a;
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if (y == 0) o = d;
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if (y == 1) o = e;
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end
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endcase
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end
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endmodule
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@ -1,5 +1,6 @@
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read_verilog muxpack.v
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design -save read
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hierarchy -top mux_if_unbal_4_1
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prep
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design -save gold
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@ -29,20 +30,21 @@ design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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design -load read
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hierarchy -top mux_if_unbal_5_3_invert
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prep
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design -save gold
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muxpack
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opt
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stat
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select -assert-count 0 t:$mux
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select -assert-count 1 t:$pmux
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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# TODO: Currently ExclusiveDatabase only analyses $eq cells
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#design -load read
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#hierarchy -top mux_if_unbal_5_3_invert
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#prep
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#design -save gold
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#muxpack
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#opt
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#stat
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#select -assert-count 0 t:$mux
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#select -assert-count 1 t:$pmux
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#design -stash gate
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#design -import gold -as gold
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#design -import gate -as gate
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#miter -equiv -flatten -make_assert -make_outputs gold gate miter
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#sat -verify -prove-asserts -show-ports miter
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design -load read
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hierarchy -top mux_if_unbal_5_3_width_mismatch
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@ -156,8 +158,8 @@ design -save gold
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muxpack
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opt
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stat
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select -assert-count 2 t:$mux
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select -assert-count 1 t:$pmux
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select -assert-count 4 t:$mux
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select -assert-count 0 t:$pmux
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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@ -171,25 +173,40 @@ design -save gold
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muxpack
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opt
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stat
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select -assert-count 0 t:$mux
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select -assert-count 1 t:$pmux
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select -assert-count 3 t:$mux
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select -assert-count 0 t:$pmux
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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#design -load read
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#hierarchy -top cliffordwolf_freduce
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#prep
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#design -save gold
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#proc; opt; freduce; opt
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#show
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#muxpack
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#opt
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#stat
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#select -assert-count 0 t:$mux
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#select -assert-count 1 t:$pmux
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#design -stash gate
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#design -import gold -as gold
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#design -import gate -as gate
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#miter -equiv -flatten -make_assert -make_outputs gold gate miter
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#sat -verify -prove-asserts -show-ports miter
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design -load read
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hierarchy -top cliffordwolf_freduce
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hierarchy -top case_nonexclusive_select
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prep
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design -save gold
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proc; opt; freduce; opt
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write_verilog -noexpr -norename
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muxpack
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opt
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stat
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select -assert-count 0 t:$mux
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select -assert-count 1 t:$pmux
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select -assert-count 2 t:$pmux
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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