Add proper test for SV-style arrays

Signed-off-by: Clifford Wolf <clifford@clifford.at>

tests/simple/arrays02.sv

@@ -0,0 +1,16 @@
+module uut_arrays02(clock, we, addr, wr_data, rd_data);
+
+input clock, we;
+input [3:0] addr, wr_data;
+output [3:0] rd_data;
+reg [3:0] rd_data;
+
+reg [3:0] memory [16];
+
+always @(posedge clock) begin
+	if (we)
+		memory[addr] <= wr_data;
+	rd_data <= memory[addr];
+end
+
+endmodule

tests/various/unpacked_arrays.sv

@@ -1,4 +0,0 @@
-module unpacked_arrays;
-  reg array_range [0:7];
-  reg array_size [8];
-endmodule

tests/various/unpacked_arrays.ys

@@ -1,2 +0,0 @@
-read_verilog -sv unpacked_arrays.sv
-stat