Add test case from #997

Signed-off-by: Clifford Wolf <clifford@clifford.at>

tests/simple/dff_init.v

@@ -40,3 +40,15 @@ module dff1a_test(n1, n1_inv, clk);
       n1 <= n1_inv;
   assign n1_inv = ~n1;
 endmodule
+
+module dff_test_997 (y, clk, wire4);
+// https://github.com/YosysHQ/yosys/issues/997
+   output wire [1:0] y;
+   input             clk;
+   input signed      wire4;
+   reg [1:0]  reg10 = 0;
+   always @(posedge clk) begin
+      reg10 <= wire4;
+   end
+   assign y = reg10;
+endmodule