riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Add simcells.v, simlib.v, and some output

This commit is contained in:
Eddie Hung 2019-06-27 11:13:49 -07:00
parent 71b046d639
commit ab7c431905
1 changed files with 11 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
tests/arch/run-test.sh
View File

@ -4,5 +4,15 @@ set -e
echo "Running syntax check on arch sim models"
for arch in ../../techlibs/*; do
find $arch -name cells_sim.v -print0 | xargs -0 -n1 -r iverilog -t null -I$arch
find $arch -name cells_sim.v | while read path; do
echo -n "Test $path ->"
iverilog -t null -I$arch $path
echo " ok"
done
done
for path in "../../techlibs/common/simcells.v" "../../techlibs/common/simlib.v"; do
echo -n "Test $path ->"
iverilog -t null $path
echo " ok"
done