mirror of https://github.com/YosysHQ/yosys.git
Fix warnings
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@ -74,7 +74,7 @@ always @*
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else o <= {W{1'bx}};
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endmodule
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module mux_if_unbal_5_3_nonexcl #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
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module mux_if_unbal_5_3_nonexcl #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
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always @* begin
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o <= {W{1'bx}};
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if (s == 0) o <= i[0*W+:W];
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@ -86,7 +86,7 @@ always @* begin
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end
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endmodule
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module mux_case_unbal_7_7#(parameter N=7, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
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module mux_case_unbal_8_7#(parameter N=8, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
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always @* begin
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o <= {W{1'bx}};
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case (s)
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@ -120,7 +120,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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design -load read
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hierarchy -top mux_case_unbal_7_7
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hierarchy -top mux_case_unbal_8_7
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prep
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design -save gold
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muxpack
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