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Wire with init on FF part, 1'bx on non-FF part

This commit is contained in:
Eddie Hung 2019-08-24 15:05:44 -07:00
parent 10c41a5cf5
commit dc87372a97
1 changed files with 3 additions and 1 deletions
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4
tests/sat/initval.v
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@ -1,4 +1,4 @@
module test(input clk, input [3:0] bar, output [3:0] foo);
module test(input clk, input [3:0] bar, output [3:0] foo, asdf);
reg [3:0] foo = 0;
reg [3:0] last_bar = 0;
reg [3:0] asdf = 4'b1xxx;
@ -12,6 +12,8 @@ module test(input clk, input [3:0] bar, output [3:0] foo);
always @(posedge clk)
last_bar <= bar;
always @(posedge clk)
asdf[3] <= bar[3];
always @*
asdf[2:0] = 3'b111;