mirror of https://github.com/YosysHQ/yosys.git
Make tests/aiger less chatty
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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@ -10,8 +10,9 @@ for aag in *.aag; do
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# Since ABC cannot read *.aag, read the *.aig instead
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# (which would have been created by the reference aig2aig utility,
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# available from http://fmv.jku.at/aiger/)
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../../yosys-abc -c "read -c ${aag%.*}.aig; write ${aag%.*}_ref.v"
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../../yosys -p "
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echo "Checking $aag."
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../../yosys-abc -q "read -c ${aag%.*}.aig; write ${aag%.*}_ref.v"
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../../yosys -qp "
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read_verilog ${aag%.*}_ref.v
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prep
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design -stash gold
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@ -26,8 +27,9 @@ sat -verify -prove-asserts -show-ports -seq 16 miter
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done
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for aig in *.aig; do
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../../yosys-abc -c "read -c $aig; write ${aig%.*}_ref.v"
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../../yosys -p "
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echo "Checking $aig."
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../../yosys-abc -q "read -c $aig; write ${aig%.*}_ref.v"
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../../yosys -qp "
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read_verilog ${aig%.*}_ref.v
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prep
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design -stash gold
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