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Merge pull request #1150 from YosysHQ/eddie/script_from_wire 

Add "script -select [selection]" to allow commands to be taken from wires
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Eddie Hung 2019-07-02 10:20:42 -07:00 committed by GitHub
parent 0447794c51 81a717e9b7
commit 8455d1f4ff
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3 changed files with 60 additions and 8 deletions
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1
CHANGELOG
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@ -12,6 +12,7 @@ Yosys 0.9 .. Yosys 0.9-dev
- Added "synth_xilinx -abc9" (experimental)
- Added "synth_ice40 -abc9" (experimental)
- Added "synth -abc9" (experimental)
- Added "script -scriptwire
Yosys 0.8 .. Yosys 0.8-dev

47
kernel/yosys.cc
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@ -1254,24 +1254,55 @@ struct HistoryPass : public Pass {
#endif
struct ScriptCmdPass : public Pass {
ScriptCmdPass() : Pass("script", "execute commands from script file") { }
ScriptCmdPass() : Pass("script", "execute commands from file or wire") { }
void help() YS_OVERRIDE {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" script <filename> [<from_label>:<to_label>]\n");
log(" script -scriptwire [selection]\n");
log("\n");
log("This command executes the yosys commands in the specified file.\n");
log("This command executes the yosys commands in the specified file (default\n");
log("behaviour), or commands embedded in the constant text value connected to the\n");
log("selected wires.\n");
log("\n");
log("The 2nd argument can be used to only execute the section of the\n");
log("file between the specified labels. An empty from label is synonymous\n");
log("for the beginning of the file and an empty to label is synonymous\n");
log("for the end of the file.\n");
log("In the default (file) case, the 2nd argument can be used to only execute the\n");
log("section of the file between the specified labels. An empty from label is\n");
log("synonymous with the beginning of the file and an empty to label is synonymous\n");
log("with the end of the file.\n");
log("\n");
log("If only one label is specified (without ':') then only the block\n");
log("marked with that label (until the next label) is executed.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE {
if (args.size() < 2)
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
bool scriptwire = false;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
if (args[argidx] == "-scriptwire") {
scriptwire = true;
continue;
}
break;
}
if (scriptwire) {
extra_args(args, argidx, design);
for (auto mod : design->selected_modules())
for (auto &c : mod->connections()) {
if (!c.first.is_wire())
continue;
auto w = c.first.as_wire();
if (!mod->selected(w))
continue;
if (!c.second.is_fully_const())
log_error("RHS of selected wire %s.%s is not constant.\n", log_id(mod), log_id(w));
auto v = c.second.as_const();
Pass::call_on_module(design, mod, v.decode_string());
}
}
else if (args.size() < 2)
log_cmd_error("Missing script file.\n");
else if (args.size() == 2)
run_frontend(args[1], "script", design);

20
tests/various/script.ys Normal file
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@ -0,0 +1,20 @@
read_verilog -formal <<EOT
module top;
foo bar();
foo asdf();
winnie the_pooh();
wire [1023:0] _RUNME0 = "select -assert-count 2 t:foo";
wire [1023:0] _RUNME1 = "select -assert-count 1 t:winnie";
endmodule
module other;
wire [1023:0] _DELETE = "cd; delete c:bar";
endmodule
EOT
script -scriptwire w:_RUNME*
select w:_DELETE
script -scriptwire
select -assert-count 1 t:foo