Add shregmap -tech xilinx test

This commit is contained in:
Eddie Hung 2019-06-12 08:34:06 -07:00
parent 6cdea93724
commit 45c2a5f876
2 changed files with 63 additions and 2 deletions

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@ -1,4 +1,4 @@
module shregmap_test(input i, clk, output [1:0] q);
module shregmap_static_test(input i, clk, output [1:0] q);
reg head = 1'b0;
reg [3:0] shift1 = 4'b0000;
reg [3:0] shift2 = 4'b0000;
@ -20,3 +20,29 @@ always @(posedge C)
r <= { r[DEPTH-2:0], D };
assign Q = r[DEPTH-1];
endmodule
module shregmap_variable_test(input i, clk, input [1:0] l1, l2, output [1:0] q);
reg head = 1'b0;
reg [3:0] shift1 = 4'b0000;
reg [3:0] shift2 = 4'b0000;
always @(posedge clk) begin
head <= i;
shift1 <= {shift1[2:0], head};
shift2 <= {shift2[2:0], head};
end
assign q = {shift2[l2], shift1[l1]};
endmodule
module $__XILINX_SHREG_(input C, D, input [1:0] L, output Q);
parameter CLKPOL = 1;
parameter ENPOL = 1;
parameter DEPTH = 1;
parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
reg [DEPTH-1:0] r = INIT;
wire clk = C ^ CLKPOL;
always @(posedge C)
r <= { r[DEPTH-2:0], D };
assign Q = r[L];
endmodule

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@ -1,6 +1,8 @@
read_verilog shregmap.v
design -save read
design -copy-to model $__SHREG_DFF_P_
hierarchy -top shregmap_test
hierarchy -top shregmap_static_test
prep
design -save gold
@ -29,3 +31,36 @@ stat
design -load gate
stat
##########
design -load read
design -copy-to model $__XILINX_SHREG_
hierarchy -top shregmap_variable_test
prep
design -save gold
simplemap t:$dff t:$dffe
shregmap -tech xilinx
stat
# show -width
write_verilog -noexpr -norename
select -assert-count 1 t:$_DFF_P_
select -assert-count 2 t:$__XILINX_SHREG_
design -stash gate
design -import gold -as gold
design -import gate -as gate
design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_
prep
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports -seq 5 miter
design -load gold
stat
design -load gate
stat