mirror of https://github.com/YosysHQ/yosys.git
Remove ice40_unlut call, simply do equiv_opt on synth_ice40
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@ -1,4 +1,2 @@
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read_verilog opt_lut.v
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synth_ice40
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ice40_unlut
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equiv_opt -map +/ice40/cells_sim.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3
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equiv_opt -map +/ice40/cells_sim.v -assert synth_ice40
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