Marcelina Kościelnicka
0aec79a0da
show: Fix width labels.
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See #3266 .
2022-04-04 22:48:09 +02:00
Miodrag Milanovic
6020ba67ac
past_ad initial value setting
2022-04-02 19:13:15 +02:00
Miodrag Milanovic
2c96ecc5f7
setInitState can be only one altering values
2022-04-02 19:13:15 +02:00
Miodrag Milanovic
b54aecd80a
Set past_d value for init state
2022-04-02 19:13:15 +02:00
Jannis Harder
8ca9737180
Merge pull request #3264 from jix/invalid_ff_dcinit_merge
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opt_merge: Add `-keepdc` option required for formal verification
2022-04-02 12:41:28 +02:00
Jannis Harder
ca5b910296
opt_merge: Add `-keepdc` option required for formal verification
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The `-keepdc` option prevents merging flipflops with dont-care bits in
their initial value, as, in general, this is not a valid transform for
formal verification.
The keepdc option of `opt` is passed along to `opt_merge` now.
2022-04-01 21:03:20 +02:00
Miodrag Milanovic
86ce441af6
Set init values for wrapped async control signals
2022-04-01 17:44:00 +02:00
Miodrag Milanovic
c95b9b4ba5
Support memories in aiw and multiclock
2022-03-31 13:10:13 +02:00
Lofty
c1057cb3e0
Merge pull request #3194 from Ravenslofty/abc9-flow3mfs
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abc9: add flow3mfs script
2022-03-28 15:51:04 +01:00
gatecat
8b64dc1dce
abc9_ops: Also derive blackboxes with timing info
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-03-24 14:36:07 +00:00
Miodrag Milanovic
322ab1cd54
Proper SigBit forming in sim
2022-03-22 14:43:18 +01:00
Miodrag Milanovic
ff3b0c2c46
Proper SigBit forming in sim
2022-03-22 14:22:32 +01:00
Miodrag Milanovic
55eed8df57
More verbose warnings
2022-03-18 14:47:35 +01:00
Miodrag Milanovic
1f3423cd7d
Recognize registers and set initial state for them in tb
2022-03-16 14:35:39 +01:00
Miodrag Milanovic
e217e3017a
Update sim help message.
2022-03-16 07:55:57 +01:00
Miodrag Milanović
25d6fdfea7
Merge pull request #3232 from YosysHQ/micko/fst2tb
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Added fst2tb pass for generating testbench
2022-03-14 20:01:55 +01:00
Miodrag Milanovic
f5c20b8286
Added fst2tb pass for generating testbench
2022-03-14 19:06:29 +01:00
Claire Xen
5e2992dae2
Merge pull request #3213 from antonblanchard/abc-typo
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abc: Fix {I} and {P} substitution
2022-03-14 16:05:23 +01:00
Miodrag Milanović
cbece4af0c
Merge pull request #3229 from YosysHQ/micko/sim_date
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Add date parameter to enable full date/time and version info
2022-03-11 19:02:57 +01:00
Claire Xenia Wolf
e21badd4b3
Add "sim -q" option
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-03-11 16:26:11 +01:00
Miodrag Milanovic
37de369ba7
Add date parameter to enable full date/time and version info
2022-03-11 16:01:59 +01:00
Claire Xenia Wolf
be32de1caa
Small fix in "sim" help message
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-03-11 15:36:23 +01:00
Miodrag Milanovic
5204694123
FstData already do conversion to VCD
2022-03-11 15:21:36 +01:00
Miodrag Milanovic
b72c779204
Support cell name in btor witness file
2022-03-11 15:11:14 +01:00
Miodrag Milanovic
357336339a
Proper write of memory data
2022-03-11 11:19:53 +01:00
Miodrag Milanovic
295b0d1899
Start work on memory init
2022-03-09 18:34:02 +01:00
Miodrag Milanovic
f37ac5d934
Fixes and error check
2022-03-09 09:48:29 +01:00
Miodrag Milanovic
ede348cdc2
cleanup
2022-03-07 16:32:32 +01:00
Miodrag Milanovic
1b1ecd4ab0
Error checks for aiger witness
2022-03-07 15:00:14 +01:00
Miodrag Milanovic
b6aca1d743
btor2 witness co-simulation
2022-03-07 13:59:36 +01:00
Miodrag Milanović
9581b9adac
Merge pull request #3219 from YosysHQ/micko/quick_vcd
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VCD reader support by using external tool
2022-03-04 10:42:14 +01:00
Miodrag Milanovic
59983eda17
Add option to ignore X only signals in output
2022-03-02 16:02:13 +01:00
Miodrag Milanovic
48b56a4f7f
Write simulation files after simulation is performed
2022-03-02 15:23:07 +01:00
Miodrag Milanovic
28bc88a57e
Cleanup
2022-03-02 09:39:22 +01:00
Miodrag Milanovic
94505395a9
Refactor sim output writers
2022-02-28 18:22:39 +01:00
Miodrag Milanovic
dfd4c81eac
Quick fix
2022-02-28 11:40:06 +01:00
Claire Xenia Wolf
56b968f61c
Add writing of aiw files to "sim" command
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-02-28 10:50:08 +01:00
Claire Xenia Wolf
1fd3a642c9
Hotfix in AIGER witness reader state machine
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-02-28 10:41:44 +01:00
Miodrag Milanovic
8be09b5b24
VCD reader support by using external tool
2022-02-28 09:09:07 +01:00
Miodrag Milanovic
9571acc0bf
Support extended aiw format
2022-02-27 16:37:40 +01:00
Miodrag Milanovic
fca168797e
Fix for last clock edge data
2022-02-25 16:15:32 +01:00
Claire Xenia Wolf
ca261d3c28
Experimental sim changes
2022-02-25 16:02:06 +01:00
Anton Blanchard
89300b2dca
abc: Fix {I} and {P} substitution
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We were searching for {D} after the first match of {I} or {P}.
2022-02-23 18:54:28 +11:00
Claire Xen
a41c1df76f
Merge pull request #3211 from YosysHQ/micko/witness
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Add support for AIGER witness files in "sim" command
2022-02-22 16:22:06 +01:00
Miodrag Milanovic
fd3f08753a
Fix handling of ce_over_srst
2022-02-21 16:36:12 +01:00
Claire Xenia Wolf
1aa9ad25d0
Fix cycle 0 in aiger witness co-simulation
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-02-18 16:27:41 +01:00
Miodrag Milanovic
41754b4207
Added AIGER witness file co simulation
2022-02-18 15:04:02 +01:00
Miodrag Milanovic
13a5c28459
simplify logic of handling flip-flops and latches
2022-02-18 09:17:36 +01:00
Miodrag Milanovic
61752b255f
Review cleanup
2022-02-17 17:18:36 +01:00
Miodrag Milanovic
fb22d7cdc4
Add support for various ff/latch cells simulation
2022-02-16 13:27:59 +01:00
Claire Xen
49545c73f7
Merge branch 'master' into clk2ff-better-names
2022-02-11 16:03:12 +01:00
Claire Xen
e016518866
Merge pull request #2019 from boqwxp/glift
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Add `glift` command for creating gate-level information flow tracking models and optimization problems
2022-02-11 15:51:24 +01:00
bfg86
7ac98d1c87
Add -suffix option to rename -wire.
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See #3195
2022-02-11 00:05:13 +01:00
Lofty
5ac32ea68c
abc9: add flow3mfs script
2022-02-10 18:28:35 +00:00
Miodrag Milanović
d7f7227ce8
Merge pull request #3185 from YosysHQ/micko/co_sim
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Add co-simulation in sim pass
2022-02-07 16:36:43 +01:00
Miodrag Milanovic
c0a156bcb4
Error detection for co-simulation
2022-02-04 11:11:36 +01:00
Miodrag Milanovic
6db23de7b1
bug fix and cleanups
2022-02-04 10:01:06 +01:00
YRabbit
f5609d52c4
Correct a typo in the manual
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Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-02-02 21:14:38 +10:00
Miodrag Milanovic
990aee5531
respect hide_internal flag
2022-02-02 10:15:22 +01:00
Miodrag Milanovic
169ffcd2fb
unify cycles counting and cleanup
2022-02-02 10:08:23 +01:00
Miodrag Milanovic
820b2fdd65
added stimulus mode and param check
2022-02-02 09:37:32 +01:00
Scott Thibault
0a6e2bd5d5
Update comment
2022-02-02 03:21:09 +01:00
Scott Thibault
e04ac4e9e9
Fix unextend method for signed constants
2022-02-02 03:21:09 +01:00
Miodrag Milanovic
8ba2000a50
error when no signal found
2022-01-31 17:41:50 +01:00
Miodrag Milanovic
1b5ff92e62
Cleanup
2022-01-31 13:45:28 +01:00
Miodrag Milanovic
eabd0ff115
Compare bits when not all are defined
2022-01-31 13:41:02 +01:00
Miodrag Milanovic
26de52fa09
Cleanup
2022-01-31 12:00:15 +01:00
Miodrag Milanovic
6513300db7
message update
2022-01-31 11:41:52 +01:00
Miodrag Milanovic
543feb75cb
Display simulation time data
2022-01-31 10:52:47 +01:00
Miodrag Milanovic
a6959d30df
Use edges when explicit
2022-01-31 09:38:25 +01:00
Miodrag Milanovic
cbadfa0268
Updating initial state and checks
2022-01-31 09:19:34 +01:00
Miodrag Milanovic
190e44f0da
Fix scope
2022-01-31 08:56:29 +01:00
Marcelina Kościelnicka
07a657fb0c
opt_reduce: Add $bmux and $demux optimization patterns.
2022-01-30 03:37:52 +01:00
Marcelina Kościelnicka
93508d58da
Add $bmux and $demux cells.
2022-01-28 23:34:41 +01:00
Miodrag Milanovic
f04d1398e5
check if stop before start
2022-01-28 19:41:43 +01:00
Miodrag Milanovic
ecbba625c4
set initial state, only flip-flops
2022-01-28 15:59:13 +01:00
Miodrag Milanovic
cb12b7c4d8
ignore not found private signals
2022-01-28 14:20:16 +01:00
Miodrag Milanovic
81b76155d6
recursive check
2022-01-28 13:24:38 +01:00
Miodrag Milanovic
4f75a2ca1b
Do actual compare
2022-01-28 12:50:41 +01:00
Miodrag Milanovic
3e35de2be1
Add more options and time handling
2022-01-28 10:18:02 +01:00
Marcelina Kościelnicka
db33b1e535
opt_dff: Don't mutate muxes while ModWalker is active.
2022-01-28 08:55:56 +01:00
Marcelina Kościelnicka
1759c80a3f
memory_bram: Make use of new mem emulation functions to map more RAMs.
2022-01-27 19:31:27 +01:00
Miodrag Milanovic
40018e191b
Display values of outputs
2022-01-26 16:52:36 +01:00
Miodrag Milanovic
be7be63fec
Check if stimulated
2022-01-26 15:51:43 +01:00
Miodrag Milanovic
9a8939f0a4
Read fst and use data to set inputs
2022-01-26 15:50:38 +01:00
Miodrag Milanovic
ccfc00705a
Add ability to write to FST file
2022-01-26 09:26:19 +01:00
Austin Seipp
b022fe61a7
opt_dff: fix sequence point copy paste bug
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Newer GCCs emit the following warning for opt_dff:
passes/opt/opt_dff.cc:560:17: warning: operation on ‘ff.Yosys::FfData::has_clk’ may be undefined [-Wsequence-point]
560 | ff.has_clk = ff.has_ce = ff.has_clk = false;
| ~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Which is correct: the order of whether the read or write of has_clk
occurs first is undefined since there is no sequence point between them.
This is almost certainly just a typo/copy paste error and objectively
wrong, so just fix it.
Signed-off-by: Austin Seipp <aseipp@pobox.com>
2022-01-04 18:18:08 +01:00
Marcelina Kościelnicka
f84c9d8e17
memory_share: Fix SAT-based sharing for wide ports.
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Fixes #3117 .
2021-12-20 18:40:14 +01:00
Catherine
4f1d62d9b2
bugpoint: avoid infinite loop between -connections and -wires.
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Fixes #3113 .
2021-12-15 08:17:02 +00:00
Marcelina Kościelnicka
0aad88a2fb
Add clean_zerowidth pass, use it for Verilog output.
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This should remove instances of zero-width sigspecs in the netlist,
avoiding problems in the Verilog backend with emitting them.
See #3103 .
2021-12-12 19:56:50 +01:00
Marcelina Kościelnicka
1184a7f3b4
opt_mem_priority: Fix non-ascii char in help message.
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This is a fixed version of #3072 .
2021-12-09 00:56:14 +01:00
Lofty
77327b2544
sta: very crude static timing analysis pass
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Co-authored-by: Eddie Hung <eddie@fpgeh.com>
2021-11-25 17:20:27 +01:00
Marcelina Kościelnicka
107aad2cd2
show: Fix wire bit indexing.
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Fixes #3078 .
2021-11-12 15:09:58 +01:00
Claire Xen
4699ddcc1b
Merge pull request #3077 from YosysHQ/claire/genlib
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Add genlib support to ABC command
2021-11-10 20:02:34 +01:00
Claire Xen
c77d5a2aac
Spelling fix in abc.cc
2021-11-10 16:47:54 +01:00
Claire Xenia Wolf
093e287a1e
Add genlib support to ABC command
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-11-10 16:40:54 +01:00
Marcelina Kościelnicka
506acd52de
iopadmap: Fix ebmarassing typo
2021-11-10 14:56:03 +01:00
Marcelina Kościelnicka
15b0d717ed
iopadmap: Add native support for negative-polarity output enable.
2021-11-09 15:40:16 +01:00
Pepijn de Vos
0c7461fe5e
gowin: widelut support ( #3042 )
2021-11-06 16:09:30 +01:00
Miodrag Milanovic
d5de2a0cdb
Make it work on all
2021-11-05 10:51:58 +01:00
Miodrag Milanovic
cbb6887ac8
Correct way of setting maybe_unsused on labels
2021-11-05 10:36:15 +01:00
Marcelina Kościelnicka
f346868ccc
flatten: Keep sigmap around between flatten_cell invocations.
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Fixes #3064 .
2021-11-02 13:18:15 +01:00
Marcelina Kościelnicka
8d881826eb
proc_dff: Emit $aldff.
2021-10-27 14:14:24 +02:00
Marcelina Kościelnicka
0a0df8d38c
dfflegalize: Refactor, add aldff support.
2021-10-27 14:14:01 +02:00
Zachary Snow
e833c6a418
verilog: use derived module info to elaborate cell connections
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- Attempt to lookup a derived module if it potentially contains a port
connection with elaboration ambiguities
- Mark the cell if module has not yet been derived
- This can be extended to implement automatic hierarchical port
connections in a future change
2021-10-25 18:25:50 -07:00
Rupert Swarbrick
bd16d01c0e
Split out logic for reprocessing an AstModule
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This will enable other features to use same core logic for replacing an
existing AstModule with a newly elaborated version.
2021-10-25 18:25:50 -07:00
Marcelina Kościelnicka
5cebf6a8ef
Change implicit conversions from bool to Sig* to explicit.
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Also fixes some completely broken code in extract_reduce.
2021-10-21 20:20:31 +02:00
Marcelina Kościelnicka
e64456f920
extract_reduce: Refactor and fix input signal construction.
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Fixes #3047 .
2021-10-21 04:10:01 +02:00
Paul Annesley
3efc14f5ad
dfflegalize: remove redundant check for initialized dlatch
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This if condition is repeated verbatim, and I can't imagine a legitimate
way the inputs could change in between. I imagine it's a copy/paste
mistake.
2021-10-17 22:10:37 +02:00
Marcelina Kościelnicka
4e70c30775
FfData: some refactoring.
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- FfData now keeps track of the module and underlying cell, if any (so
calling emit on FfData created from a cell will replace the existing cell)
- FfData implementation is split off to its own .cc file for faster
compilation
- the "flip FF data sense by inserting inverters in front and after"
functionality that zinit uses is moved onto FfData class and beefed up
to have dffsr support, to support more use cases
2021-10-07 04:24:06 +02:00
Marcelina Kościelnicka
e7d89e653c
Hook up $aldff support in various passes.
2021-10-02 21:01:21 +02:00
Marcelina Kościelnicka
ba0723cad7
zinit: Refactor to use FfData.
2021-10-02 20:19:48 +02:00
Marcelina Kościelnicka
63b9df8693
kernel/ff: Refactor FfData to enable FFs with async load.
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- *_en is split into *_ce (clock enable) and *_aload (async load aka
latch gate enable), so both can be present at once
- has_d is removed
- has_gclk is added (to have a clear marker for $ff)
- d_is_const and val_d leftovers are removed
- async2sync, clk2fflogic, opt_dff are updated to operate correctly on
FFs with async load
2021-10-02 20:19:48 +02:00
Marcelina Kościelnicka
f9aad606ca
simplemap: refactor to use FfData.
2021-10-02 03:24:57 +02:00
Eddie Hung
96b6410dcb
abc9: make re-entrant ( #2993 )
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* Add testcase
* Cleanup some state at end of abc9
* Re-assign abc9_box_id from scratch
* Suppress delete unless prep_bypass did something
2021-09-09 10:06:31 -07:00
Eddie Hung
65316ec926
abc9: holes module to instantiate cells with NEW_ID ( #2992 )
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* Add testcase
* holes module to instantiate cells with NEW_ID
2021-09-09 10:06:20 -07:00
Eddie Hung
f03e2c30aa
abc9: replace cell type/parameters if derived type already processed ( #2991 )
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* Add close bracket
* Add testcase
* Replace cell type/param if in unmap_design
* Improve abc9_box error message too
* Update comment as per review
2021-09-09 10:05:55 -07:00
Marcelina Kościelnicka
9cbff3a4a9
opt_merge: Remove and reinsert init when connecting nets.
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Mutating the SigMap by adding a new connection will throw off FfInitVals
index. Work around this by removing the relevant init values from index
whenever we connect nets, then re-add the new init value.
Should fix #2920 .
2021-08-22 18:34:11 +02:00
Marcelina Kościelnicka
62d41d4639
opt_clean: Make the init attribute follow the FF's Q.
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Previously, opt_clean would reconnect all ports (including FF Q ports)
to a "canonical" SigBit chosen by complex rules, but would leave the
init attribute on the old wire. This change applies the same
canonicalization rules to the init attributes, ensuring that init moves
to wherever the Q port moved.
Part of another jab at #2920 .
2021-08-22 15:38:29 +02:00
Marcelina Kościelnicka
faacc7ad89
proc_prune: Make assign removal and promotion per-bit, remember promoted bits.
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Fixes #2962 .
2021-08-14 15:26:11 +02:00
Marcelina Kościelnicka
f791328506
Add opt_mem_widen pass.
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If all of us are wide, then none of us are!
2021-08-14 01:06:23 +02:00
Marcelina Kościelnicka
1f74ec3535
memory_share: Add -nosat and -nowiden options.
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This unlocks wide port recognition by default.
2021-08-14 00:09:04 +02:00
Marcelina Kościelnicka
9fdedf4d1c
memory_dff: Recognize soft transparency logic.
2021-08-13 23:08:32 +02:00
Marcelina Kościelnicka
616ace2d92
Add new opt_mem_priority pass.
2021-08-13 11:58:52 +02:00
Miodrag Milanović
30927df881
Merge pull request #2932 from YosysHQ/mwk/logger-check-expected
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logger: Add -check-expected subcommand.
2021-08-13 11:45:20 +02:00
Marcelina Kościelnicka
d0d9aca2c3
memory_share: Pass addresses through sigmap_xmux everywhere.
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This fixes wide port recognition in some cases.
2021-08-13 01:17:55 +02:00
Marcelina Kościelnicka
c58ac63c97
logger: Add -check-expected subcommand.
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This allows us to have multiple "expect this warning" calls in a single
long script, covering only as many passes as necessary.
2021-08-12 17:41:39 +02:00
Marcelina Kościelnicka
72d86c327e
memory_dff: Recognize read ports with reset / initial value.
2021-08-11 14:17:48 +02:00
Marcelina Kościelnicka
24027b5446
proc_memwr: Use the v2 memwr cell.
2021-08-11 13:34:10 +02:00
Marcelina Kościelnicka
fd79217763
Add v2 memory cells.
2021-08-11 13:34:10 +02:00
Marcelina Kościelnicka
e6f3d1c225
kernel/mem: Introduce transparency masks.
2021-08-11 00:04:16 +02:00
Marcelina Kościelnicka
d25b9088c8
Refactor common parts of SAT-using optimizations into a helper.
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This also aligns the functionality:
- in all cases, the onehot attribute is used to create appropriate
constraints (previously, opt_dff didn't do it at all, and share
created one-hot constraints based on $pmux presence alone, which
is unsound)
- in all cases, shift and mul/div/pow cells are now skipped when
importing the SAT problem (previously only memory_share did this)
— this avoids creating clauses for hard cells that are unlikely
to help with proving the UNSATness needed for optimization
2021-08-09 16:54:35 +02:00
Marcelina Kościelnicka
98003430d6
opt_merge: Use FfInitVals.
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Partial #2920 fix.
2021-08-08 01:19:22 +02:00
Marcelina Kościelnicka
63f9e0544f
memory_share: Don't skip ports with EN wired to input for SAT sharing.
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Fixes #2912 .
2021-08-04 04:47:43 +02:00
Marcelina Kościelnicka
8733e1923a
memory_bram: Move init data swizzling before other swizzling.
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Fixes #2907 .
2021-08-03 15:04:10 +02:00
Marcelina Kościelnicka
4451f7f5e9
memory_bram: Some refactoring
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This will make more sense when the new transparency masks land.
Fixes #2902 .
2021-08-01 16:51:24 +02:00
Zachary Snow
c016f6a423
proc_rmdead: use explicit pattern set when there are no wildcards
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If width of a case expression was large, explicit patterns could cause
the existing logic to take an extremely long time, or exhaust the
maximum size of the underlying set. For cases where all of the patterns
are fully defined and there are no constants in the case expression,
this change uses a simple set to track which patterns have been seen.
2021-07-29 20:55:59 -04:00
Marcelina Kościelnicka
54e75129e5
opt_lut: Allow more than one -dlogic per cell type.
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Fixes #2061 .
2021-07-29 17:30:07 +02:00
Marcelina Kościelnicka
19720b970d
memory: Introduce $meminit_v2 cell, with EN input.
2021-07-28 23:18:38 +02:00
Marcelina Kościelnicka
a0e912ba99
proc: Run opt_expr at the end
2021-07-27 20:44:45 +02:00
Marcelina Kościelnicka
436d42c00c
opt_expr: Propagate constants to port connections.
...
This adds one simple piece of functionality to opt_expr: when a cell
port is connected to a fully-constant signal (as determined by sigmap),
the port is reconnected directly to the constant value. This is just
enough optimization to fix the "non-constant $meminit input" problem
without requiring a full opt_clean or a separate pass.
2021-07-27 20:44:26 +02:00
Rupert Swarbrick
7a25246a7e
Use new read_id_num helper function elsewhere in hierarchy.cc
2021-07-20 10:13:15 -04:00
Rupert Swarbrick
8fd6b45a3c
Extract connection checking logic from expand_module in hierarchy.cc
...
No functional change, but pulls more logic out of the expand_module
function.
2021-07-20 10:13:15 -04:00
Rupert Swarbrick
7d50b83322
Extract missing module support in hierarchy.cc to a helper function
...
I think the code is now a bit easier to follow (and has lost some
levels of indentation!).
The only non-trivial change is that I removed the check for
cell->type[0] != '$' when deciding whether to complain if we couldn't
find a module. This will always be true because of the early exit
earlier in the function.
2021-07-14 22:54:50 -04:00
Rupert Swarbrick
88f20fa4dd
Delete unused found_init variable
...
Spotted during compilation:
passes/proc/proc_init.cc: In function ‘void {anonymous}::proc_init(Yosys::RTLIL::Module*, Yosys::SigMap&, Yosys::RTLIL::Process*)’:
passes/proc/proc_init.cc:31:7: warning: variable ‘found_init’ set but not used [-Wunused-but-set-variable]
2021-07-14 10:19:07 +01:00
Marcelina Kościelnicka
009940f56c
rtlil: Make Process handling more uniform with Cell and Wire.
...
- add a backlink to module from Process
- make constructor and destructor protected, expose Module functions
to add and remove processes
2021-07-12 00:47:34 +02:00
Rupert Swarbrick
e2c9580024
Move interface expansion in hierarchy.cc into a helper class
...
There should be no functional change, but this splits up the control
flow across functions, using class fields to hold the state that's
being tracked. The result should be a bit easier to read.
This is part of work to add bind support, but I'm doing some
refactoring in the hierarchy pass to make the code a bit easier to
work with. The idea is that (eventually) the IFExpander object will
hold all the logic for expanding interfaces, and then other code can
do bind insertion.
2021-06-16 21:48:18 -04:00
gatecat
6a6d049f1c
opt_muxtree: Update port_off and port_idx even for constant bits
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-11 12:06:35 +01:00
Marcelina Kościelnicka
1667ad658b
opt_expr: Fix mul/div/mod by POT patterns to support >= 32 bits.
...
The previous code, in addition to being needlessly limitted to 32 bits
in the first place, also had UB for the 31th bit (doing 1 << 31).
2021-06-09 19:53:44 +02:00
Marcelina Kościelnicka
12b3a9765d
opt_expr: Optimize div/mod by const 1.
...
Turns out the code for div by a power of 2 is already almost capable of
optimizing this to a shift-by-0 or and-with-0, which will be further
folded into nothingness; let's beef it up to handle div by 1 as well.
Fixes #2820 .
2021-06-09 17:42:30 +02:00
Claire Xen
55e8f5061a
Merge pull request #2817 from YosysHQ/claire/fixemails
...
Fixing old e-mail addresses and deadnames
2021-06-09 13:22:52 +02:00
Claire Xenia Wolf
588137cd08
Fix deadname SVN links
...
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-06-09 12:44:37 +02:00
Claire Xenia Wolf
0ada13cbe2
Use HTTPS for website links, gatecat email
...
git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g ;
2021-06-09 12:16:56 +02:00
Zachary Snow
d9f11bb7a6
autoname: simple perf optimizations
2021-06-08 15:02:42 -04:00
Claire Xenia Wolf
72787f52fc
Fixing old e-mail addresses and deadnames
...
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g ;
2021-06-08 00:39:36 +02:00
Marcelina Kościelnicka
13b901bf1c
memory_map: Improve start_offset handling.
...
Fixes #2775 .
2021-05-31 17:45:21 +02:00
Marcelina Kościelnicka
82f5829aba
memory_share: Add read port merging.
...
This is mostly meant for wide port recognition, but may also happen to
merge some ports with compatible initial/reset values (eg. 0 vs x).
2021-05-29 16:05:58 +02:00
Marcelina Kościelnicka
2d10caabbc
memory_share: Improve sat-based port sharing.
2021-05-28 14:25:33 +02:00
Marcelina Kościelnicka
cbf6b719fe
Make a few passes auto-call Mem::narrow instead of rejecting wide ports.
...
This essentially adds wide port support for free in passes that don't
have a usefully better way of handling wide ports than just breaking
them up to narrow ports, avoiding "please run memory_narrow" annoyance.
2021-05-28 00:40:56 +02:00
Marcelina Kościelnicka
1eae6025e7
memory_share: Improve same-address merging, recognize wide write ports.
2021-05-27 15:53:12 +02:00
Marcelina Kościelnicka
83a218141c
kernel/mem: Add sub_addr helpers.
2021-05-26 03:34:02 +02:00
Marcelina Kościelnicka
d99fce3bc7
mem/extract_rdff: Fix "no FF made" edge case.
...
When converting a sync transparent read port with const address to async
read port, nothing at all needs to be done other than clk_enable change,
and thus we have no FF cell to return. Handle this case correctly in
the helper and in its users.
2021-05-25 23:42:31 +02:00
Marcelina Kościelnicka
18806f1ef6
memory_bram: Reuse extract_rdff helper for make_outreg.
...
Also properly skip read ports with init value or reset when not making
use of make_outreg. Proper support for matching those will land later.
2021-05-25 22:42:03 +02:00
Marcelina Kościelnicka
e6b078d156
opt_mem: Add reset/init value support.
2021-05-25 20:06:00 +02:00
Marcelina Kościelnicka
96c7d60304
memory_bram: Respect write port priority.
2021-05-25 16:28:33 +02:00
Marcelina Kościelnicka
5628f5a88f
opt_mem_feedback: Respect write port priority.
2021-05-25 15:59:41 +02:00
Marcelina Kościelnicka
e0736c1622
Add memory_narrow pass.
2021-05-25 03:04:13 +02:00
Marcelina Kościelnicka
47f958ce45
memory_share: Add wide port support.
2021-05-25 02:57:32 +02:00
Marcelina Kościelnicka
9d5d5a48b1
opt_mem_feedback: Add wide port support.
2021-05-25 02:57:32 +02:00
Marcelina Kościelnicka
c1a4730739
memory_map: Add wide port support.
2021-05-25 02:57:32 +02:00
Marcelina Kościelnicka
1c903d3e47
sim: Add wide port support.
2021-05-25 02:57:32 +02:00
Marcelina Kościelnicka
69bf5c81c7
Reject wide ports in some passes that will never support them.
2021-05-25 02:07:25 +02:00
Marcelina Kościelnicka
835688bf80
opt_mem_feedback: Rewrite feedback path finding logic.
...
Fixes #2766 .
2021-05-24 23:20:30 +02:00
Marcelina Kościelnicka
b706adb809
opt_mem_feedback: Convert to Mem helpers.
2021-05-24 23:20:30 +02:00
Marcelina Kościelnicka
df2b79ca76
memory_share: Use Mem helpers.
2021-05-23 23:16:12 +02:00
Marcelina Kościelnicka
afd5366fc2
extract_rdff: Add initvals parameter.
...
This is not used yet, but will be needed when read port reset/initial
value support lands.
2021-05-23 22:05:26 +02:00
Marcelina Kościelnicka
d905990d01
memory_share: Split off feedback path finding as a separate pass.
...
memory_share is actually three passes in a trenchcoat. Split off the
one that has the least in common with the other two as a separate pass.
2021-05-23 18:30:39 +02:00
Marcelina Kościelnicka
1eea06bcc0
Add new helper class for merging FFs into cells, use for memory_dff.
...
Fixes #1854 .
2021-05-23 14:46:59 +02:00
Marcelina Kościelnicka
a23d9409e7
opt_mem: Remove write ports with const-0 EN.
...
Fixes #2765 .
2021-05-23 14:30:56 +02:00
Marcelina Kościelnicka
039f4f48d5
memory_memx: Use Mem helper.
2021-05-22 22:31:07 +02:00
Marcelina Kościelnicka
c4cc888b2c
kernel/rtlil: Extract some helpers for checking memory cell types.
...
There will soon be more (versioned) memory cells, so handle passes that
only care if a cell is memory-related by a simple helper call instead of
a hardcoded list.
2021-05-22 21:43:00 +02:00
Marcelina Kościelnicka
8c734e07b8
memory_dff: Use Mem helper.
2021-05-21 02:26:27 +02:00
Marcelina Kościelnicka
a6081b46ce
connect: Add -assert option, fix non-working sigmap.
...
Should be useful for writing tests.
2021-05-08 15:49:41 +02:00
Marcelina Kościelnicka
5c1e6a0e20
opt_dff: Fix NOT gates wired in reverse.
2021-05-04 21:03:40 +02:00
whitequark
c5c57e3f5e
flatten: rewrite memid in memwr actions.
2021-04-09 09:46:53 +00:00
Marcelina Kościelnicka
b7ea71e6e3
equiv: Suggest running async2sync or clk2fflogic where appropriate.
...
See #2713 .
2021-03-30 18:20:21 +02:00
Eddie Hung
8c5f379435
abc9: uniquify blackboxes like whiteboxes ( #2695 )
...
* abc9_ops: uniquify blackboxes too
* abc9_ops: update comment
* abc9_ops: allow bypass for param-less blackboxes
* Add tests
2021-03-29 22:02:06 -07:00
Eddie Hung
55dc5a4e4f
abc9: fix SCC issues ( #2694 )
...
* xilinx: add SCC test for DSP48E1
* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1
Have a test that checks it works through ABC9 when enabled
* abc9 to break SCCs using $__ABC9_SCC_BREAKER module
* Add test
* abc9_ops: remove refs to (* abc9_keep *) on wires
* abc9_ops: do not bypass cells in an SCC
* Add myself to CODEOWNERS for abc9*
* Fix compile
* abc9_ops: run -prep_hier before scc
* Fix tests
* Remove bug reference pending fix
* abc9: fix for -prep_hier -dff
* xaiger: restore PI handling
* abc9_ops: -prep_xaiger sigmap
* abc9_ops: -mark_scc -> -break_scc
* abc9: eliminate hard-coded abc9.box from tests
Also tidy up
* Address review
2021-03-29 22:01:57 -07:00
Iris Johnson
4c39189b13
Clarify bugpoint documentation regarding output
...
Bugpoint's current documentation does specify that the result of a run is stored as the current design,
however it's easy to skim over what that means in practice.
Add a documentation comment to explain specifically that an after bugpoint `write_xyz` pass is required to save
the reduced design.
2021-03-24 16:24:33 -05:00
Zachary Snow
c8b45a4a82
bugpoint: add runner option
2021-03-17 15:54:00 -04:00
gatecat
dd6d34f461
blackbox: Include whiteboxed modules
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-17 13:58:04 +00:00
Marcelina Kościelnicka
a55bf6375b
proc_arst: Add special-casing of clock signal in conditionals.
...
The already-existing special case for conditionals on clock has been
remade as follows:
- now triggered for the last remaining edge trigger after all others
have been converted to async reset, not just when there is only one
sync rule in the first place
- does not require all contained assignments to be constant, as opposed
to a reset conditional — merely const-folds the condition
In addition, the code has been refactored a bit; as a bonus, the
priority order of async resets found is now preserved in resulting sync
rule ordering (though this is not yet respected by proc_dff).
Fixes #2656 .
2021-03-15 17:17:29 +01:00
Marcelina Kościelnicka
3af871f969
opt_clean: Remove init attribute bits together with removed DFFs.
...
Fixes #2546 .
2021-03-15 17:16:53 +01:00
Miodrag Milanovic
81c2b92bb4
Add _pm.h files to GENLIST, fixes vcxsrc target
2021-03-11 15:56:32 +01:00
Marcelina Kościelnicka
a3528649c8
memory_dff: Remove now-useless write port handling.
2021-03-08 20:16:29 +01:00
Marcelina Kościelnicka
4e03865d5b
Add support for memory writes in processes.
2021-03-08 20:16:29 +01:00
Marcelina Kościelnicka
c00a29296c
sim: Avoid a crash on empty cell connection.
...
Fixes #2513 .
2021-03-08 17:03:31 +01:00
Marcelina Kościelnicka
760284033d
proc_dff: Fix emitted FF when a register is not assigned in async reset
...
Fixes #2619 .
2021-03-08 17:01:43 +01:00
Marcelina Kościelnicka
bc717abad2
memory_dff: Remove code looking for $mux cells.
...
This job is now performed by `opt_dff`, which runs before this pass.
2021-03-08 16:58:12 +01:00
Dan Ravensloft
9cdc6b5f2e
Replace assert in abc9_ops with more useful error message
2021-03-07 18:52:14 +01:00
Marcelina Kościelnicka
d245e2bae5
proc_clean: Fix empty case removal conditions.
...
Fixes #2639 .
2021-03-06 17:39:50 +01:00
Noah Moroze
90b40aa51f
clk2fflogic: nice names for autogenerated signals
2021-03-02 18:28:56 -05:00
Marcelina Kościelnicka
4746ffd7b2
assertpmux: Fix crash on unused $pmux output.
...
Fixes #2595 .
2021-02-22 23:30:28 +01:00
Robert Baruch
1d79222af4
Fixes command line for abc pass in -fast -sop mode
2021-02-16 16:34:09 -08:00
whitequark
baf1875307
Merge pull request #2529 from zachjs/unnamed-genblk
...
verilog: significant block scoping improvements
2021-02-04 09:57:28 +00:00
Zachary Snow
fe74b0cd95
verilog: significant block scoping improvements
...
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-31 09:42:09 -05:00
whitequark
708eb327a1
Merge pull request #2564 from whitequark/flatten-improve-error
...
flatten: clarify confusing error message
2021-01-29 02:55:51 +00:00
Claire Xen
d0d7a360ed
Merge pull request #2535 from Ravenslofty/scc-specify
...
scc: Add -specify option to find loops in boxes
2021-01-28 19:01:29 +01:00
whitequark
2364820f50
flatten: clarify confusing error message.
2021-01-26 18:29:53 +00:00
Dan Ravensloft
74dad5afe7
scc: Add -specify option to find loops in boxes
2021-01-26 16:23:08 +00:00
whitequark
f200a8fe1c
Merge pull request #2549 from pgadfort/support-multiple-libs
...
adding support for passing multiple liberty files to abc
2021-01-25 10:36:14 +00:00
Miodrag Milanović
bfa353f154
Merge pull request #2536 from TobiasFaller/master
...
Fixed missing goto statement in passes/techmap/abc.cc
2021-01-20 20:42:02 +01:00
Peter Gadfort
169234d6e9
adding support for passing multiple liberty files to abc
2021-01-18 16:47:49 -05:00
Marcelina Kościelnicka
01626e6746
opt_share: Fix X and CO signal width for shifted $alu in opt_share.
...
These need to be the same length as actual Y, not visible part of Y.
Fixes #2538 .
2021-01-14 14:54:08 +01:00
Tobias Faller
760a2c1343
Fixed missing goto statement in passes/techmap/abc.cc
2021-01-12 16:17:51 +01:00
umarcor
e61b107072
plugin: enhance no-plugin error
2020-12-29 05:50:04 +01:00
Larry Doolittle
84c0b5c690
passes/pmgen/pmgen.py: trivial change to remove C++ compiler warnings
...
Verified that the result still builds and passes self-tests
2020-12-23 14:38:25 -08:00
StefanBruens
9396678db4
Fix use-after-free in LUT opt pass
...
RTLIL::Module::remove(Cell* cell) calls `delete cell`.
Any subsequent accesses of `cell` then causes undefined behavior.
2020-12-22 03:23:42 +01:00
Zachary Snow
0d8e5d965f
Sign extend port connections where necessary
...
- Signed cell outputs are sign extended when bound to larger wires
- Signed connections are sign extended when bound to larger cell inputs
- Sign extension is performed in hierarchy and flatten phases
- genrtlil indirects signed constants through signed wires
- Other phases producing RTLIL may need to be updated to preserve
signedness information
- Resolves #1418
- Resolves #2265
2020-12-18 20:33:14 -07:00
Miodrag Milanovic
82dcf78cd9
Return nice error in pmgen generated code, fixes #2482
2020-12-09 11:06:22 +01:00
whitequark
1838edf35c
bugpoint: add -wires option.
2020-12-07 09:24:35 +00:00
whitequark
2b474a01e1
bugpoint: try to remove whole processes first.
2020-12-07 08:42:54 +00:00
whitequark
b1135a88dd
bugpoint: accept quoted strings in -grep.
2020-12-07 08:42:54 +00:00
whitequark
75f9e9cb45
bugpoint: add -command option.
2020-12-07 08:42:54 +00:00
Gabriel Somlo
150b729b6f
Add #include needed to build with gcc-11
...
Suggested by Jeff Law <law@redhat.com>
2020-11-26 06:12:12 -05:00
whitequark
2a39c785a2
Merge pull request #2450 from nitz/sim-vcd-filename
...
Add rewrite_filename for sim -vcd argument.
2020-11-25 02:48:10 +00:00
Chris Dailey
cdc802e4b7
Add rewrite_filename for sim -vcd argument.
2020-11-24 15:17:16 -05:00
whitequark
bc085761e6
Merge pull request #2428 from whitequark/check-processes
...
check: add support for processes
2020-11-24 15:04:42 +00:00
Miodrag Milanovic
829b5cca60
Expose abc and data paths as globals
2020-11-06 14:17:15 +01:00
whitequark
d6a93b8b90
check: add support for processes.
2020-11-03 15:36:27 +00:00
whitequark
191406f930
check: reformat log/help text to match most other passes
2020-11-03 12:37:02 +00:00
Ethan Mahintorabi
5c36e7757c
This patch adds support for defining the ABC location at runtime instead of at compile time. This is helpful in build systems like bazel which do not have stable locations for binaries or directories during the compilation phase.
...
This change should be backwards compatible with the existing behavior.
2020-10-28 19:00:06 -07:00
N. Engelhardt
3b86b5da5f
Merge pull request #2403 from nakengelhardt/sim_timescale
...
sim -vcd: add date, version, and option for timescale
2020-10-22 14:01:24 +02:00
Marcelina Kościelnicka
eb76d35e80
memory_dff: Fix needlessly duplicating enable bits.
...
When the register being merged into the EN signal happens to be a $sdff,
the current code creates a new $mux for every bit, even if they happen
to be identical (as is usually the case), preventing proper grouping
further down the flow. Fix this by adding a simple cache.
Fixes #2409 .
2020-10-22 13:03:42 +02:00
Marcelina Kościelnicka
b065e09045
sim: Use Mem helper.
2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka
e759e301a8
clk2fflogic: Use Mem helper.
2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka
06141db233
opt_mem: Use Mem helpers.
2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka
21896e2a02
memory_bram: Use Mem helpers.
2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka
1e8098279f
memory_map: Use Mem helpers.
2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka
d390b380e1
memory_unpack: Use Mem helpers.
2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka
e9978aaf15
memory_collect: Use Mem helpers.
2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka
248b193d6d
memory_nordff: Use Mem helpers.
2020-10-21 17:51:20 +02:00
N. Engelhardt
1c96a0b1d5
use strftime instead of put_time for gcc 4.8 compatibility
2020-10-21 17:47:00 +02:00
N. Engelhardt
eccc48c39f
wild guessing at the problem because it builds fine on my machines
2020-10-16 18:46:59 +02:00
N. Engelhardt
668d5253a5
sim -vcd: add date, version, and option for timescale
2020-10-16 18:19:58 +02:00
Marcelina Kościelnicka
7670a89e1f
opt_clean: Better memory handling.
...
Previously, `$memwr` and `$meminit` cells were always preserved (along
with the memory itself). With this change, they are instead part of the
main cell mark-and-sweep pass: a memory (and its `$meminit` and `$memwr`
cells) is only preserved iff any associated `$memrd` cell needs to be
preserved.
2020-10-08 18:05:51 +02:00
Miodrag Milanovic
412332fdb3
Validate parameters only when they are used
2020-09-25 11:40:37 +02:00
N. Engelhardt
3238190797
use the new isPublic() in a few places
2020-09-14 12:43:18 +02:00
whitequark
2d10d59d93
Merge pull request #2356 from whitequark/flatten-techmap-no-tpl_driven-sigmap
...
flatten, techmap: don't canonicalize tpl driven bits via sigmap
2020-08-27 11:28:31 +00:00
whitequark
702f7c0253
Merge pull request #2358 from whitequark/rename-ilang-to-rtlil
...
Replace "ILANG" with "RTLIL" everywhere
2020-08-27 11:24:06 +00:00
Marcelina Kościelnicka
880df4c897
dfflegalize: Fix decision tree for adffe.
...
When an adffe is being legalized, and is not natively supported,
prioritize unmapping to adff over converting to dffsre if dffsre is not
natively supported itself.
Fixes #2361 .
2020-08-27 13:17:42 +02:00
whitequark
00e7dec7f5
Replace "ILANG" with "RTLIL" everywhere.
...
The only difference between "RTLIL" and "ILANG" is that the latter is
the text representation of the former, as opposed to the in-memory
graph representation. This distinction serves no purpose but confuses
people: it is not obvious that the ILANG backend writes RTLIL graphs.
Passes `write_ilang` and `read_ilang` are provided as aliases to
`write_rtlil` and `read_rtlil` for compatibility.
2020-08-26 17:29:32 +00:00
whitequark
9f0892159e
flatten, techmap: don't canonicalize tpl driven bits via sigmap.
...
For connection `assign a = b;`, `sigmap(a)` returns `b`. This is
exactly the opposite of the desired canonicalization for driven bits.
Consider the following code:
module foo(inout a, b);
assign a = b;
endmodule
module bar(output c);
foo f(c, 1'b0);
endmodule
Before this commit, the inout ports would be swapped after flattening
(and cause a crash while attempting to drive a constant value).
This issue was introduced in 9f772eb9
.
Fixes #2183 .
2020-08-26 16:29:42 +00:00
Peder Bergebakken Sundt
656ee70f8e
proc: Add -nomux switch
...
running proc -nomux will ommit the proc_mux pass
2020-08-20 22:58:08 +02:00
clairexen
a96df40814
Merge pull request #2344 from YosysHQ/mwk/opt_share-fixes
...
opt_share: Refactor, fix some bugs.
2020-08-20 16:24:53 +02:00
clairexen
1d0d9d5c86
Merge pull request #2337 from YosysHQ/mwk/clean-keep-wire
...
opt_clean: Fix module keep rules.
2020-08-20 16:23:55 +02:00
clairexen
799076af24
Merge pull request #2333 from YosysHQ/mwk/peepopt-shiftmul-signed
...
peeopt.shiftmul: Add a signedness check.
2020-08-20 16:23:07 +02:00
clairexen
6a68b8ed54
Merge pull request #2328 from YosysHQ/mwk/opt_dff-cleanup
...
Remove passes redundant with opt_dff
2020-08-20 16:21:58 +02:00
clairexen
faf8e19511
Merge pull request #2327 from YosysHQ/mwk/techmap-constmap-fix
...
techmap.CONSTMAP: Handle outputs before inputs.
2020-08-20 16:21:09 +02:00
clairexen
16bb3fc8bb
Merge pull request #2326 from YosysHQ/mwk/peeopt-muldiv-sign
...
peepopt.muldiv: Add a signedness check.
2020-08-20 16:19:37 +02:00
clairexen
1cdb533fa5
Merge pull request #2319 from YosysHQ/mwk/techmap-celltype-pattern
...
techmap: Add support for [] wildcards in techmap_celltype.
2020-08-20 16:18:40 +02:00
Xiretza
916028906a
Ensure \A_SIGNED is never used with $shiftx
...
It has no effect on the output ($shiftx doesn't perform any sign
extension whatsoever), so an attempt to use it should be caught early.
2020-08-18 19:36:24 +02:00
Marcelina Kościelnicka
2b777bbda8
opt_share: Refactor, fix some bugs.
...
Fixes #2334 .
Fixes #2335 .
Fixes #2336 .
2020-08-17 17:26:36 +02:00
Marcelina Kościelnicka
2ab350a7b0
opt_clean: Fix module keep rules.
...
- wires with keep attribute now force a module to be kept
- presence of $memwr and $meminit cells no longer forces a module to be
kept
2020-08-09 13:57:00 +02:00
Marcelina Kościelnicka
54a0c083a1
Remove now-redundant dff2dffe pass.
2020-08-07 13:21:34 +02:00
Marcelina Kościelnicka
5693386a4e
Remove now-redundant dff2dffs pass.
2020-08-07 13:21:34 +02:00
Marcelina Kościelnicka
a0e99a9f3f
peepopt: Remove now-redundant dffmux pattern.
2020-08-07 13:21:34 +02:00
Marcelina Kościelnicka
acd8c5c205
Remove now-redundant opt_rmdff pass.
2020-08-07 13:21:34 +02:00
Marcelina Kościelnicka
9a4f420b4b
Replace opt_rmdff with opt_dff.
2020-08-07 13:21:03 +02:00
Marcelina Kościelnicka
c1ed1c28be
peeopt.shiftmul: Add a signedness check.
...
Fixes #2332 .
2020-08-05 21:01:20 +02:00
Marcelina Kościelnicka
b4a4cb081d
techmap.CONSTMAP: Handle outputs before inputs.
...
Fixes #2321 .
2020-08-05 12:28:18 +02:00
Marcelina Kościelnicka
e89cc9c02f
peepopt.muldiv: Add a signedness check.
...
Fixes #2318 .
2020-08-04 16:30:24 +02:00
Marcelina Kościelnicka
522788f016
techmap: Add support for [] wildcards in techmap_celltype.
...
Fixes #1826 .
2020-08-02 22:46:48 +02:00
Marcelina Kościelnicka
18ad56ef41
Add dffunmap pass.
...
To be used with backends that cannot deal with fancy FF types (like blif
or smt).
2020-07-31 00:59:51 +02:00
Marcelina Kościelnicka
6cd135a5eb
opt_expr: Remove -clkinv option, make it the default.
...
Adds -noclkinv option just in case the old behavior was actually useful
to someone.
2020-07-31 00:08:15 +02:00
Marcelina Kościelnicka
cf60699884
synth_ice40: Use opt_dff.
...
The main part is converting ice40_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the mux patterns on
its own.
The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.
2020-07-30 22:26:20 +02:00
Marcelina Kościelnicka
8501342fc5
synth_xilinx: Use opt_dff.
...
The main part is converting xilinx_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the patterns on its
own.
The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.
2020-07-30 22:26:09 +02:00
Marcelina Kościelnicka
4a05cad7f8
async2sync: Support all FF types.
2020-07-30 20:22:03 +02:00
Marcelina Kościelnicka
af6623ebb8
Add opt_dff pass.
2020-07-30 18:27:04 +02:00
Marcelina Kościelnicka
dc18bf1969
opt_expr: Fix handling of $_XNOR_ cells with A = B.
...
Fixes #2311 .
2020-07-29 12:41:43 +02:00
Marcelina Kościelnicka
a1a0abf52a
equiv_induct: Fix up assumption for $equiv cells in -undef mode.
...
Before this fix, equiv_induct only assumed that one of the following is
true:
- defined value of A is equal to defined value of B
- A is undefined
This lets through valuations where A is defined, B is undefined, and
the defined (meaningless) value of B happens to match the defined value
of A. Instead, tighten this up to OR of the following:
- defined value of A is equal to defined value of B, and B is not
undefined
- A is undefined
2020-07-27 18:36:13 +02:00
Marcelina Kościelnicka
bd959d5d9e
async2sync: Refactor to use FfInitVals.
2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka
c9251eb26b
memory_dff: Refactor to use FfInitVals.
2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka
557f81cb49
proc_dlatch: Refactor to use FfInitVals.
2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka
31d6107521
pmux2shift: Refactor to use FfInitVals.
2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka
4d9105ccb0
wreduce: Refactor to use FfInitVals.
2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka
7b1a4fc1e6
techmap: Refactor to use FfInitVals.
2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka
9e72be3ae8
shregmap: Refactor to use FfInitVals.
2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka
522f367db3
abc: Refactor to use FfInitVals.
2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka
336b8c7786
dffinit: Refactor to use FfInitVals.
2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka
1c8483b7dd
zinit: Refactor to use FfInitVals.
2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka
e98382f6e2
dfflegalize: Refactor to use FfInitVals.
2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka
abe4e9e607
clk2fflogic: Support all FF types.
2020-07-24 03:19:48 +02:00
Marcelina Kościelnicka
eae2edf3e4
memory_dff: recognize more dff cells
2020-07-23 20:55:28 +02:00
Marcelina Kościelnicka
dc07ae9677
techmap: Add _TECHMAP_CELLNAME_ special parameter.
...
This parameter will resolve to the name of the cell being mapped. The
first user of this parameter will be synth_intel_alm's Quartus output,
which requires a unique (and preferably descriptive) name passed as
a cell parameter for the memory cells.
2020-07-21 15:00:54 +02:00
Alberto Gonzalez
2f786fcfac
qbfsat: Add `-solver-option` option.
2020-07-20 21:54:56 +00:00
Marcelina Kościelnicka
61a7ec4768
opt_merge: Dedup one more use of FF cell type list.
2020-07-15 06:19:18 +02:00
Marcelina Kościelnicka
b33744b03a
proc_dlatch: Remove init values for combinatorial processes.
...
Fixes #2258 .
2020-07-12 18:50:30 +02:00
Marcelina Kościelnicka
240351c44e
dfflegalize: Gather init values from all wires.
...
Skipping non-selected wires is unsound in an obvious way.
2020-07-12 17:39:13 +02:00
Marcelina Kościelnicka
7ed9d18907
dfflibmap: Refactor to use dfflegalize internally.
2020-07-09 18:51:03 +02:00
Marcelina Kościelnicka
32d2cc8c28
clkbufmap: improve input pad handling.
...
- allow inserting only the input pad cell
- do not insert the usual buffer if the input pad already acts as a
buffer
2020-07-09 18:48:01 +02:00
Marcelina Kościelnicka
03e28f7ab4
clk2fflogic: Consistently treat async control signals as negative hold.
...
This fixes some dfflegalize equivalence checks, and breaks others — and
I strongly suspect the others are due to bad support for multiple
async inputs in `proc` (in particular, lack of proper support for
dlatchsr and sketchy circuits on dffsr control inputs).
2020-07-09 18:12:47 +02:00
Marcelina Kościelnicka
e9c2c1b717
dfflegalize: Add special support for const-D latches.
...
Those can be created by `opt_dff` when optimizing `$adff` with const
clock, or with D == Q. Make dfflegalize do the opposite transform
when such dlatches would be otherwise unimplementable.
2020-07-09 18:11:32 +02:00
Marcelina Kościelnicka
943147b768
dfflegalize: typo fix
2020-07-07 15:00:52 +02:00
Marcelina Kościelnicka
af54b8bc61
Naming fixes.
2020-07-05 22:21:59 +02:00
Marcelina Kościelnicka
f3f55ae7c2
dfflegalize: Prefer mapping dff to sdff before adff
...
This ensures that, when both sync and async FFs are available and abc9
is involved, the sync FFs will be used, and will thus remain available
for sequential synthesis.
2020-07-05 12:01:43 +02:00
Marcelina Kościelnicka
7afcb72c98
opt_expr: Fix crash on $mul optimization with more zeros removed than Y has.
...
Fixes #2221 .
2020-07-05 06:31:58 +02:00
Eddie Hung
27a9d1b6e6
abc9: only techmap (* abc9_flop *) modules
2020-07-04 19:45:10 +02:00
Eddie Hung
0ba79feb6f
abc9: techmap from user design to allow abc9_flop modules to be composed
...
from other primitives
2020-07-04 19:45:10 +02:00
Rupert Swarbrick
a9b61080a4
Add newlines to help text for dfflegalize
...
I think these were probably missed by accident. Spotted because GCC
spits out lots of messages like this:
passes/techmap/dfflegalize.cc:114:7: warning: zero-length gnu_printf format string [-Wformat-zero-length]
114 | log("");
| ^~
(because we tell GCC that the first argument to log() looks like a
printf control string in log.h, and a zero length such string triggers
a warning).
2020-07-03 12:30:12 +02:00
clairexen
e4b9e64d1b
Merge pull request #2208 from boqwxp/qbfsat-cleanup
...
qbfsat: Cleanup and refactoring
2020-07-02 17:48:37 +02:00
clairexen
5428666151
Merge pull request #2186 from YosysHQ/mwk/dfflegalize
...
Add dfflegalize pass.
2020-07-02 17:46:11 +02:00
clairexen
d3422f8a5e
Merge pull request #2211 from YosysHQ/mwk/fix-fmcombine-ff
...
fmcombine: use the master ff cell type list
2020-07-02 17:43:48 +02:00
clairexen
5dbf91847a
Merge pull request #2210 from YosysHQ/mwk/fix-opt_merge
...
opt_merge: use the master FF type list
2020-07-02 17:43:34 +02:00
Alberto Gonzalez
56f98b9e3d
qbfsat: Remove useless comment and #ifndef guards.
2020-07-01 19:55:16 +00:00
Alberto Gonzalez
3345d39e6f
qbfsat: Specify default values for some options in the help message.
2020-07-01 19:55:16 +00:00
Alberto Gonzalez
95e8016811
qbfsat: Clean up external executable command lines and update temporary directory name.
2020-07-01 19:55:16 +00:00
Alberto Gonzalez
8cd60be654
qbfsat: Clean up and refactor data structures into `qbfsat.h`.
2020-07-01 19:55:16 +00:00
Alberto Gonzalez
bbfa2d65fa
glift: Use ID() rather than string literals.
2020-07-01 19:51:48 +00:00
Alberto Gonzalez
eda1af73c4
glift: Use worker pattern.
2020-07-01 19:51:47 +00:00
Alberto Gonzalez
3eb2593876
glift: Add support for $_NAND_ and $_NOR_ cells.
2020-07-01 19:51:47 +00:00
Alberto Gonzalez
8cb1a86c23
glift: Add support for $_MUX_ and $_NMUX_ cells.
2020-07-01 19:51:47 +00:00
Alberto Gonzalez
23defc6fe9
glift: Add support for $_XOR_ and $_XNOR_ cells.
2020-07-01 19:51:47 +00:00
Alberto Gonzalez
209a123b97
glift: Add initial hierarchy support.
2020-07-01 19:51:47 +00:00
Alberto Gonzalez
20ad371724
glift: Replace `YS_OVERRIDE` with `override`.
2020-07-01 19:51:47 +00:00
Alberto Gonzalez
91c20fca72
glift: Add `-simple-cost-model` option
...
Rather than assigning specific weights to specific versions of taint tracking logic and summing the weights of all GLIFT cells, sum the following values for each GLIFT cell:
- 0 if the associated hole/$anyconst cell value is non-zero, i.e. reduced-precision taint tracking logic is chosen at this cell
- 1 if the associated hole/$anyconst cell value is zero, i.e. the full-precision taint tracking logic is chosen at this cell
This simplified cost modeling reduces the potential for the QBF-SAT solver to minimize taint tracking logic area but significantly simplifies the QBF-SAT problem.
2020-07-01 19:51:47 +00:00
Alberto Gonzalez
26bd686259
glift: Add `-instrument-more` option to add 4 more versions of taint tracking logic. Also refactor a bit and update help text.
2020-07-01 19:51:46 +00:00
Alberto Gonzalez
bc207d5426
glift: Change command names to better represent their functions.
2020-07-01 19:51:46 +00:00
Alberto Gonzalez
ddfb9f08e2
glift: Add `-create-imprecise` command, rename other commands, and re-work the help text.
2020-07-01 19:51:46 +00:00
Alberto Gonzalez
72cebef279
glift: Add replacement scoring and area minimization option.
2020-07-01 19:51:46 +00:00
Alberto Gonzalez
c36440a7ee
glift: Remove outputs by default; add `-keep-outputs` option; properly reset internal state between calls.
2020-07-01 19:51:46 +00:00
Alberto Gonzalez
19dafcd4f1
glift: Initial implementation of the `-sketchify` option.
2020-07-01 19:51:46 +00:00
Alberto Gonzalez
09848b3b9f
glift: Initial implementation of GLIFT model construction.
2020-07-01 19:51:45 +00:00
Alberto Gonzalez
5f45fe51ea
glift: Add skeleton for `glift` command.
2020-07-01 19:51:45 +00:00
clairexen
b1707407a0
Merge pull request #2138 from boqwxp/qbfsat-oflag
...
qbfsat: Add `-O[012]` options to control pre-solving simplification with ABC
2020-07-01 16:35:27 +02:00
clairexen
2b0f6e24e2
Merge pull request #2206 from boqwxp/qbfsat-fix-name-specialization
...
qbfsat: Fix name-based hole specialization
2020-07-01 16:34:32 +02:00
Marcelina Kościelnicka
e3564b4502
Add dfflegalize pass.
2020-07-01 01:57:15 +02:00
Marcelina Kościelnicka
7c91f13f51
fmcombine: use the master ff cell type list
2020-06-30 21:07:17 +02:00
Marcelina Kościelnicka
77b15dd8e9
opt_merge: use the master FF type list
2020-06-30 20:57:35 +02:00
clairexen
3fb5b4fd8a
Merge pull request #2199 from YosysHQ/mmicko/sim_memory
...
sim - error when memrd and memwr detected
2020-06-30 17:12:51 +02:00
clairexen
275cee71f6
Merge pull request #2201 from YosysHQ/fix_test_cell_ilang
...
Use ID macro to fix assertion
2020-06-30 17:11:13 +02:00
Alberto Gonzalez
83c595aaac
qbfsat: Add `-O[012]` options to control pre-solving simplification with ABC.
...
Thanks to @mwk for the gate mapping part of the ABC scripts.
Co-Authored-By: Marcelina Kościelnicka <mwk@0x04.net>
2020-06-30 06:44:17 +00:00
Alberto Gonzalez
f544a2cc84
qbfsat: Fix name-based hole specialization.
...
Look for unique connections in the containing module with the $anyconst port Y SigBit on the RHS and use those. If no such connection is found, fall back to using the name of the $anyconst port Y SigBit.
2020-06-30 01:53:21 +00:00
whitequark
a97c13f0ca
techmap: don't drop attributes on replaced cells.
...
This was introduced in 76c4ee4ea5
.
Fixes #2204 .
2020-06-29 23:14:13 +00:00
Miodrag Milanović
4160acc0b1
Merge pull request #2200 from YosysHQ/mmicko/fix_expose
...
expose pass fix
2020-06-29 15:16:29 +02:00
Miodrag Milanovic
405b4e97a1
Give error that options are exclusive
2020-06-29 14:45:49 +02:00
Miodrag Milanovic
0545a042f3
cleanup
2020-06-29 14:42:48 +02:00
Miodrag Milanovic
5aae936044
Use ID macro to fix assertion
2020-06-29 13:18:13 +02:00
Miodrag Milanovic
87717d67d1
expose pass fix
2020-06-29 11:56:43 +02:00
Miodrag Milanovic
48b6d3272c
sim - error when memrd and memwr detected
2020-06-29 10:33:39 +02:00
Xiretza
e2cfe57edd
test_cell: don't generate directional shifts with \B_SIGNED=1
...
This was made an explicit error in e97e33d
, "kernel: require \B_SIGNED=0
on $shl, $sshl, $shr, $sshr.".
2020-06-28 21:30:16 +02:00
clairexen
c7d71f436d
Merge pull request #2168 from whitequark/assert-unused-exprs
...
Use (and ignore) the expression provided to log_assert in NDEBUG builds
2020-06-25 18:21:51 +02:00
clairexen
21209d632e
Merge pull request #2135 from boqwxp/qbfsat-timeinfo
...
log and qbfsat: Also include child process usage in `PerformanceTimer::query()` and report the time for each call to the QBF-SAT solver
2020-06-25 18:18:09 +02:00
clairexen
fb6441731a
Merge pull request #2093 from boqwxp/qbfsat-bugfixes
...
qbfsat: Multiple bugfixes
2020-06-25 18:14:17 +02:00
Marcelina Kościelnicka
8f12c5b063
simplemap: Fix $dffsre mapping.
2020-06-23 23:16:43 +02:00
Marcelina Kościelnicka
88e7f90663
Update dff2dffe, dff2dffs, zinit to new FF types.
2020-06-23 18:24:53 +02:00
Marcelina Kościelnicka
832acc8648
Add new FF types to simplemap.
2020-06-23 15:40:02 +02:00
Marcelina Kościelnicka
119f79d8b9
Add support for new FF types in some opt passes.
2020-06-23 15:40:02 +02:00
Marcelina Kościelnicka
b0bee396a8
Add new builtin FF types
...
The new types include:
- FFs with async reset and enable (`$adffe`, `$_DFFE_[NP][NP][01][NP]_`)
- FFs with sync reset (`$sdff`, `$_SDFF_[NP][NP][01]_`)
- FFs with sync reset and enable, reset priority (`$sdffs`, `$_SDFFE_[NP][NP][01][NP]_`)
- FFs with sync reset and enable, enable priority (`$sdffce`, `$_SDFFCE_[NP][NP][01][NP]_`)
- FFs with async reset, set, and enable (`$dffsre`, `$_DFFSRE_[NP][NP][NP][NP]_`)
- latches with reset or set (`$adlatch`, `$_DLATCH_[NP][NP][01]_`)
The new FF types are not actually used anywhere yet (this is left
for future commits).
2020-06-23 15:40:02 +02:00
Alberto Gonzalez
a564cc806f
log, qbfsat: Include child process time in `PerformanceTimer::query()` and report the time for each call to the QBF-SAT solver.
2020-06-21 02:16:52 +00:00
Alberto Gonzalez
62a9e62a1b
qbfsat: Simplify solution recovery parsing and tweak the solution regexes.
2020-06-21 02:16:11 +00:00
Alberto Gonzalez
e1fedf054e
qbfsat: Avoid instantiating `AttrObject`s directly.
...
Co-Authored-By: Claire Wolf <claire@symbioticeda.com>
2020-06-21 02:16:11 +00:00
Alberto Gonzalez
08cede4669
qbfsat: Simplify solution format and replace `SigBit::str()` with `log_signal()`.
...
Co-Authored-By: Claire Wolf <claire@symbioticeda.com>
2020-06-21 02:16:11 +00:00
Alberto Gonzalez
4ab41c6435
qbfsat: Fixes three bugs.
...
1. Infinite loop in the optimization procedure when the first solution found while maximizing is at zero.
2. A signed-ness issue when maximizing.
3. Erroneously entering bisection mode with no wire to optimize.
2020-06-21 02:16:11 +00:00
Alberto Gonzalez
a3d1f8637a
qbfsat: Use bit precise mapping for hole value wires and a more robust hole spec for writing to and specializing from a solution file.
2020-06-21 02:16:11 +00:00
whitequark
c8c3c7af87
Use [[maybe_unused]] instead of YS_ATTRIBUTE(unused).
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[[maybe_unused]] is available since C++17, so this commit adds
a polyfill YS_MAYBE_UNUSED. Once we require C++17 we can drop it.
2020-06-19 15:48:58 +00:00
whitequark
118e4caa37
Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug().
2020-06-19 15:48:58 +00:00
whitequark
ede4b10da8
Merge pull request #2173 from whitequark/use-cxx11-final-override
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Use C++11 final/override/[[noreturn]]
2020-06-19 06:15:33 +00:00
whitequark
7191dd16f9
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
Alberto Gonzalez
76dfa81790
cutpoint: Improve efficiency by iterating over module ports instead of module wires.
2020-06-18 17:42:36 +00:00
N. Engelhardt
dfde1cf1c5
Merge pull request #2153 from boqwxp/splitnets-cleanup
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splitnets: Cleanup and efficiency improvements
2020-06-18 19:16:55 +02:00
whitequark
5439faebf9
Merge pull request #2142 from whitequark/splitnets-hdlname
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splitnets: propagate (*hdlname*) and disambiguate via start_offset
2020-06-18 16:57:24 +00:00
Anonymous Maarten
60fb9cabcf
msvc does not support designated initializers in structs
2020-06-17 16:20:52 +02:00
Alberto Gonzalez
f5d7cd60f5
splitnets: Clean up pseudo-private member usage
2020-06-13 05:47:55 +00:00
Alberto Gonzalez
b70de98bd1
splitnets: Slightly improve efficiency by avoiding some unnecessary lookups
2020-06-13 05:26:30 +00:00
whitequark
2139a5c21a
splitnets: propagate (*hdlname*) and disambiguate via start_offset.
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This allows reliably coalescing the split wires later.
2020-06-10 19:59:08 +00:00
Claire Wolf
0bd70e8222
Drive-by modernization in sat.cc
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-06-09 22:48:26 +02:00
Claire Wolf
3c7122c378
Do not optimize away FFs in "prep" and Verific fron-end
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-06-09 15:54:14 +02:00
whitequark
98e1080345
flatten: accept processes.
2020-06-09 09:56:23 +00:00
whitequark
fbb346ea91
flatten: preserve original object names via hdlname attribute.
2020-06-08 20:19:41 +00:00
whitequark
8d821dbbdb
flatten: only prepend $flatten once per wire.
2020-06-08 20:19:41 +00:00
whitequark
a1814b732f
flatten: make hygienic.
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Before this commit, `flatten` matched the template objects with
the newly created objects solely by their name. Because of this,
it could be confused by code such as:
module bar();
$dff a();
endmodule
module foo();
bar b();
$dff \b.a ();
endmodule
After this commit, `flatten` avoids every possible case of name
collision.
Fixes #2106 .
2020-06-08 19:30:21 +00:00
clairexen
369dcb4e82
Merge pull request #2085 from rswarbrick/select
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Silence warning in select.cc and pass some more args by ref
2020-06-08 15:55:52 +02:00
clairexen
0f209378a8
Merge pull request #2089 from rswarbrick/modports
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Simplify a modport check in hierarchy.cc
2020-06-08 15:48:11 +02:00
clairexen
fbd0d8d5f0
Merge pull request #2105 from whitequark/split-flatten-off-techmap
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Split `flatten` from `techmap` and simplify it
2020-06-08 15:27:15 +02:00
Marcelina Kościelnicka
28b9f49c94
fsm_extract: avoid calling log_signal to determine wire name
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log_signal can result in a string with spaces (when bit selection is
involved), which breaks the rule of IdString not containing whitespace.
Instead, remove the sigspec from the name entirely — given that the
resulting wire will have no users, it will be removed later anyway,
so its name doesn't really matter.
Fixes #2118
2020-06-08 03:49:58 +02:00
Eddie Hung
69850204c4
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve
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abc9: -dff improvements
2020-06-04 08:15:25 -07:00
whitequark
5a5a9b4ffe
flatten: clean up log messages.
2020-06-04 12:22:59 +00:00
whitequark
d731fe054b
flatten: topologically sort modules.
2020-06-04 12:22:59 +00:00
Eddie Hung
45cd323055
Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixes
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abc9: fixes around handling combinatorial loops
2020-06-03 17:35:46 -07:00
whitequark
6268bdfe6f
flatten: simplify.
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`flatten` cannot derive modules in most cases because that would just
yield processes, and it does not support `-autoproc`; in practice
`flatten` has to be preceded by a call to `hierarchy`, which makes
deriving unnecessary.
2020-06-04 00:02:12 +00:00
whitequark
d3e2100306
flatten: simplify. NFC.
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Remove redundant sigmaps.
2020-06-04 00:02:12 +00:00
whitequark
66255dab4e
flatten: simplify.
...
Flattening does not benefit from topologically sorting cells within
a module when processing them.
2020-06-04 00:02:12 +00:00
whitequark
5d2b6d1394
flatten: simplify. NFC.
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Flatten is non-recursive and doesn't need to keep track of handled
cells.
2020-06-04 00:02:12 +00:00
whitequark
3c3fa774e5
flatten: simplify. NFC.
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Flattening always does "non-recursive" mapping.
2020-06-04 00:02:12 +00:00
whitequark
e561a3a76f
flatten: simplify. NFC.
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The `celltypeMap` always maps `x` to `{x}`.
2020-06-04 00:02:12 +00:00
whitequark
6783876807
flatten: simplify. NFC.
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The `design` and `map` designs are always the same when flattening.
2020-06-04 00:02:12 +00:00
whitequark
9338ff66b9
RTLIL: factor out RTLIL::Module::addMemory. NFC.
2020-06-04 00:02:12 +00:00
whitequark
ebbbe2156e
flatten: rename techmap-related stuff. NFC.
2020-06-04 00:02:12 +00:00
whitequark
76c4ee4ea5
techmap, flatten: remove dead options.
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After splitting the passes, some options can never be activated,
and most conditions involving them become dead. Remove them, and also
all of the newly dead code.
2020-06-04 00:02:12 +00:00
whitequark
6ac54a74fe
flatten: split from techmap.
...
Although the two passes started out very similar, they diverged over
time and now have little in common. Moreover, `techmap` is extremely
complex while `flatten` does not have to be, and this complexity
interferes with improving `flatten`.
2020-06-03 15:34:03 +00:00
whitequark
fb5b070e7e
techmap: remove dead variable. NFC.
2020-06-03 01:44:06 +00:00
whitequark
0a74368bfc
techmap: use C++11 default member initializers. NFC.
2020-06-02 23:43:20 +00:00
whitequark
f3e86bb32a
techmap: simplify.
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`rewrite_filename` is already called in `Frontend::extra_args`.
2020-06-02 23:43:20 +00:00
whitequark
68d747f767
techmap: use +/techmap.v instead of an ad-hoc code generator.
2020-06-02 23:43:20 +00:00
clairexen
ff785cdb46
Merge pull request #1862 from boqwxp/cleanup_techmap
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Clean up `passes/techmap/techmap.cc`
2020-05-31 20:40:48 +02:00
Eddie Hung
08d9703ecb
abc9_ops: fix comment
2020-05-30 09:01:03 -07:00
Eddie Hung
fe273faad1
Merge pull request #2081 from YosysHQ/eddie/blackbox_ast
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blackbox: use Module::makeblackbox() method
2020-05-30 08:59:20 -07:00
Eddie Hung
ea4374a223
abc9_ops: update messaging (credit to @Xiretza for spotting)
2020-05-30 08:57:48 -07:00
clairexen
ea46ed81f9
Merge pull request #2018 from boqwxp/qbfsat-timeout
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smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, and CVC4.
2020-05-30 15:04:51 +02:00
Eddie Hung
b17e8495b8
abc9_ops: optimise to not derive unless attribute exists
2020-05-29 17:33:10 -07:00
Eddie Hung
d3b53bc495
abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_
2020-05-29 17:17:40 -07:00
clairexen
94c1035389
Merge pull request #1885 from Xiretza/mod-rem-cells
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Fix modulo/remainder semantics
2020-05-29 16:37:23 +02:00
clairexen
5874a14d65
Merge pull request #2017 from boqwxp/qbfsat-cvc4
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qbfsat: Add support for CVC4.
2020-05-29 16:23:10 +02:00
clairexen
1c8d5a08a0
Merge pull request #2016 from boqwxp/qbfsat-yices
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qbfsat: Add `-solver` option and allow choice of Z3 or Yices, making Yices the default.
2020-05-29 16:21:45 +02:00
Xiretza
edd8ff2c07
Add flooring division operator
...
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $divfloor cell provides this flooring division.
This commit also fixes the handling of $div in opt_expr, which was
previously optimized as if it was $divfloor.
2020-05-28 22:59:04 +02:00
Xiretza
17163cf43a
Add flooring modulo operator
...
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $modfloor cell provides this flooring modulo (also known as "remainder"
in several languages, but this name is ambiguous).
This commit also fixes the handling of $mod in opt_expr, which was
previously optimized as if it was $modfloor.
2020-05-28 22:59:03 +02:00
whitequark
0d99522b3c
Merge pull request #2095 from rswarbrick/hier-typo
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Fix small typos in documentation for hierarchy command
2020-05-28 10:49:14 +00:00
Rupert Swarbrick
1158bbf7db
Fix small typos in documentation for hierarchy command
2020-05-28 11:39:44 +01:00
Alberto Gonzalez
5896ffd56f
printattrs: Simplify `get_indent_str()`.
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Co-Authored-By: Xiretza <xiretza@xiretza.xyz>
2020-05-28 05:34:28 +00:00
Alberto Gonzalez
f671c99cb8
printattrs: Refactor indentation string building for clarity.
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Co-Authored-By: whitequark <whitequark@whitequark.org>
2020-05-27 23:15:07 +00:00
Rupert Swarbrick
d681c9df85
Pass some more args by reference in select.cc
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Before this patch, the code passed around std::string objects by
value. It's probably not a hot-spot, but it can't hurt to avoid the
copying.
Removing the copy and clean-up code means the resulting code is ~6.1kb
smaller when compiled with GCC 9.3 and standard settings.
2020-05-27 09:42:23 +01:00
Rupert Swarbrick
061d1f0c07
Minor optimisations in select.cc's match_ids function
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- Pass a string argument by reference
- Avoid multiple calls to IdString::str and IdString::c_str
- Avoid combining checks for size > 0 and first char (C strings are
null terminated, so foo[0] != '\0' implies that foo has positive
length)
2020-05-27 09:36:33 +01:00
Rupert Swarbrick
0d9beb5b2e
Silence warning in select.cc
...
With GCC 9.3, at least, compiling select.cc spits out a warning about
an implausible bound being passed to strncmp. This comes from inlining
IdString::compare(): it turns out that passing std::string::npos as a
bound to strncmp triggers it.
This patch replaces the compare call with a memcmp with the same
effect. The repeated calls to IdString::c_str are slightly
inefficient, but I'll address that in a follow-up commit.
2020-05-27 09:34:15 +01:00
Alberto Gonzalez
e50e4ee285
printattrs: Use `flags` to pretty-print the `RTLIL::Const` appropriately.
...
Co-Authored-By: whitequark <whitequark@whitequark.org>
2020-05-27 08:00:00 +00:00
Alberto Gonzalez
b8365547e9
misc: Add `printattrs` command.
2020-05-27 08:00:00 +00:00
Rupert Swarbrick
7746bba69a
Simplify a modport check in hierarchy.cc
...
This code originally comes from commit 458a940
. When an interface is
used via a modport, code in genrtlil.cc sets '\\interface_type' and
'\\interface_modport' properties on the wire.
In hierarchy.cc, we pick up the modport name and add it to a dict
called modports_used_in_submodule (that maps connection source to
modport name).
Before this patch, the modport name is retrieved as a strpool and then
iterated over in an arbitrary order, discarding all entries but the
last. In practice, the pool will always have 0 or 1 entries because
the string used to construct it is a valid identifier, so doesn't
contain any pipe symbols.
This patch changes the code to retrieve the modport name as just a
string. This will have the same effect in practice, but may be a bit
less confusing!
The code also gets moved down closer to where the result is used,
which might be a bit more efficient since we won't always get as far
as the check.
The patch also removes some commented-out code, which I think was
intended to add some typechecking at some point, but was never
implemented. Since this dates back to October 2018, I think it makes
more sense to just take it out.
2020-05-26 16:50:42 +01:00
Eddie Hung
00c5ceb1f2
abc9_ops: -prep_xaiger exclude (* abc9_keep *) wires from toposort
2020-05-25 16:40:53 -07:00
Alberto Gonzalez
9847a4eea8
smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, and CVC4.
2020-05-25 20:39:30 +00:00
Alberto Gonzalez
f9eef5e3f7
qbfsat: Add support for CVC4.
2020-05-25 20:39:03 +00:00
Alberto Gonzalez
903456c267
qbfsat: Add `-solver` option and allow choice of Z3 or Yices, making Yices the default.
...
Ensures that "BV" is the logic whenever solving an exists-forall problem with Yices, moves the "(set-logic ...)" directive above any non-info line, sets the `ef-max-iters` parameter to a very high number when using Yices in exists-forall mode so as not to prematurely abandon difficult problems, and does not provide the incompatible "--incremental" Yices argument when in exists-forall mode.
2020-05-25 20:38:29 +00:00
Eddie Hung
721283ac2a
blackbox: re-use existing Module::makeblackbox() method
2020-05-25 10:53:49 -07:00
Eddie Hung
7bad23f19c
abc9_ops: -reintegrate to preserve flop names
2020-05-25 08:43:33 -07:00
clairexen
ae11156c90
Merge pull request #2015 from boqwxp/qbfsat-bisection
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qbfsat: Add an iterative bisection optimization method and make it the default.
2020-05-25 15:50:18 +02:00
Alberto Gonzalez
ac41f8a9c7
qbfsat: Remove cruft inadvertently left untouched in commit 86fc49a9d6
.
2020-05-23 00:53:09 +00:00
Alberto Gonzalez
aea0fd5ed4
qbfsat: Add bisection mode and make it the default.
...
Also adds `-nooptimize` and reorganizes `qbfsat.cc` a bit.
2020-05-23 00:53:09 +00:00
Eddie Hung
4f0f321169
abc9_ops: update comment
2020-05-21 21:39:13 -07:00
Miodrag Milanović
637650597b
Merge pull request #2059 from boqwxp/logger-vector-to-dict
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log: Use `dict` instead of `std::vector<std::pair>` for `log_expect_{error, warning, log}` to better express the intent that each element is unique.
2020-05-21 15:36:30 +02:00
Eddie Hung
2d573a0ff6
Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff
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abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *)
2020-05-18 08:06:50 -07:00
Alberto Gonzalez
8297afe925
log: Use `dict` instead of `std::vector<std::pair>` for `log_expect_{error, warning, log}` to better express the intent that each element is unique.
2020-05-15 00:55:32 +00:00
Eddie Hung
67fc0c3698
abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_
...
instead of moving them to $__ prefix
2020-05-14 16:44:35 -07:00
Eddie Hung
07eecff9cc
Merge pull request #2055 from YosysHQ/eddie/logger_multiple
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logger: fix for multiple calls with same pattern
2020-05-14 15:30:08 -07:00
Alberto Gonzalez
e173291649
techmap: Replace naughty `const_cast<>()`s.
...
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-05-14 20:06:55 +00:00
Alberto Gonzalez
97fd304cbe
techmap: Replace pseudo-private member usage with the range accessor function and some naughty `const_cast<>()`s.
2020-05-14 20:06:55 +00:00
Eddie Hung
36bb201dd9
techmap: sort celltypeMap as it determines techmap order
2020-05-14 20:06:55 +00:00
Alberto Gonzalez
ce62d0751a
Replace `std::set`s using custom comparators with `pool`.
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Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-05-14 20:06:55 +00:00
Eddie Hung
dabeb1e8a1
techmap: prefix special wires with backslash for use as IdString
2020-05-14 20:06:55 +00:00
Alberto Gonzalez
bd54d67ad4
Further clean up `passes/techmap/techmap.cc`.
...
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
982562ff13
Use `emplace()` for more efficient insertion into various `dict`s.
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
c658d9d59d
Build constant bits directly rather than constructing an object and copying its bits.
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
f235f212ea
Replace `std::set` with `pool` for `cell_to_inbit` and `outbit_to_cell`.
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
6294621825
Use `emplace()` rather than `insert()`.
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
dfcb936cd5
Clean up pseudo-private member usage and ensure range iteration uses references where possible to avoid unnecessary copies.
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
a4755c50c3
Clean up extraneous buffer.
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
7857782575
Replace `std::map` with `dict` for `unique_bit_id`.
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
6d64d768b0
Replace `std::map` with `dict` for `port_new2old_map`, `port_connmap`, and `cellbits_to_tplbits`.
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
5cb4ae4666
Replace `std::map` with `dict` for `connbits_map`, `cell_to_inbit`, and `outbit_to_cell`.
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
c43017fc08
Replace `std::map` with `dict` for `TechmapWires` type.
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
644e55b3d3
Replace `std::map` with `dict` for `celltypeMap`.
2020-05-14 20:06:53 +00:00
Alberto Gonzalez
67f4046c05
Replace `std::set` with `pool` for `handled_cells` and `techmap_wire_names`.
2020-05-14 20:06:53 +00:00
Alberto Gonzalez
64c16f8c13
Replace `std::map` with `dict` for `positional_ports`.
2020-05-14 20:06:53 +00:00
Alberto Gonzalez
2fb4931e5b
Add specialized `hash()` for type `dict` and use a `dict` instead of a `std::map` for `techmap_cache` and `techmap_do_cache`.
2020-05-14 20:06:53 +00:00
Alberto Gonzalez
437f3fb342
Replace `std::map` with `dict` for `simplemap_mappers`.
2020-05-14 20:06:53 +00:00
Alberto Gonzalez
99b586b283
Use `nullptr` instead of `NULL` in `passes/techmap/techmap.cc`.
2020-05-14 20:06:53 +00:00
Alberto Gonzalez
5f7f213c7f
Replace `std::string` and `RTLIL::IdString` with `IdString` in `passes/techmap/techmap.cc`.
...
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-05-14 20:06:53 +00:00
Alberto Gonzalez
e49fdee404
Do not modify design modules while iterating over `modules()`.
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Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-05-14 20:06:53 +00:00
Alberto Gonzalez
985a29ff3b
Clean up pseudo-private member usage, superfluous `std::vector` instantiation, and `RTLIL::id2cstr()` usage in `passes/techmap/techmap.cc`.
2020-05-14 20:06:53 +00:00
Eddie Hung
7b3a4a1fff
opt_expr: Sx to Sz; spotted by @Xiretza
2020-05-14 12:14:23 -07:00
Eddie Hung
73b7ea713c
Merge pull request #1994 from YosysHQ/eddie/fix_bug1758
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opt_expr: improve single-bit $and/$or/$xor/$xnor cells; gate cells too
2020-05-14 11:56:22 -07:00
Eddie Hung
425867d175
logger: clean up doc
2020-05-14 10:38:31 -07:00
Eddie Hung
02df0198b6
abc9_ops: -prep_hier to create unmap module that removes Q's (* init *)
2020-05-14 10:33:57 -07:00
Eddie Hung
13f9d65b6f
abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it
2020-05-14 10:33:57 -07:00
Eddie Hung
fa31e84112
Fix broken test when ignoring abc9_flop with init == 1'b1
2020-05-14 10:33:57 -07:00
Eddie Hung
97a0a04314
abc9_ops/xaiger: further reducing Module::derive() calls by ...
...
replacing _all_ (* abc9_box *) instantiations with their derived types
2020-05-14 10:33:57 -07:00
Eddie Hung
e79127fceb
Cleanup; reduce Module::derive() calls
2020-05-14 10:33:57 -07:00
Eddie Hung
8d34aee3d5
abc9: update to =_$abc9_flops pattern which includes whiteboxes
2020-05-14 10:33:57 -07:00
Eddie Hung
f652a9c11c
abc9_ops: update docs
2020-05-14 10:33:57 -07:00
Eddie Hung
57c478c537
abc9: only do +/abc9_map if `DFF
2020-05-14 10:33:57 -07:00
Eddie Hung
2946bb60e9
abc9: rework submod -- since it won't move (* keep *) cells
2020-05-14 10:33:56 -07:00
Eddie Hung
b65610fb62
abc9_ops: move assert
2020-05-14 10:33:56 -07:00
Eddie Hung
ed7cb0b095
abc9: put 'aigmap' back
2020-05-14 10:33:56 -07:00
Eddie Hung
b3e2538a14
abc9_ops: fix bypass boxes using (* abc9_bypass *)
2020-05-14 10:33:56 -07:00
Eddie Hung
d5a8aaba8c
abc9_ops: tidy up, suppress error if no boxes/holes
2020-05-14 10:33:56 -07:00
Eddie Hung
e2044fd9c7
abc9_ops: -prep_delays to not insert delay box if input connection is const
2020-05-14 10:33:56 -07:00
Eddie Hung
8b5fb99245
abc9_ops: cleanup; -prep_dff -> -prep_dff_submod
2020-05-14 10:33:56 -07:00
Eddie Hung
7cd3f4a79b
abc9_ops: add -prep_bypass for auto bypass boxes; refactor
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Eliminate need for abc9_{,un}map.v in xilinx
-prep_dff_{hier,unmap} -> -prep_hier
2020-05-14 10:33:56 -07:00
Eddie Hung
bb840cca9c
abc9_ops: -reintegrate to handle $_FF_; cleanup
2020-05-14 10:33:56 -07:00
Eddie Hung
c50601e35e
abc9: restore selected_modules()
2020-05-14 10:33:56 -07:00
Eddie Hung
48052ad813
abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too
2020-05-14 10:33:56 -07:00
Eddie Hung
4cec21b93e
abc9_ops: -prep_dff_map to error if async flop found
2020-05-14 10:33:56 -07:00
Eddie Hung
c41c180f68
abc9: remove redundant wbflip
2020-05-14 10:33:56 -07:00
Eddie Hung
ec4bbb1444
abc9: generate $abc9_holes design instead of <name>$holes
2020-05-14 10:33:56 -07:00
Eddie Hung
c52bb11fb6
abc9_ops: more robust
2020-05-14 10:33:56 -07:00
Eddie Hung
8d7b3c06b2
abc9: suppress warnings when no compatible + used flop boxes formed
2020-05-14 10:33:56 -07:00
Eddie Hung
fb447951be
abc9: cleanup
2020-05-14 10:33:56 -07:00
Eddie Hung
8bad885e78
abc9_ops: -prep_dff_map to check $_DFF_[NP]_.Q drives module output
2020-05-14 10:33:56 -07:00
Eddie Hung
489e83fc1e
abc9_ops: do away with '$abc9_cells' selection
2020-05-14 10:33:56 -07:00
Eddie Hung
043ad8e76c
abc9_ops: use new 'design -delete' and 'select -unset'
2020-05-14 10:33:56 -07:00
Eddie Hung
509de98468
submod: revert accidental change
2020-05-14 10:33:56 -07:00
Eddie Hung
e38b1280f9
abc9_ops: -prep_dff_map to warn if no specify cells
2020-05-14 10:33:56 -07:00
Eddie Hung
a1ae5845f8
abc9_ops: -prep_dff_map to cope with plain $_DFF_[NP]_ flops
2020-05-14 10:33:56 -07:00
Eddie Hung
6b3aa91a2a
abc9: cleanup
2020-05-14 10:33:56 -07:00
Eddie Hung
edacb8f437
abc9_ops: do not use (* abc9_init *)
2020-05-14 10:33:56 -07:00
Eddie Hung
95763c8d18
abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxes
2020-05-14 10:33:56 -07:00
Eddie Hung
accfc70fc2
abc9: fix behaviour and help for -box option
2020-05-14 10:33:56 -07:00
Eddie Hung
65395168a0
logger: fix for multiple calls with same pattern
2020-05-14 10:32:07 -07:00
Eddie Hung
cd92a706ae
Fix whitespace
2020-05-14 09:51:17 -07:00
Eddie Hung
5be4b00a0d
opt_clean: improve warning message
2020-05-14 00:59:38 -07:00
Eddie Hung
fc9fb09a91
opt_clean: rminit without -purge; also remove if consistent with const..
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warn otherwise
2020-05-14 00:31:08 -07:00
Eddie Hung
68b31f5e99
opt_clean: really make 'clean' identical to 'opt_clean' by rminit too
2020-05-14 00:31:08 -07:00
Eddie Hung
9694dc42dd
opt_expr: consume_x to require/imply !keepdc
2020-05-08 11:12:43 -07:00
Eddie Hung
17f4e06247
opt_expr: restore consume_x; use for coarse grained too
2020-05-08 11:07:44 -07:00
Claire Wolf
0610424940
Merge pull request #2005 from YosysHQ/claire/fix1990
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Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
2020-05-07 18:11:48 +02:00
Claire Wolf
5c82c19b4b
Merge pull request #2014 from YosysHQ/claire/fixoptalu
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Fix the other "opt_expr -fine" bug introduced in 213a89558
2020-05-03 11:56:29 +02:00
Claire Wolf
2285cf1219
Fix the other "opt_expr -fine" bug introduced in 213a89558
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 21:50:43 +02:00
Claire Wolf
885deb4e88
Fix the other "opt_expr -fine" bug introduced in 213a89558
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 21:34:24 +02:00
Eddie Hung
da7da44919
abc9_ops: -reintegrate to be sensitive to start_offset too
2020-05-02 11:19:04 -07:00
Claire Wolf
c3e5a070ea
Add plusargs for output files in test_autotb output
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
Claire Wolf
ca3fc3c882
Merge pull request #2010 from YosysHQ/claire/fixopt
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Fix "opt_expr -fine" bug introduced in 213a89558
2020-05-02 11:20:02 +02:00
Claire Wolf
8ee32adac3
Fix "opt_expr -fine" bug introduced in 213a89558
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-01 20:12:16 +02:00
whitequark
b43c282e4e
Add WASI platform support.
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This includes the following significant changes:
* Patching ezsat and minisat to disable resource limiting code
on WASM/WASI, since the POSIX functions they use are unavailable.
* Adding a new definition, YOSYS_DISABLE_SPAWN, present if platform
does not support spawning subprocesses (i.e. Emscripten or WASI).
This definition hides the definition of `run_command()`.
* Adding a new Makefile flag, DISABLE_SPAWN, present in the same
condition. This flag disables all passes that require spawning
subprocesses for their function.
2020-04-30 18:56:25 +00:00
Eddie Hung
b5f38f8342
opt_expr: const_xnor replacement to pad Y with 1'b1
2020-04-24 14:13:45 -07:00
Eddie Hung
56dd036b97
bugpoint: improve messaging
2020-04-24 13:41:19 -07:00
Eddie Hung
e602184856
bugpoint: (* keep *) to (* bugpoint_keep *); also apply to modules/cells
2020-04-24 13:26:04 -07:00
Eddie Hung
4bfe6ebea9
bugpoint: skip ports with (* keep *) on; add header
2020-04-24 11:17:09 -07:00
Eddie Hung
83570bc0da
opt_expr: more fixes for $xor/$xnor
2020-04-24 11:15:29 -07:00
Eddie Hung
90b71eb84b
opt_expr: do not group by X, more fixes
2020-04-23 18:15:07 -07:00
Eddie Hung
e7058593f4
opt_expr: improve single-bit $and/$or/$xor/$xnor cells; gate cells too
2020-04-23 15:57:48 -07:00
Eddie Hung
bf021a0e1f
bugpoint: improve help text
2020-04-23 12:16:55 -07:00
Eddie Hung
b048afc3a6
Merge pull request #1974 from YosysHQ/eddie/abc9_disable_mfs
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abc9: tolerate &mfs failure by writing output file before calling it (and using that if it fails)
2020-04-23 06:43:30 -07:00
Claire Wolf
dc9a72bc8d
Merge pull request #1989 from boqwxp/qbfsat_anyconst_sourcelocs
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qbfsat: Make hole name recovery from source locations more robust.
2020-04-23 11:34:19 +02:00
Claire Wolf
1797c574da
Merge pull request #1988 from boqwxp/qbfsat
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qbfsat: Add `-assume-negative-polarity` option.
2020-04-23 11:33:54 +02:00
Alberto Gonzalez
4ee8452d34
qbfsat: Make hole name recovery more robust. Allow multiple cell types to share the same source location as long as only one `$anyconst` or `$anyseq` has that location.
2020-04-23 05:45:44 +00:00
Alberto Gonzalez
7369e6b26b
qbfsat: Add `-assume-negative-polarity` option.
2020-04-23 04:06:15 +00:00
Eddie Hung
592baebd22
xilinx: xilinx_dsp_cascade to check CREG for DSP48E1 only
2020-04-22 17:43:25 -07:00
Eddie Hung
fa9df06c9d
Merge pull request #1949 from YosysHQ/eddie/select_blackbox
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select: do not select inside black-/white- boxes unless '=' prefix used
2020-04-22 15:35:05 -07:00
Claire Wolf
beb9e4b299
Update passes/cmds/select.cc
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Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-04-22 21:31:32 +02:00
Eddie Hung
7f33a0294b
Cleanup use of hard-coded default parameters in light of #1945
2020-04-22 12:02:30 -07:00
Eddie Hung
eaa5a3e786
select: do not select black/white boxes by default, '=' prefix to do so
2020-04-22 10:15:56 -07:00
Eddie Hung
28623f19ee
Merge pull request #1950 from YosysHQ/eddie/design_import
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design: -import to not count black/white-boxes as candidates for top
2020-04-22 09:32:13 -07:00
Claire Wolf
c32b4bded5
Merge pull request #1976 from YosysHQ/dave/fix-sim-const
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sim: Fix handling of constant-connected cell inputs at startup
2020-04-22 16:57:34 +02:00
Marcelina Kościelnicka
cd82afb740
bugpoint: Don't remove modules or cells while iterating over them.
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Reported by @ZirconiumX.
2020-04-22 00:09:01 +02:00
Marcelina Kościelnicka
846c79b312
hierarchy: Convert positional parameters to named.
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Fixes #1821 .
2020-04-21 19:09:00 +02:00
Claire Wolf
d834cc7afb
Add '=' selection pattern prefix for non-blackbox only patterns
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-21 14:23:24 +02:00
David Shah
abf81c7639
sim: Fix handling of constant-connected cell inputs at startup
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-21 08:58:52 +01:00
Eddie Hung
3d7b983351
abc9: tolerate ABC nonzero exit code if output.aig; write before &mfs
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Re-enable mfs for xilinx/ecp5 speculatively -- if it fails, use pre-mfs
result
2020-04-20 11:26:11 -07:00
Eddie Hung
a998a4155d
xilinx/ecp5: disable abc9's "&mfs" optimisation
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Can sometimes fire an assertion, e.g. #1962
2020-04-20 10:30:10 -07:00
Eddie Hung
8c992ca47f
abc9: -prep_lut to be more robust
2020-04-20 09:39:35 -07:00
David Shah
586739ecf3
qbfsat: Fix illegal use of 'stdout' identifier
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-17 08:42:39 +01:00
whitequark
69743aad42
Merge pull request #1864 from boqwxp/cleanup_techmap_abc
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Clean up pseudo-private member usage and simplify `passes/techmap/abc.cc`
2020-04-17 02:25:18 +00:00