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Merge branch 'master' into clk2ff-better-names

This commit is contained in:
Claire Xen 2022-02-11 16:03:12 +01:00 committed by GitHub
parent 90b40aa51f e016518866
commit 49545c73f7
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757 changed files with 49469 additions and 8717 deletions
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2
.clang-format
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@ -6,7 +6,7 @@ BreakBeforeBraces: Linux
AllowShortIfStatementsOnASingleLine: false
IndentCaseLabels: false
# From CodingReadme
# From guidelines/CodingStyle
TabWidth: 8
ContinuationIndentWidth: 2
ColumnLimit: 150

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@ -6,8 +6,7 @@
Dockerfile
README.md
manual
CodingReadme
guidelines
CodeOfConduct
.travis
.travis.yml

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name: Build and run tests (Linux)
on: [push, pull_request]
jobs:
test-linux:
runs-on: ${{ matrix.os.id }}
strategy:
matrix:
os:
- { id: ubuntu-20.04, name: focal }
compiler:
- 'clang-12'
- 'clang-11'
- 'gcc-11'
- 'gcc-10'
cpp_std:
- 'c++11'
- 'c++14'
- 'c++17'
- 'c++20'
include:
# Limit the older compilers to C++11 mode
- os: { id: ubuntu-18.04, name: bionic }
compiler: 'clang-3.9'
cpp_std: 'c++11'
- os: { id: ubuntu-18.04, name: bionic }
compiler: 'gcc-4.8'
cpp_std: 'c++11'
fail-fast: false
steps:
- name: Install Dependencies
shell: bash
run: |
sudo apt-get update
sudo apt-get install gperf build-essential bison flex libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot pkg-config python python3 libboost-system-dev libboost-python-dev libboost-filesystem-dev zlib1g-dev
- name: Setup GCC
if: startsWith(matrix.compiler, 'gcc')
shell: bash
run: |
CXX=${CC/#gcc/g++}
sudo apt-add-repository ppa:ubuntu-toolchain-r/test
sudo apt-get update
sudo apt-get install $CC $CXX
echo "CC=$CC" >> $GITHUB_ENV
echo "CXX=$CXX" >> $GITHUB_ENV
env:
CC: ${{ matrix.compiler }}
- name: Setup Clang
if: startsWith(matrix.compiler, 'clang')
shell: bash
run: |
wget https://apt.llvm.org/llvm-snapshot.gpg.key
sudo apt-key add llvm-snapshot.gpg.key
rm llvm-snapshot.gpg.key
sudo apt-add-repository "deb https://apt.llvm.org/${{ matrix.os.name }}/ llvm-toolchain-${{ matrix.os.name }} main"
sudo apt-get update
CXX=${CC/#clang/clang++}
sudo apt-get install $CC $CXX
echo "CC=$CC" >> $GITHUB_ENV
echo "CXX=$CXX" >> $GITHUB_ENV
env:
CC: ${{ matrix.compiler }}
- name: Runtime environment
shell: bash
env:
WORKSPACE: ${{ github.workspace }}
run: |
echo "GITHUB_WORKSPACE=`pwd`" >> $GITHUB_ENV
echo "$GITHUB_WORKSPACE/.local/bin" >> $GITHUB_PATH
echo "procs=$(nproc)" >> $GITHUB_ENV
- name: Tool versions
shell: bash
run: |
$CC --version
$CXX --version
- name: Checkout Yosys
uses: actions/checkout@v2
- name: Get iverilog
shell: bash
run: |
git clone https://github.com/steveicarus/iverilog.git
- name: Cache iverilog
id: cache-iverilog
uses: actions/cache@v2
with:
path: .local/
key: ${{ matrix.os.id }}-${{ hashFiles('iverilog/.git/refs/heads/master') }}
- name: Build iverilog
if: steps.cache-iverilog.outputs.cache-hit != 'true'
shell: bash
run: |
mkdir -p $GITHUB_WORKSPACE/.local/
cd iverilog
autoconf
CC=gcc CXX=g++ ./configure --prefix=$GITHUB_WORKSPACE/.local
make -j${{ env.procs }}
make install
- name: Build yosys (gcc-4.8)
if: matrix.compiler == 'gcc-4.8'
shell: bash
run: |
make config-${{ matrix.compiler }}
make -j${{ env.procs }} CCXXSTD=${{ matrix.cpp_std }} CC=$CC CXX=$CC LD=$CC
- name: Build yosys
if: matrix.compiler != 'gcc-4.8'
shell: bash
run: |
make config-${CC%%-*}
make -j${{ env.procs }} CCXXSTD=${{ matrix.cpp_std }} CC=$CC CXX=$CC LD=$CC
- name: Run tests
shell: bash
run: |
make -j${{ env.procs }} test CXXSTD=${{ matrix.cpp_std }} CC=$CC CXX=$CC LD=$CC

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.github/workflows/test-macos.yml vendored Normal file
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name: Build and run tests (macOS)
on: [push, pull_request]
jobs:
test-macos:
runs-on: ${{ matrix.os.id }}
strategy:
matrix:
os:
- { id: macos-11, name: 'Big Sur' }
cpp_std:
- 'c++11'
- 'c++17'
fail-fast: false
steps:
- name: Install Dependencies
run: |
brew install bison flex gawk libffi pkg-config bash
- name: Runtime environment
shell: bash
env:
WORKSPACE: ${{ github.workspace }}
run: |
echo "GITHUB_WORKSPACE=`pwd`" >> $GITHUB_ENV
echo "$GITHUB_WORKSPACE/.local/bin" >> $GITHUB_PATH
echo "$(brew --prefix bison)/bin" >> $GITHUB_PATH
echo "$(brew --prefix flex)/bin" >> $GITHUB_PATH
echo "procs=$(sysctl -n hw.ncpu)" >> $GITHUB_ENV
- name: Tool versions
shell: bash
run: |
cc --version
- name: Checkout Yosys
uses: actions/checkout@v2
- name: Get iverilog
shell: bash
run: |
git clone https://github.com/steveicarus/iverilog.git
- name: Cache iverilog
id: cache-iverilog
uses: actions/cache@v2
with:
path: .local/
key: ${{ matrix.os.id }}-${{ hashFiles('iverilog/.git/refs/heads/master') }}
- name: Build iverilog
if: steps.cache-iverilog.outputs.cache-hit != 'true'
shell: bash
run: |
mkdir -p $GITHUB_WORKSPACE/.local/
cd iverilog
autoconf
CC=gcc CXX=g++ ./configure --prefix=$GITHUB_WORKSPACE/.local/
make -j${{ env.procs }}
make install
- name: Build yosys
shell: bash
run: |
make config-clang
make -j${{ env.procs }} CXXSTD=${{ matrix.cpp_std }} CC=cc CXX=cc LD=cc
- name: Run tests
shell: bash
run: |
make -j${{ env.procs }} test CXXSTD=${{ matrix.cpp_std }} CC=cc CXX=cc LD=cc
test-macos-homebrew:
runs-on: ${{ matrix.os.id }}
strategy:
matrix:
os:
- { id: macos-10.15, name: Catalina }
cpp_std:
- 'c++17'
compiler:
- gcc
fail-fast: false
steps:
- name: Install Dependencies
run: |
brew install bison flex gawk libffi pkg-config bash
- name: Runtime environment
shell: bash
env:
WORKSPACE: ${{ github.workspace }}
run: |
echo "GITHUB_WORKSPACE=`pwd`" >> $GITHUB_ENV
echo "$GITHUB_WORKSPACE/.local/bin" >> $GITHUB_PATH
echo "$(brew --prefix bison)/bin" >> $GITHUB_PATH
echo "$(brew --prefix flex)/bin" >> $GITHUB_PATH
echo "procs=$(sysctl -n hw.ncpu)" >> $GITHUB_ENV
- name: Setup compiler
shell: bash
run: |
brew install ${{ matrix.compiler }}
CC=${COMPILER/@/-}
CXX=${CC/#gcc/g++}
echo "CC=$CC" >> $GITHUB_ENV
echo "CXX=$CXX" >> $GITHUB_ENV
env:
COMPILER: ${{ matrix.compiler }}
- name: Tool versions
shell: bash
run: |
$CC --version
$CXX --version
- name: Checkout Yosys
uses: actions/checkout@v2
- name: Get iverilog
shell: bash
run: |
git clone https://github.com/steveicarus/iverilog.git
- name: Cache iverilog
id: cache-iverilog-homebrew
uses: actions/cache@v2
with:
path: .local/
key: ${{ matrix.os.id }}-homebrew-${{ hashFiles('iverilog/.git/refs/heads/master') }}
- name: Build iverilog
if: steps.cache-iverilog.outputs.cache-hit != 'true'
shell: bash
run: |
mkdir -p $GITHUB_WORKSPACE/.local
cd iverilog
autoconf
CC=gcc CXX=g++ ./configure --prefix=$GITHUB_WORKSPACE/.local
make -j${{ env.procs }}
make install
- name: Build yosys
shell: bash
run: |
make config-gcc
make -j${{ env.procs }} CXXSTD=${{ matrix.cpp_std }} CC=$CC CXX=$CC LD=$CC
- name: Run tests
shell: bash
run: |
make -j${{ env.procs }} test CXXSTD=${{ matrix.cpp_std }} CC=$CC CXX=$CC LD=$CC

34
.github/workflows/version.yml vendored Normal file
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@ -0,0 +1,34 @@
name: Bump version
on:
workflow_dispatch:
schedule:
- cron: '0 0 * * *'
jobs:
bump-version:
runs-on: ubuntu-latest
steps:
- name: Checkout
uses: actions/checkout@v2
with:
fetch-depth: 0
- name: Take last commit
id: log
run: echo "::set-output name=message::$(git log --no-merges -1 --oneline)"
- name: Take repository
id: repo
run: echo "::set-output name=message::$GITHUB_REPOSITORY"
- name: Bump version
if: "!contains(steps.log.outputs.message, 'Bump version') && contains(steps.repo.outputs.message, 'YosysHQ/yosys')"
run: |
make bumpversion
git config --local user.email "41898282+github-actions[bot]@users.noreply.github.com"
git config --local user.name "github-actions[bot]"
git add Makefile
git commit -m "Bump version"
- name: Push changes # push the output folder to your repo
if: "!contains(steps.log.outputs.message, 'Bump version') && contains(steps.repo.outputs.message, 'YosysHQ/yosys')"
uses: ad-m/github-push-action@master
with:
github_token: ${{ secrets.GITHUB_TOKEN }}

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.github/workflows/vs.yml vendored Normal file
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name: Visual Studio Build
on: [push, pull_request]
jobs:
yosys-vcxsrc:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- name: Cache sources
id: cache-sources
uses: actions/cache@v2
with:
path: .
key: cache-yosys
- name: Build
run: make vcxsrc YOSYS_VER=latest
- uses: actions/upload-artifact@v2
with:
name: vcxsrc
path: yosys-win32-vcxsrc-latest.zip
build:
runs-on: windows-2019
needs: yosys-vcxsrc
steps:
- uses: actions/download-artifact@v2
with:
name: vcxsrc
path: .
- name: unzip
run: unzip yosys-win32-vcxsrc-latest.zip
- name: setup-msbuild
uses: microsoft/setup-msbuild@v1
- name: MSBuild
working-directory: yosys-win32-vcxsrc-latest
run: msbuild YosysVS.sln /p:PlatformToolset=v142 /p:Configuration=Release /p:WindowsTargetPlatformVersion=10.0.17763.0

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@ -0,0 +1,7 @@
Marcelina Kościelnicka <mwk@0x04.net>
Marcelina Kościelnicka <mwk@0x04.net> <koriakin@0x04.net>
Marcelina Kościelnicka <mwk@0x04.net> <marcin@symbioticeda.com>
Claire Xenia Wolf <claire@yosyshq.com> <claire@clairexen.net>
Claire Xenia Wolf <claire@yosyshq.com> <claire@symbioticeda.com>
Claire Xenia Wolf <claire@yosyshq.com> <clifford@symbioticeda.com>
Claire Xenia Wolf <claire@yosyshq.com> <clifford@clifford.at>

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.travis.yml
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@ -1,144 +0,0 @@
sudo: false
language: cpp
cache:
ccache: true
directories:
- ~/.local-bin
env:
global:
- MAKEFLAGS="-j 2"
matrix:
include:
# Latest gcc-4.8, earliest version supported by Travis
- os: linux
addons:
apt:
packages:
- g++-4.8
- gperf
- build-essential
- bison
- flex
- libreadline-dev
- gawk
- tcl-dev
- libffi-dev
- git
- graphviz
- xdot
- pkg-config
- python
- python3
- libboost-system-dev
- libboost-python-dev
- libboost-filesystem-dev
- zlib1g-dev
env:
- MATRIX_EVAL="CONFIG=gcc && CC=gcc-4.8 && CXX=g++-4.8"
# Latest gcc supported on Travis Linux
- os: linux
addons:
apt:
sources:
- ubuntu-toolchain-r-test
packages:
- g++-9
- gperf
- build-essential
- bison
- flex
- libreadline-dev
- gawk
- tcl-dev
- libffi-dev
- git
- graphviz
- xdot
- pkg-config
- python
- python3
- libboost-system-dev
- libboost-python-dev
- libboost-filesystem-dev
- zlib1g-dev
env:
- MATRIX_EVAL="CONFIG=gcc && CC=gcc-9 && CXX=g++-9"
# Clang which ships on Trusty Linux
- os: linux
addons:
apt:
sources:
- ubuntu-toolchain-r-test
- llvm-toolchain-precise-3.8
packages:
- clang-3.8
- gperf
- build-essential
- bison
- flex
- libreadline-dev
- gawk
- tcl-dev
- libffi-dev
- git
- graphviz
- xdot
- pkg-config
- python
- python3
- libboost-system-dev
- libboost-python-dev
- libboost-filesystem-dev
- zlib1g-dev
env:
- MATRIX_EVAL="CONFIG=clang && CC=clang-3.8 && CXX=clang++-3.8"
# Latest clang supported by Travis Linux
- os: linux
addons:
apt:
sources:
- llvm-toolchain-xenial-8
packages:
- clang-8
- gperf
- build-essential
- bison
- flex
- libreadline-dev
- gawk
- tcl-dev
- libffi-dev
- git
- graphviz
- xdot
- pkg-config
- python
- python3
- libboost-system-dev
- libboost-python-dev
- libboost-filesystem-dev
- zlib1g-dev
env:
- MATRIX_EVAL="CONFIG=clang && CC=clang-8 && CXX=clang++-8"
# # Latest clang on Mac OS X
# - os: osx
# osx_image: xcode9.4
# env:
# - MATRIX_EVAL="CONFIG=clang && CC=clang && CXX=clang++"
before_install:
- ./.travis/setup.sh
script:
- ./.travis/build-and-test.sh
after_success:
- ./.travis/deploy-after-success.sh

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.travis/build-and-test.sh
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@ -1,51 +0,0 @@
#! /bin/bash
set -e
source .travis/common.sh
##########################################################################
echo
echo 'Configuring...' && echo -en 'travis_fold:start:script.configure\\r'
echo
if [ "$CONFIG" = "gcc" ]; then
echo "Configuring for gcc."
make config-gcc
elif [ "$CONFIG" = "clang" ]; then
echo "Configuring for clang."
make config-clang
fi
echo
echo -en 'travis_fold:end:script.configure\\r'
echo
##########################################################################
echo
echo 'Building...' && echo -en 'travis_fold:start:script.build\\r'
echo
make CC=$CC CXX=$CC LD=$CC
echo
echo -en 'travis_fold:end:script.build\\r'
echo
##########################################################################
./yosys tests/simple/fiedler-cooley.v
echo
echo 'Testing...' && echo -en 'travis_fold:start:script.test\\r'
echo
make test
echo
echo -en 'travis_fold:end:script.test\\r'
echo
##########################################################################

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.travis/common.sh
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@ -1,15 +0,0 @@
#! /bin/bash
# Setup the CC / CXX from the matrix config
eval "${MATRIX_EVAL}"
# Look for location binaries first
export PATH="$HOME/.local-bin/bin:$PATH"
# OS X specific common setup
if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then
export PATH="/usr/local/opt/ccache/libexec:$PATH"
fi
# Parallel builds!
MAKEFLAGS="-j 2"

6
.travis/deploy-after-success.sh
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@ -1,6 +0,0 @@
#! /bin/bash
set -x
set -e
# FIXME: Upload the build results somewhere...

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.travis/setup.sh
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@ -1,63 +0,0 @@
#! /bin/bash
set -e
source .travis/common.sh
##########################################################################
# Output status information.
(
set +e
set -x
git status
git branch -v
git log -n 5 --graph
git log --format=oneline -n 20 --graph
)
echo
echo -en 'travis_fold:end:before_install.git\\r'
echo
##########################################################################
# Mac OS X specific setup.
if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then
(
echo
echo 'Setting up brew...' && echo -en 'travis_fold:start:before_install.brew\\r'
echo
brew update
brew tap Homebrew/bundle
brew bundle
brew install ccache
echo
echo -en 'travis_fold:end:before_install.brew\\r'
echo
)
fi
##########################################################################
# Install iverilog
(
if [ ! -e ~/.local-bin/bin/iverilog ]; then
echo
echo 'Building iverilog...' && echo -en 'travis_fold:start:before_install.iverilog\\r'
echo
mkdir -p ~/.local-src
mkdir -p ~/.local-bin
cd ~/.local-src
git clone git://github.com/steveicarus/iverilog.git
cd iverilog
autoconf
CC=gcc CXX=g++ ./configure --prefix=$HOME/.local-bin
make
make install
echo
echo -en 'travis_fold:end:before_install.iverilog\\r'
echo
fi
)
##########################################################################

260
CHANGELOG
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@ -2,74 +2,246 @@
List of major changes and improvements between releases
=======================================================
Yosys 0.14 .. Yosys 0.14-dev
--------------------------
Yosys 0.9 .. Yosys 0.9-dev
Yosys 0.13 .. Yosys 0.14
--------------------------
* Various
- Added $bmux and $demux cells and related optimization patterns.
* New commands and options
- Added "bmuxmap" and "dmuxmap" passes
- Added "-fst" option to "sim" pass for writing FST files
- Added "-r", "-scope", "-start", "-stop", "-at", "-sim", "-sim-gate",
"-sim-gold" options to "sim" pass for co-simulation
* Anlogic support
- Added support for BRAMs
Yosys 0.12 .. Yosys 0.13
--------------------------
* Various
- Use "read" command to parse HDL files from Yosys command-line
- Added "yosys -r <topmodule>" command line option
- write_verilog: dump zero width sigspecs correctly
* SystemVerilog
- Fixed regression preventing the use array querying functions in case
expressions and case item expressions
- Fixed static size casts inadvertently limiting the result width of binary
operations
- Fixed static size casts ignoring expression signedness
- Fixed static size casts not extending unbased unsized literals
- Added automatic `nosync` inference for local variables in `always_comb`
procedures which are always assigned before they are used to avoid errant
latch inference
* New commands and options
- Added "clean_zerowidth" pass
* Verific support
- Add YOSYS to the implicitly defined verilog macros in verific
Yosys 0.11 .. Yosys 0.12
--------------------------
* Various
- Added iopadmap native support for negative-polarity output enable
- ABC update
* SystemVerilog
- Support parameters using struct as a wiretype
* New commands and options
- Added "-genlib" option to "abc" pass
- Added "sta" very crude static timing analysis pass
* Verific support
- Fixed memory block size in import
* New back-ends
- Added support for GateMate FPGA from Cologne Chip AG
* Intel ALM support
- Added preliminary Arria V support
Yosys 0.10 .. Yosys 0.11
--------------------------
* Various
- Added $aldff and $aldffe (flip-flops with async load) cells
* SystemVerilog
- Fixed an issue which prevented writing directly to a memory word via a
connection to an output port
- Fixed an issue which prevented unbased unsized literals (e.g., `'1`) from
filling the width of a cell input
- Fixed an issue where connecting a slice covering the entirety of a signed
signal to a cell input would cause a failed assertion
* Verific support
- Importer support for {PRIM,WIDE_OPER}_DFF
- Importer support for PRIM_BUFIF1
- Option to use Verific without VHDL support
- Importer support for {PRIM,WIDE_OPER}_DLATCH{,RS}
- Added -cfg option for getting/setting Verific runtime flags
Yosys 0.9 .. Yosys 0.10
--------------------------
* Various
- Added "write_xaiger" backend
- Added "abc9" pass for timing-aware techmapping (experimental, FPGA only)
- Added "synth_xilinx -abc9" (experimental)
- Added "synth_ice40 -abc9" (experimental)
- Added "synth -abc9" (experimental)
- Added "script -scriptwire"
- Added "synth_xilinx -nocarry"
- Added "synth_xilinx -nowidelut"
- Added "synth_ecp5 -nowidelut"
- "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
- Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
- Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
- Renamed labels in synth_intel (e.g. bram -> map_bram)
- Renamed labels/options in synth_xilinx (e.g. dram -> map_lutram; -nodram -> -nolutram)
- Added automatic gzip decompression for frontends
- Added $_NMUX_ cell type
- Added automatic gzip compression (based on filename extension) for backends
- Improve attribute and parameter encoding in JSON to avoid ambiguities between
bit vectors and strings containing [01xz]*
- Improvements in pmgen: subpattern and recursive matches
- Support explicit FIRRTL properties
- Improvements in pmgen: slices, choices, define, generate
- Added "_TECHMAP_WIREINIT_*_" parameter and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
- Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
- Added new frontend: rpc
- Added --version and -version as aliases for -V
- Improve yosys-smtbmc "solver not found" handling
- Improved support of $readmem[hb] Memory Content File inclusion
- Added CXXRTL backend
- Use YosysHQ/abc instead of upstream berkeley-abc/abc
- Added WASI platform support.
- Added extmodule support to firrtl backend
- Added $divfloor and $modfloor cells
- Added $adffe, $dffsre, $sdff, $sdffe, $sdffce, $adlatch cells
- Added "_TECHMAP_CELLNAME_" parameter for "techmap" pass
- Added firrtl backend support for generic parameters in blackbox components
- Added $meminit_v2 cells (with support for write mask)
- Added $mem_v2, $memrd_v2, $memwr_v2, with the following features:
- write priority masks, per write/write port pair
- transparency and undefined collision behavior masks, per read/write port pair
- read port reset and initialization
- wide ports (accessing a naturally aligned power-of-two number of memory cells)
* New commands and options
- Added "write_xaiger" backend
- Added "read_xaiger"
- Added "abc9" pass for timing-aware techmapping (experimental, FPGA only)
- Added "synth -abc9" (experimental)
- Added "script -scriptwire"
- Added "clkbufmap" pass
- Added "extractinv" pass and "invertible_pin" attribute
- Added "proc_clean -quiet"
- Added "proc_prune" pass
- Added "stat -tech cmos"
- Added "opt_share" pass, run as part of "opt -full"
- Added "-match-init" option to "dff2dffs" pass
- Added "equiv_opt -multiclock"
- Added "techmap_autopurge" support to techmap
- Added "add -mod <modname[s]>"
- Added "paramap" pass
- Added "portlist" command
- Added "check -mapped"
- Added "check -allow-tbuf"
- Added "autoname" pass
- Added "write_verilog -extmem"
- Added "opt_mem" pass
- Added "scratchpad" pass
- Added "fminit" pass
- Added "opt_lut_ins" pass
- Added "logger" pass
- Added "show -nobg"
- Added "exec" command
- Added "design -delete"
- Added "design -push-copy"
- Added "qbfsat" command
- Added "select -unset"
- Added "dfflegalize" pass
- Removed "opt_expr -clkinv" option, made it the default
- Added "proc -nomux
- Merged "dffsr2dff", "opt_rmdff", "dff2dffe", "dff2dffs", "peepopt.dffmux" passes into a new "opt_dff" pass
* SystemVerilog
- Added checking of always block types (always_comb, always_latch and always_ff)
- Added support for wildcard port connections (.*)
- Added support for enum typedefs
- Added support for structs and packed unions.
- Allow constant function calls in for loops and generate if and case
- Added support for static cast
- Added support for logic typed parameters
- Fixed generate scoping issues
- Added support for real-valued parameters
- Allow localparams in constant functions
- Module name scope support
- Support recursive functions using ternary expressions
- Extended support for integer types
- Support for parameters without default values
- Allow globals in one file to depend on globals in another
- Added support for: *=, /=, %=, <<=, >>=, <<<=, >>>=
- Added support for parsing the 'bind' construct
- support declaration in procedural for initialization
- support declaration in generate for initialization
- Support wand and wor of data types
* Verific support
- Added "verific -L"
- Add Verific SVA support for "always" properties
- Add Verific support for SVA nexttime properties
- Improve handling of verific primitives in "verific -import -V" mode
- Import attributes for wires
- Support VHDL enums
- Added support for command files
* New back-ends
- Added initial EFINIX support
- Added Intel ALM: alternative synthesis for Intel FPGAs
- Added initial Nexus support
- Added initial MachXO2 support
- Added initial QuickLogic PolarPro 3 support
* ECP5 support
- Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
- Added "synth_ecp5 -abc9" (experimental)
- Added "synth_ecp5 -nowidelut"
- "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
* iCE40 support
- Added "synth_ice40 -abc9" (experimental)
- Added "synth_ice40 -device"
- Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
- Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
- Removed "ice40_unlut"
- Added "ice40_dsp" for Lattice iCE40 DSP packing
- "synth_ice40 -dsp" to infer DSP blocks
* Xilinx support
- Added "synth_xilinx -abc9" (experimental)
- Added "synth_xilinx -nocarry"
- Added "synth_xilinx -nowidelut"
- "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
- Renamed labels/options in synth_xilinx (e.g. dram -> map_lutram; -nodram -> -nolutram)
- Added "synth_xilinx -family xc6s" for Spartan 6 support (experimental)
- Added "synth_xilinx -ise" (experimental)
- Added "synth_xilinx -iopad"
- "synth_xilinx" now automatically inserts clock buffers (add -noclkbuf to disable)
- Improvements in pmgen: subpattern and recursive matches
- Added "opt_share" pass, run as part of "opt -full"
- Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
- Removed "ice40_unlut"
- Improvements in pmgen: slices, choices, define, generate
- Added "xilinx_srl" for Xilinx shift register extraction
- Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
- Added "_TECHMAP_WIREINIT_*_" parameter and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
- Added "-match-init" option to "dff2dffs" pass
- Added "techmap_autopurge" support to techmap
- Added "add -mod <modname[s]>"
- Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
- Added "ice40_dsp" for Lattice iCE40 DSP packing
- Added "xilinx_dsp" for Xilinx DSP packing
- "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
- "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
- "synth_ice40 -dsp" to infer DSP blocks
- Added latch support to synth_xilinx
- Added support for flip-flops with synchronous reset to synth_xilinx
- Added support for flip-flops with reset and enable to synth_xilinx
- Added "check -mapped"
- Added checking of SystemVerilog always block types (always_comb,
always_latch and always_ff)
- Added support for SystemVerilog wildcard port connections (.*)
- Added "xilinx_dffopt" pass
- Added "scratchpad" pass
- Added "synth_xilinx -dff"
- Improved support of $readmem[hb] Memory Content File inclusion
- Added "opt_lut_ins" pass
- Added "logger" pass
- Added "design -delete"
- Added "select -unset"
- Use YosysHQ/abc instead of upstream berkeley-abc/abc
- Added $divfloor and $modfloor cells
- Added $adffe, $dffsre, $sdff, $sdffe, $sdffce, $adlatch cells
- Added "dfflegalize" pass
- Added "_TECHMAP_CELLNAME_" parameter for "techmap" pass
- Merged "dffsr2dff", "opt_rmdff", "dff2dffe", "dff2dffs", "peepopt.dffmux" passes into a new "opt_dff" pass
* Intel support
- Renamed labels in synth_intel (e.g. bram -> map_bram)
- synth_intel: cyclone10 -> cyclone10lp, a10gx -> arria10gx
- Added "intel_alm -abc9" (experimental)
* CoolRunner2 support
- Separate and improve buffer cell insertion pass
- Use extract_counter to optimize counters
Yosys 0.8 .. Yosys 0.9
----------------------

5
CODEOWNERS
View File

@ -16,6 +16,8 @@ backends/cxxrtl/ @whitequark
passes/cmds/bugpoint.cc @whitequark
passes/techmap/flowmap.cc @whitequark
passes/opt/opt_lut.cc @whitequark
passes/techmap/abc9*.cc @eddiehung
backends/aiger/xaiger.cc @eddiehung
## External Contributors
@ -29,6 +31,8 @@ frontends/verilog/ @zachjs
frontends/ast/ @zachjs
techlibs/intel_alm/ @ZirconiumX
techlibs/gowin/ @pepijndevos
techlibs/gatemate/ @pu-cc
# pyosys
misc/*.py @btut
@ -38,4 +42,5 @@ backends/firrtl @ucbjrl @azidar
passes/sat/qbfsat.cc @boqwxp
passes/sat/qbfsat.h @boqwxp
passes/cmds/exec.cc @boqwxp
passes/cmds/glift.cc @boqwxp
passes/cmds/printattrs.cc @boqwxp

2
COPYING
View File

@ -1,6 +1,6 @@
ISC License
Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com>
Copyright (C) 2012 - 2020 Claire Xenia Wolf <claire@yosyshq.com>
Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above

123
Makefile
View File

@ -18,6 +18,8 @@ ENABLE_READLINE := 1
ENABLE_EDITLINE := 0
ENABLE_GHDL := 0
ENABLE_VERIFIC := 0
DISABLE_VERIFIC_EXTENSIONS := 0
DISABLE_VERIFIC_VHDL := 0
ENABLE_COVER := 1
ENABLE_LIBYOSYS := 0
ENABLE_PROTOBUF := 0
@ -85,6 +87,7 @@ all: top-all
YOSYS_SRC := $(dir $(firstword $(MAKEFILE_LIST)))
VPATH := $(YOSYS_SRC)
CXXSTD ?= c++11
CXXFLAGS := $(CXXFLAGS) -Wall -Wextra -ggdb -I. -I"$(YOSYS_SRC)" -MD -MP -D_YOSYS_ -fPIC -I$(PREFIX)/include
LDLIBS := $(LDLIBS) -lstdc++ -lm
PLUGIN_LDFLAGS :=
@ -126,12 +129,12 @@ LDFLAGS += -rdynamic
LDLIBS += -lrt
endif
YOSYS_VER := 0.9+3981
GIT_REV := $(shell cd $(YOSYS_SRC) && git rev-parse --short HEAD 2> /dev/null || echo UNKNOWN)
YOSYS_VER := 0.14+6
GIT_REV := $(shell git -C $(YOSYS_SRC) rev-parse --short HEAD 2> /dev/null || echo UNKNOWN)
OBJS = kernel/version_$(GIT_REV).o
bumpversion:
sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 8a4c6e6.. | wc -l`/;" Makefile
sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline a4522d6.. | wc -l`/;" Makefile
# set 'ABCREV = default' to use abc/ as it is
#
@ -139,10 +142,10 @@ bumpversion:
# is just a symlink to your actual ABC working directory, as 'make mrproper'
# will remove the 'abc' directory and you do not want to accidentally
# delete your work on ABC..
ABCREV = 4f5f73d
ABCREV = f6fa2dd
ABCPULL = 1
ABCURL ?= https://github.com/YosysHQ/abc
ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1
ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 VERBOSE=$(Q)
# set ABCEXTERNAL = <abc-command> to use an external ABC instance
# Note: The in-tree ABC (yosys-abc) will not be installed when ABCEXTERNAL is set.
@ -186,21 +189,21 @@ endif
ifeq ($(CONFIG),clang)
CXX = clang
LD = clang++
CXXFLAGS += -std=c++11 -Os
CXXFLAGS += -std=$(CXXSTD) -Os
ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H"
ifneq ($(SANITIZER),)
$(info [Clang Sanitizer] $(SANITIZER))
CXXFLAGS += -g -O1 -fno-omit-frame-pointer -fno-optimize-sibling-calls -fsanitize=$(SANITIZER)
LDFLAGS += -g -fsanitize=$(SANITIZER)
ifeq ($(SANITIZER),address)
ifneq ($(findstring address,$(SANITIZER)),)
ENABLE_COVER := 0
endif
ifeq ($(SANITIZER),memory)
ifneq ($(findstring memory,$(SANITIZER)),)
CXXFLAGS += -fPIE -fsanitize-memory-track-origins
LDFLAGS += -fPIE -fsanitize-memory-track-origins
endif
ifeq ($(SANITIZER),cfi)
ifneq ($(findstring cfi,$(SANITIZER)),)
CXXFLAGS += -flto
LDFLAGS += -flto
endif
@ -209,7 +212,7 @@ endif
else ifeq ($(CONFIG),gcc)
CXX = gcc
LD = gcc
CXXFLAGS += -std=c++11 -Os
CXXFLAGS += -std=$(CXXSTD) -Os
ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H"
else ifeq ($(CONFIG),gcc-static)
@ -217,7 +220,7 @@ LD = $(CXX)
LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -static
LDLIBS := $(filter-out -lrt,$(LDLIBS))
CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
CXXFLAGS += -std=c++11 -Os
CXXFLAGS += -std=$(CXXSTD) -Os
ABCMKARGS = CC="$(CC)" CXX="$(CXX)" LD="$(LD)" ABC_USE_LIBSTDCXX=1 LIBS="-lm -lpthread -static" OPTFLAGS="-O" \
ARCHFLAGS="-DABC_USE_STDINT_H -DABC_NO_DYNAMIC_LINKING=1 -Wno-unused-but-set-variable $(ARCHFLAGS)" ABC_USE_NO_READLINE=1
ifeq ($(DISABLE_ABC_THREADS),1)
@ -227,13 +230,13 @@ endif
else ifeq ($(CONFIG),gcc-4.8)
CXX = gcc-4.8
LD = gcc-4.8
CXXFLAGS += -std=c++11 -Os
CXXFLAGS += -std=$(CXXSTD) -Os
ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H"
else ifeq ($(CONFIG),afl-gcc)
CXX = AFL_QUIET=1 AFL_HARDEN=1 afl-gcc
LD = AFL_QUIET=1 AFL_HARDEN=1 afl-gcc
CXXFLAGS += -std=c++11 -Os
CXXFLAGS += -std=$(CXXSTD) -Os
ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H"
else ifeq ($(CONFIG),cygwin)
@ -245,7 +248,7 @@ ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H"
else ifeq ($(CONFIG),emcc)
CXX = emcc
LD = emcc
CXXFLAGS := -std=c++11 $(filter-out -fPIC -ggdb,$(CXXFLAGS))
CXXFLAGS := -std=$(CXXSTD) $(filter-out -fPIC -ggdb,$(CXXFLAGS))
ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H -DABC_MEMALIGN=8"
EMCCFLAGS := -Os -Wno-warn-absolute-paths
EMCCFLAGS += --memory-init-file 0 --embed-file share -s NO_EXIT_RUNTIME=1
@ -295,7 +298,7 @@ AR = $(WASI_SDK)/bin/ar
RANLIB = $(WASI_SDK)/bin/ranlib
WASIFLAGS := --sysroot $(WASI_SDK)/share/wasi-sysroot $(WASIFLAGS)
endif
CXXFLAGS := $(WASIFLAGS) -std=c++11 -Os $(filter-out -fPIC,$(CXXFLAGS))
CXXFLAGS := $(WASIFLAGS) -std=$(CXXSTD) -Os $(filter-out -fPIC,$(CXXFLAGS))
LDFLAGS := $(WASIFLAGS) -Wl,-z,stack-size=1048576 $(filter-out -rdynamic,$(LDFLAGS))
LDLIBS := $(filter-out -lrt,$(LDLIBS))
ABCMKARGS += AR="$(AR)" RANLIB="$(RANLIB)"
@ -314,7 +317,7 @@ else ifeq ($(CONFIG),mxe)
PKG_CONFIG = /usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-pkg-config
CXX = /usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-g++
LD = /usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-g++
CXXFLAGS += -std=c++11 -Os -D_POSIX_SOURCE -DYOSYS_MXE_HACKS -Wno-attributes
CXXFLAGS += -std=$(CXXSTD) -Os -D_POSIX_SOURCE -DYOSYS_MXE_HACKS -Wno-attributes
CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s
LDLIBS := $(filter-out -lrt,$(LDLIBS))
@ -326,7 +329,7 @@ EXE = .exe
else ifeq ($(CONFIG),msys2-32)
CXX = i686-w64-mingw32-g++
LD = i686-w64-mingw32-g++
CXXFLAGS += -std=c++11 -Os -D_POSIX_SOURCE -DYOSYS_WIN32_UNIX_DIR
CXXFLAGS += -std=$(CXXSTD) -Os -D_POSIX_SOURCE -DYOSYS_WIN32_UNIX_DIR
CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s
LDLIBS := $(filter-out -lrt,$(LDLIBS))
@ -337,7 +340,7 @@ EXE = .exe
else ifeq ($(CONFIG),msys2-64)
CXX = x86_64-w64-mingw32-g++
LD = x86_64-w64-mingw32-g++
CXXFLAGS += -std=c++11 -Os -D_POSIX_SOURCE -DYOSYS_WIN32_UNIX_DIR
CXXFLAGS += -std=$(CXXSTD) -Os -D_POSIX_SOURCE -DYOSYS_WIN32_UNIX_DIR
CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s
LDLIBS := $(filter-out -lrt,$(LDLIBS))
@ -354,53 +357,29 @@ TARGETS += libyosys.so
endif
ifeq ($(ENABLE_PYOSYS),1)
#Detect name of boost_python library. Some distros usbe boost_python-py<version>, other boost_python<version>, some only use the major version number, some a concatenation of major and minor version numbers
ifeq ($(OS), Darwin)
# Detect name of boost_python library. Some distros use boost_python-py<version>, other boost_python<version>, some only use the major version number, some a concatenation of major and minor version numbers
CHECK_BOOST_PYTHON = (echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null $(shell $(PYTHON_CONFIG) --ldflags) -l$(1) - > /dev/null 2>&1 && echo "-l$(1)")
BOOST_PYTHON_LIB ?= $(shell \
if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null $(shell $(PYTHON_CONFIG) --ldflags) -lboost_python-py$(subst .,,$(PYTHON_VERSION)) - > /dev/null 2>&1; then echo "-lboost_python-py$(subst .,,$(PYTHON_VERSION))"; else \
if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null $(shell $(PYTHON_CONFIG) --ldflags) -lboost_python-py$(subst .,,$(PYTHON_MAJOR_VERSION)) - > /dev/null 2>&1; then echo "-lboost_python-py$(subst .,,$(PYTHON_MAJOR_VERSION))"; else \
if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null $(shell $(PYTHON_CONFIG) --ldflags) -lboost_python$(subst .,,$(PYTHON_VERSION)) - > /dev/null 2>&1; then echo "-lboost_python$(subst .,,$(PYTHON_VERSION))"; else \
if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null $(shell $(PYTHON_CONFIG) --ldflags) -lboost_python$(subst .,,$(PYTHON_MAJOR_VERSION)) - > /dev/null 2>&1; then echo "-lboost_python$(subst .,,$(PYTHON_MAJOR_VERSION))"; else \
echo ""; fi; fi; fi; fi;)
else
BOOST_PYTHON_LIB ?= $(shell \
if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null `$(PYTHON_CONFIG) --libs` -lboost_python-py$(subst .,,$(PYTHON_VERSION)) - > /dev/null 2>&1; then echo "-lboost_python-py$(subst .,,$(PYTHON_VERSION))"; else \
if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null `$(PYTHON_CONFIG) --libs` -lboost_python-py$(subst .,,$(PYTHON_MAJOR_VERSION)) - > /dev/null 2>&1; then echo "-lboost_python-py$(subst .,,$(PYTHON_MAJOR_VERSION))"; else \
if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null `$(PYTHON_CONFIG) --libs` -lboost_python$(subst .,,$(PYTHON_VERSION)) - > /dev/null 2>&1; then echo "-lboost_python$(subst .,,$(PYTHON_VERSION))"; else \
if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null `$(PYTHON_CONFIG) --libs` -lboost_python$(subst .,,$(PYTHON_MAJOR_VERSION)) - > /dev/null 2>&1; then echo "-lboost_python$(subst .,,$(PYTHON_MAJOR_VERSION))"; else \
echo ""; fi; fi; fi; fi;)
endif
$(call CHECK_BOOST_PYTHON,boost_python-py$(subst .,,$(PYTHON_VERSION))) || \
$(call CHECK_BOOST_PYTHON,boost_python-py$(PYTHON_MAJOR_VERSION)) || \
$(call CHECK_BOOST_PYTHON,boost_python$(subst .,,$(PYTHON_VERSION))) || \
$(call CHECK_BOOST_PYTHON,boost_python$(PYTHON_MAJOR_VERSION)) \
)
ifeq ($(BOOST_PYTHON_LIB),)
$(error BOOST_PYTHON_LIB could not be detected. Please define manually)
endif
ifeq ($(OS), Darwin)
ifeq ($(PYTHON_MAJOR_VERSION),3)
LDLIBS += $(shell $(PYTHON_CONFIG) --ldflags) $(BOOST_PYTHON_LIB) -lboost_system -lboost_filesystem
CXXFLAGS += $(shell $(PYTHON_CONFIG) --includes) -DWITH_PYTHON
else
LDLIBS += $(shell $(PYTHON_CONFIG) --ldflags) $(BOOST_PYTHON_LIB) -lboost_system -lboost_filesystem
CXXFLAGS += $(shell $(PYTHON_CONFIG) --includes) -DWITH_PYTHON
endif
else
ifeq ($(PYTHON_MAJOR_VERSION),3)
LDLIBS += $(shell $(PYTHON_CONFIG) --libs) $(BOOST_PYTHON_LIB) -lboost_system -lboost_filesystem
# python-config --ldflags includes LDLIBS for some reason
LDFLAGS += $(filter-out -l%,$(shell $(PYTHON_CONFIG) --ldflags))
CXXFLAGS += $(shell $(PYTHON_CONFIG) --includes) -DWITH_PYTHON
else
LDLIBS += $(shell $(PYTHON_CONFIG) --libs) $(BOOST_PYTHON_LIB) -lboost_system -lboost_filesystem
CXXFLAGS += $(shell $(PYTHON_CONFIG) --includes) -DWITH_PYTHON
endif
endif
ifeq ($(ENABLE_PYOSYS),1)
PY_WRAPPER_FILE = kernel/python_wrappers
OBJS += $(PY_WRAPPER_FILE).o
PY_GEN_SCRIPT= py_wrap_generator
PY_WRAP_INCLUDES := $(shell python$(PYTHON_VERSION) -c "from misc import $(PY_GEN_SCRIPT); $(PY_GEN_SCRIPT).print_includes()")
endif
endif
endif # ENABLE_PYOSYS
ifeq ($(ENABLE_READLINE),1)
CXXFLAGS += -DYOSYS_ENABLE_READLINE
@ -522,7 +501,19 @@ endif
ifeq ($(ENABLE_VERIFIC),1)
VERIFIC_DIR ?= /usr/local/src/verific_lib
VERIFIC_COMPONENTS ?= verilog vhdl database util containers hier_tree
VERIFIC_COMPONENTS ?= verilog database util containers hier_tree
ifneq ($(DISABLE_VERIFIC_VHDL),1)
VERIFIC_COMPONENTS += vhdl
CXXFLAGS += -DVERIFIC_VHDL_SUPPORT
else
ifneq ($(wildcard $(VERIFIC_DIR)/vhdl),)
VERIFIC_COMPONENTS += vhdl
endif
endif
ifneq ($(DISABLE_VERIFIC_EXTENSIONS),1)
VERIFIC_COMPONENTS += extensions
CXXFLAGS += -DYOSYSHQ_VERIFIC_EXTENSIONS
endif
CXXFLAGS += $(patsubst %,-I$(VERIFIC_DIR)/%,$(VERIFIC_COMPONENTS)) -DYOSYS_ENABLE_VERIFIC
ifeq ($(OS), Darwin)
LDLIBS += $(patsubst %,$(VERIFIC_DIR)/%/*-mac.a,$(VERIFIC_COMPONENTS)) -lz
@ -589,6 +580,7 @@ $(eval $(call add_include_file,kernel/yosys.h))
$(eval $(call add_include_file,kernel/hashlib.h))
$(eval $(call add_include_file,kernel/log.h))
$(eval $(call add_include_file,kernel/rtlil.h))
$(eval $(call add_include_file,kernel/binding.h))
$(eval $(call add_include_file,kernel/register.h))
$(eval $(call add_include_file,kernel/celltypes.h))
$(eval $(call add_include_file,kernel/celledges.h))
@ -599,15 +591,20 @@ $(eval $(call add_include_file,kernel/modtools.h))
$(eval $(call add_include_file,kernel/macc.h))
$(eval $(call add_include_file,kernel/utils.h))
$(eval $(call add_include_file,kernel/satgen.h))
$(eval $(call add_include_file,kernel/qcsat.h))
$(eval $(call add_include_file,kernel/ff.h))
$(eval $(call add_include_file,kernel/ffinit.h))
$(eval $(call add_include_file,kernel/fstdata.h))
$(eval $(call add_include_file,kernel/mem.h))
$(eval $(call add_include_file,libs/ezsat/ezsat.h))
$(eval $(call add_include_file,libs/ezsat/ezminisat.h))
$(eval $(call add_include_file,libs/fst/fstapi.h))
$(eval $(call add_include_file,libs/sha1/sha1.h))
$(eval $(call add_include_file,libs/json11/json11.hpp))
$(eval $(call add_include_file,passes/fsm/fsmdata.h))
$(eval $(call add_include_file,frontends/ast/ast.h))
$(eval $(call add_include_file,frontends/ast/ast_binding.h))
$(eval $(call add_include_file,frontends/blif/blifparse.h))
$(eval $(call add_include_file,backends/rtlil/rtlil_backend.h))
$(eval $(call add_include_file,backends/cxxrtl/cxxrtl.h))
$(eval $(call add_include_file,backends/cxxrtl/cxxrtl_vcd.h))
@ -617,12 +614,13 @@ $(eval $(call add_include_file,backends/cxxrtl/cxxrtl_vcd_capi.cc))
$(eval $(call add_include_file,backends/cxxrtl/cxxrtl_vcd_capi.h))
OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o
OBJS += kernel/binding.o
ifeq ($(ENABLE_ABC),1)
ifneq ($(ABCEXTERNAL),)
kernel/yosys.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"'
endif
endif
OBJS += kernel/cellaigs.o kernel/celledges.o kernel/satgen.o kernel/mem.o
OBJS += kernel/cellaigs.o kernel/celledges.o kernel/satgen.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/fstdata.o
kernel/log.o: CXXFLAGS += -DYOSYS_SRC='"$(YOSYS_SRC)"'
kernel/yosys.o: CXXFLAGS += -DYOSYS_DATDIR='"$(DATDIR)"' -DYOSYS_PROGRAM_PREFIX='"$(PROGRAM_PREFIX)"'
@ -646,6 +644,10 @@ OBJS += libs/minisat/SimpSolver.o
OBJS += libs/minisat/Solver.o
OBJS += libs/minisat/System.o
OBJS += libs/fst/fstapi.o
OBJS += libs/fst/fastlz.o
OBJS += libs/fst/lz4.o
include $(YOSYS_SRC)/frontends/*/Makefile.inc
include $(YOSYS_SRC)/passes/*/Makefile.inc
include $(YOSYS_SRC)/backends/*/Makefile.inc
@ -699,9 +701,9 @@ $(PROGRAM_PREFIX)yosys$(EXE): $(OBJS)
libyosys.so: $(filter-out kernel/driver.o,$(OBJS))
ifeq ($(OS), Darwin)
$(P) $(LD) -o libyosys.so -shared -Wl,-install_name,$(DESTDIR)$(LIBDIR)/libyosys.so $(LDFLAGS) $^ $(LDLIBS)
$(P) $(LD) -o libyosys.so -shared -Wl,-install_name,$(LIBDIR)/libyosys.so $(LDFLAGS) $^ $(LDLIBS)
else
$(P) $(LD) -o libyosys.so -shared -Wl,-soname,$(DESTDIR)$(LIBDIR)/libyosys.so $(LDFLAGS) $^ $(LDLIBS)
$(P) $(LD) -o libyosys.so -shared -Wl,-soname,$(LIBDIR)/libyosys.so $(LDFLAGS) $^ $(LDLIBS)
endif
%.o: %.cc
@ -749,7 +751,7 @@ ifneq ($(ABCREV),default)
$(Q) if test -d abc/.hg; then \
echo 'REEBE: NOP qverpgbel vf n ut jbexvat pbcl! Erzbir nop/ naq er-eha "znxr".' | tr 'A-Za-z' 'N-ZA-Mn-za-m'; false; \
fi
$(Q) if ( cd abc 2> /dev/null && ! git diff-index --quiet HEAD; ); then \
$(Q) if test -d abc && ! git -C abc diff-index --quiet HEAD; then \
echo 'REEBE: NOP pbagnvaf ybpny zbqvsvpngvbaf! Frg NOPERI=qrsnhyg va Lbflf Znxrsvyr!' | tr 'A-Za-z' 'N-ZA-Mn-za-m'; false; \
fi
# set a variable so the test fails if git fails to run - when comparing outputs directly, empty string would match empty string
@ -761,7 +763,7 @@ ifneq ($(ABCREV),default)
fi
endif
$(Q) rm -f abc/abc-[0-9a-f]*
$(Q) cd abc && $(MAKE) $(S) $(ABCMKARGS) $(if $(filter %.a,$@),PROG="abc-$(ABCREV)",PROG="abc-$(ABCREV)$(EXE)") MSG_PREFIX="$(eval P_OFFSET = 5)$(call P_SHOW)$(eval P_OFFSET = 10) ABC: " $(if $(filter %.a,$@),libabc-$(ABCREV).a)
$(Q) $(MAKE) -C abc $(S) $(ABCMKARGS) $(if $(filter %.a,$@),PROG="abc-$(ABCREV)",PROG="abc-$(ABCREV)$(EXE)") MSG_PREFIX="$(eval P_OFFSET = 5)$(call P_SHOW)$(eval P_OFFSET = 10) ABC: " $(if $(filter %.a,$@),libabc-$(ABCREV).a)
ifeq ($(ABCREV),default)
.PHONY: abc/abc-$(ABCREV)$(EXE)
@ -804,6 +806,7 @@ test: $(TARGETS) $(EXTRA_TARGETS)
+cd tests/svinterfaces && bash run-test.sh $(SEEDOPT)
+cd tests/svtypes && bash run-test.sh $(SEEDOPT)
+cd tests/proc && bash run-test.sh
+cd tests/blif && bash run-test.sh
+cd tests/opt && bash run-test.sh
+cd tests/aiger && bash run-test.sh $(ABCOPT)
+cd tests/arch && bash run-test.sh
@ -816,6 +819,8 @@ test: $(TARGETS) $(EXTRA_TARGETS)
+cd tests/arch/gowin && bash run-test.sh $(SEEDOPT)
+cd tests/arch/intel_alm && bash run-test.sh $(SEEDOPT)
+cd tests/arch/nexus && bash run-test.sh $(SEEDOPT)
+cd tests/arch/quicklogic && bash run-test.sh $(SEEDOPT)
+cd tests/arch/gatemate && bash run-test.sh $(SEEDOPT)
+cd tests/rpc && bash run-test.sh
+cd tests/memfile && bash run-test.sh
+cd tests/verilog && bash run-test.sh
@ -954,7 +959,7 @@ ifeq ($(ENABLE_ABC),1)
cp -r $(PROGRAM_PREFIX)yosys-abc.exe abc/lib/x86/pthreadVC2.dll yosys-win32-mxebin-$(YOSYS_VER)/
endif
echo -en 'This is Yosys $(YOSYS_VER) for Win32.\r\n' > yosys-win32-mxebin-$(YOSYS_VER)/readme.txt
echo -en 'Documentation at http://www.clifford.at/yosys/.\r\n' >> yosys-win32-mxebin-$(YOSYS_VER)/readme.txt
echo -en 'Documentation at https://yosyshq.net/yosys/.\r\n' >> yosys-win32-mxebin-$(YOSYS_VER)/readme.txt
zip -r yosys-win32-mxebin-$(YOSYS_VER).zip yosys-win32-mxebin-$(YOSYS_VER)/
endif

38
README.md
View File

@ -1,7 +1,7 @@
```
yosys -- Yosys Open SYnthesis Suite
Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com>
Copyright (C) 2012 - 2020 Claire Xenia Wolf <claire@yosyshq.com>
Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
@ -38,13 +38,13 @@ Web Site and Other Resources
============================
More information and documentation can be found on the Yosys web site:
- http://www.clifford.at/yosys/
- https://yosyshq.net/yosys/
The "Documentation" page on the web site contains links to more resources,
including a manual that even describes some of the Yosys internals:
- http://www.clifford.at/yosys/documentation.html
- https://yosyshq.net/yosys/documentation.html
The file `CodingReadme` in this directory contains additional information
The directory `guidelines` contains additional information
for people interested in using the Yosys C++ APIs.
Users interested in formal verification might want to use the formal verification
@ -53,8 +53,23 @@ front-end for Yosys, SymbiYosys:
- https://github.com/YosysHQ/SymbiYosys
Setup
======
Installation
============
Yosys is part of the [Tabby CAD Suite](https://www.yosyshq.com/tabby-cad-datasheet) and the [OSS CAD Suite](https://github.com/YosysHQ/oss-cad-suite-build)! The easiest way to use yosys is to install the binary software suite, which contains all required dependencies and related tools.
* [Contact YosysHQ](https://www.yosyshq.com/contact) for a [Tabby CAD Suite](https://www.yosyshq.com/tabby-cad-datasheet) Evaluation License and download link
* OR go to https://github.com/YosysHQ/oss-cad-suite-build/releases to download the free OSS CAD Suite
* Follow the [Install Instructions on GitHub](https://github.com/YosysHQ/oss-cad-suite-build#installation)
Make sure to get a Tabby CAD Suite Evaluation License if you need features such as industry-grade SystemVerilog and VHDL parsers!
For more information about the difference between Tabby CAD Suite and the OSS CAD Suite, please visit https://www.yosyshq.com/tabby-cad-datasheet
Many Linux distributions also provide Yosys binaries, some more up to date than others. Check with your package manager!
Building from Source
====================
You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is
recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make.
@ -90,10 +105,6 @@ For Cygwin use the following command to install all prerequisites, or select the
setup-x86_64.exe -q --packages=bison,flex,gcc-core,gcc-g++,git,libffi-devel,libreadline-devel,make,pkg-config,python3,tcl-devel,boost-build,zlib-devel
There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well
as a source distribution for Visual Studio. Visit the Yosys download page for
more information: http://www.clifford.at/yosys/download.html
To configure the build system to use a specific compiler, use one of
$ make config-clang
@ -489,6 +500,11 @@ Verilog Attributes and non-standard features
for use in blackboxes and whiteboxes. Use ``read_verilog -specify`` to
enable this functionality. (By default these blocks are ignored.)
- The ``reprocess_after`` internal attribute is used by the Verilog frontend to
mark cells with bindings which might depend on the specified instantiated
module. Modules with such cells will be reprocessed during the ``hierarchy``
pass once the referenced module definition(s) become available.
Non-standard or SystemVerilog features for formal verification
==============================================================
@ -568,7 +584,7 @@ Building the documentation
==========================
Note that there is no need to build the manual if you just want to read it.
Simply download the PDF from http://www.clifford.at/yosys/documentation.html
Simply download the PDF from https://yosyshq.net/yosys/documentation.html
instead.
On Ubuntu, texlive needs these packages to be able to build the manual:

2
backends/aiger/aiger.cc
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

43
backends/aiger/xaiger.cc
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
* 2019 Eddie Hung <eddie@fpgeh.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
@ -156,7 +156,7 @@ struct XAigerWriter
// promote keep wires
for (auto wire : module->wires())
if (wire->get_bool_attribute(ID::keep) || wire->get_bool_attribute(ID::abc9_keep))
if (wire->get_bool_attribute(ID::keep))
sigmap.add(wire);
for (auto wire : module->wires()) {
@ -177,11 +177,10 @@ struct XAigerWriter
undriven_bits.insert(bit);
unused_bits.insert(bit);
bool keep = wire->get_bool_attribute(ID::abc9_keep);
if (wire->port_input || keep)
if (wire->port_input)
input_bits.insert(bit);
keep = keep || wire->get_bool_attribute(ID::keep);
bool keep = wire->get_bool_attribute(ID::keep);
if (wire->port_output || keep) {
if (bit != wirebit)
alias_map[wirebit] = bit;
@ -262,26 +261,27 @@ struct XAigerWriter
if (!timing.count(inst_module->name))
timing.setup_module(inst_module);
auto &t = timing.at(inst_module->name).arrival;
for (const auto &conn : cell->connections()) {
auto port_wire = inst_module->wire(conn.first);
if (!port_wire->port_output)
for (auto &i : timing.at(inst_module->name).arrival) {
if (!cell->hasPort(i.first.name))
continue;
for (int i = 0; i < GetSize(conn.second); i++) {
auto d = t.at(TimingInfo::NameBit(conn.first,i), 0);
if (d == 0)
continue;
auto port_wire = inst_module->wire(i.first.name);
log_assert(port_wire->port_output);
auto d = i.second.first;
if (d == 0)
continue;
auto offset = i.first.offset;
#ifndef NDEBUG
if (ys_debug(1)) {
static std::set<std::tuple<IdString,IdString,int>> seen;
if (seen.emplace(inst_module->name, conn.first, i).second) log("%s.%s[%d] abc9_arrival = %d\n",
log_id(cell->type), log_id(conn.first), i, d);
}
#endif
arrival_times[conn.second[i]] = d;
if (ys_debug(1)) {
static pool<std::pair<IdString,TimingInfo::NameBit>> seen;
if (seen.emplace(inst_module->name, i.first).second) log("%s.%s[%d] abc9_arrival = %d\n",
log_id(cell->type), log_id(i.first.name), offset, d);
}
#endif
arrival_times[cell->getPort(i.first.name)[offset]] = d;
}
if (abc9_flop)
@ -432,7 +432,8 @@ struct XAigerWriter
// that has been padded to its full width
if (bit == State::Sx)
continue;
log_assert(!aig_map.count(bit));
if (aig_map.count(bit))
log_error("Visited AIG node more than once; this could be a combinatorial loop that has not been broken\n");
aig_map[bit] = 2*aig_m;
}

2
backends/blif/blif.cc
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

24
backends/btor/btor.cc
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -18,7 +18,7 @@
*/
// [[CITE]] Btor2 , BtorMC and Boolector 3.0
// Aina Niemetz, Mathias Preiner, Clifford Wolf, Armin Biere
// Aina Niemetz, Mathias Preiner, C. Wolf, Armin Biere
// Computer Aided Verification - 30th International Conference, CAV 2018
// https://cs.stanford.edu/people/niemetz/publication/2018/niemetzpreinerwolfbiere-cav18/
@ -708,7 +708,7 @@ struct BtorWorker
goto okay;
}
if (cell->type.in(ID($mem), ID($memrd), ID($memwr), ID($meminit)))
if (cell->is_mem_cell())
{
Mem *mem = mem_cells[cell];
@ -728,10 +728,11 @@ struct BtorWorker
log_error("Memory %s.%s has mixed async/sync write ports.\n",
log_id(module), log_id(mem->memid));
for (auto &port : mem->rd_ports)
for (auto &port : mem->rd_ports) {
if (port.clk_enable)
log_error("Memory %s.%s has sync read ports.\n",
log_error("Memory %s.%s has sync read ports. Please use memory_nordff to convert them first.\n",
log_id(module), log_id(mem->memid));
}
int data_sid = get_bv_sid(mem->width);
int bool_sid = get_bv_sid(1);
@ -864,7 +865,7 @@ struct BtorWorker
log_error("Unsupported cell type %s for cell %s.%s -- please run `dffunmap` before `write_btor`.\n",
log_id(cell->type), log_id(module), log_id(cell));
}
if (cell->type.in(ID($adff), ID($adffe), ID($dffsr), ID($dffsre)) || cell->type.str().substr(0, 5) == "$_DFF") {
if (cell->type.in(ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($dffsr), ID($dffsre)) || cell->type.str().substr(0, 5) == "$_DFF" || cell->type.str().substr(0, 7) == "$_ALDFF") {
log_error("Unsupported cell type %s for cell %s.%s -- please run `async2sync; dffunmap` or `clk2fflogic` before `write_btor`.\n",
log_id(cell->type), log_id(module), log_id(cell));
}
@ -1080,10 +1081,12 @@ struct BtorWorker
memories = Mem::get_all_memories(module);
dict<IdString, Mem*> mem_dict;
for (auto &mem : memories)
for (auto &mem : memories) {
mem.narrow();
mem_dict[mem.memid] = &mem;
}
for (auto cell : module->cells())
if (cell->type.in(ID($mem), ID($memwr), ID($memrd), ID($meminit)))
if (cell->is_mem_cell())
mem_cells[cell] = mem_dict[cell->parameters.at(ID::MEMID).decode_string()];
btorf_push("inputs");
@ -1396,6 +1399,11 @@ struct BtorBackend : public Backend {
log_header(design, "Executing BTOR backend.\n");
log_push();
Pass::call(design, "bmuxmap");
Pass::call(design, "demuxmap");
log_pop();
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{

102
backends/cxxrtl/cxxrtl.h
View File

@ -457,6 +457,42 @@ struct value : public expr_base<value<Bits>> {
return shr<AmountBits, /*Signed=*/true>(amount);
}
template<size_t ResultBits, size_t SelBits>
value<ResultBits> bmux(const value<SelBits> &sel) const {
static_assert(ResultBits << SelBits == Bits, "invalid sizes used in bmux()");
size_t amount = sel.data[0] * ResultBits;
size_t shift_chunks = amount / chunk::bits;
size_t shift_bits = amount % chunk::bits;
value<ResultBits> result;
chunk::type carry = 0;
if (ResultBits % chunk::bits + shift_bits > chunk::bits)
carry = data[result.chunks + shift_chunks] << (chunk::bits - shift_bits);
for (size_t n = 0; n < result.chunks; n++) {
result.data[result.chunks - 1 - n] = carry | (data[result.chunks + shift_chunks - 1 - n] >> shift_bits);
carry = (shift_bits == 0) ? 0
: data[result.chunks + shift_chunks - 1 - n] << (chunk::bits - shift_bits);
}
return result;
}
template<size_t ResultBits, size_t SelBits>
value<ResultBits> demux(const value<SelBits> &sel) const {
static_assert(Bits << SelBits == ResultBits, "invalid sizes used in demux()");
size_t amount = sel.data[0] * Bits;
size_t shift_chunks = amount / chunk::bits;
size_t shift_bits = amount % chunk::bits;
value<ResultBits> result;
chunk::type carry = 0;
for (size_t n = 0; n < chunks; n++) {
result.data[shift_chunks + n] = (data[n] << shift_bits) | carry;
carry = (shift_bits == 0) ? 0
: data[n] >> (chunk::bits - shift_bits);
}
if (Bits % chunk::bits + shift_bits > chunk::bits)
result.data[shift_chunks + chunks] = carry;
return result;
}
size_t ctpop() const {
size_t count = 0;
for (size_t n = 0; n < chunks; n++) {
@ -722,50 +758,32 @@ std::ostream &operator<<(std::ostream &os, const wire<Bits> &val) {
template<size_t Width>
struct memory {
std::vector<value<Width>> data;
const size_t depth;
std::unique_ptr<value<Width>[]> data;
size_t depth() const {
return data.size();
}
memory() = delete;
explicit memory(size_t depth) : data(depth) {}
explicit memory(size_t depth) : depth(depth), data(new value<Width>[depth]) {}
memory(const memory<Width> &) = delete;
memory<Width> &operator=(const memory<Width> &) = delete;
memory(memory<Width> &&) = default;
memory<Width> &operator=(memory<Width> &&) = default;
// The only way to get the compiler to put the initializer in .rodata and do not copy it on stack is to stuff it
// into a plain array. You'd think an std::initializer_list would work here, but it doesn't, because you can't
// construct an initializer_list in a constexpr (or something) and so if you try to do that the whole thing is
// first copied on the stack (probably overflowing it) and then again into `data`.
template<size_t Size>
struct init {
size_t offset;
value<Width> data[Size];
};
template<size_t... InitSize>
explicit memory(size_t depth, const init<InitSize> &...init) : data(depth) {
data.resize(depth);
// This utterly reprehensible construct is the most reasonable way to apply a function to every element
// of a parameter pack, if the elements all have different types and so cannot be cast to an initializer list.
auto _ = {std::move(std::begin(init.data), std::end(init.data), data.begin() + init.offset)...};
(void)_;
memory<Width> &operator=(memory<Width> &&other) {
assert(depth == other.depth);
data = std::move(other.data);
write_queue = std::move(other.write_queue);
return *this;
}
// An operator for direct memory reads. May be used at any time during the simulation.
const value<Width> &operator [](size_t index) const {
assert(index < data.size());
assert(index < depth);
return data[index];
}
// An operator for direct memory writes. May only be used before the simulation is started. If used
// after the simulation is started, the design may malfunction.
value<Width> &operator [](size_t index) {
assert(index < data.size());
assert(index < depth);
return data[index];
}
@ -790,7 +808,7 @@ struct memory {
std::vector<write> write_queue;
void update(size_t index, const value<Width> &val, const value<Width> &mask, int priority = 0) {
assert(index < data.size());
assert(index < depth);
// Queue up the write while keeping the queue sorted by priority.
write_queue.insert(
std::upper_bound(write_queue.begin(), write_queue.end(), priority,
@ -947,9 +965,9 @@ struct debug_item : ::cxxrtl_object {
flags = 0;
width = Width;
lsb_at = 0;
depth = item.data.size();
depth = item.depth;
zero_at = zero_offset;
curr = item.data.empty() ? nullptr : item.data[0].data;
curr = item.data ? item.data[0].data : nullptr;
next = nullptr;
outline = nullptr;
}
@ -999,6 +1017,22 @@ struct debug_item : ::cxxrtl_object {
next = nullptr;
outline = &group;
}
template<size_t Bits, class IntegerT>
IntegerT get() const {
assert(width == Bits && depth == 1);
value<Bits> item;
std::copy(curr, curr + value<Bits>::chunks, item.data);
return item.template get<IntegerT>();
}
template<size_t Bits, class IntegerT>
void set(IntegerT other) const {
assert(width == Bits && depth == 1);
value<Bits> item;
item.template set<IntegerT>(other);
std::copy(item.data, item.data + value<Bits>::chunks, next);
}
};
static_assert(std::is_standard_layout<debug_item>::value, "debug_item is not compatible with C layout");
@ -1035,9 +1069,9 @@ struct debug_items {
}
};
// Tag class to disambiguate module move constructor and module constructor that takes black boxes
// out of another instance of the module.
struct adopt {};
// Tag class to disambiguate the default constructor used by the toplevel module that calls reset(),
// and the constructor of interior modules that should not call it.
struct interior {};
struct module {
module() {}

891
backends/cxxrtl/cxxrtl_backend.cc
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File diff suppressed because it is too large Load Diff

15
backends/cxxrtl/cxxrtl_vcd.h
View File

@ -69,12 +69,25 @@ class vcd_writer {
} while (ident != 0);
}
void emit_name(const std::string &name) {
for (char c : name) {
if (c == ':') {
// Due to a bug, GTKWave cannot parse a colon in the variable name, causing the VCD file
// to be unreadable. It cannot be escaped either, so replace it with the sideways colon.
buffer += "..";
} else {
buffer += c;
}
}
}
void emit_var(const variable &var, const std::string &type, const std::string &name,
size_t lsb_at, bool multipart) {
assert(!streaming);
buffer += "$var " + type + " " + std::to_string(var.width) + " ";
emit_ident(var.ident);
buffer += " " + name;
buffer += " ";
emit_name(name);
if (multipart || name.back() == ']' || lsb_at != 0) {
if (var.width == 1)
buffer += " [" + std::to_string(lsb_at) + "]";

2
backends/edif/edif.cc
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

362
backends/firrtl/firrtl.cc
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -23,6 +23,7 @@
#include "kernel/celltypes.h"
#include "kernel/cellaigs.h"
#include "kernel/log.h"
#include "kernel/mem.h"
#include <algorithm>
#include <string>
#include <vector>
@ -366,126 +367,6 @@ struct FirrtlWorker
RTLIL::Design *design;
std::string indent;
// Define read/write ports and memories.
// We'll collect their definitions and emit the corresponding FIRRTL definitions at the appropriate point in module construction.
// For the moment, we don't handle $readmemh or $readmemb.
// These will be part of a subsequent PR.
struct read_port {
string name;
bool clk_enable;
bool clk_parity;
bool transparent;
RTLIL::SigSpec clk;
RTLIL::SigSpec ena;
RTLIL::SigSpec addr;
read_port(string name, bool clk_enable, bool clk_parity, bool transparent, RTLIL::SigSpec clk, RTLIL::SigSpec ena, RTLIL::SigSpec addr) : name(name), clk_enable(clk_enable), clk_parity(clk_parity), transparent(transparent), clk(clk), ena(ena), addr(addr) {
// Current (3/13/2019) conventions:
// generate a constant 0 for clock and a constant 1 for enable if they are undefined.
if (!clk.is_fully_def())
this->clk = SigSpec(State::S0);
if (!ena.is_fully_def())
this->ena = SigSpec(State::S1);
}
string gen_read(const char * indent) {
string addr_expr = make_expr(addr);
string ena_expr = make_expr(ena);
string clk_expr = make_expr(clk);
string addr_str = stringf("%s%s.addr <= %s\n", indent, name.c_str(), addr_expr.c_str());
string ena_str = stringf("%s%s.en <= %s\n", indent, name.c_str(), ena_expr.c_str());
string clk_str = stringf("%s%s.clk <= asClock(%s)\n", indent, name.c_str(), clk_expr.c_str());
return addr_str + ena_str + clk_str;
}
};
struct write_port : read_port {
RTLIL::SigSpec mask;
write_port(string name, bool clk_enable, bool clk_parity, bool transparent, RTLIL::SigSpec clk, RTLIL::SigSpec ena, RTLIL::SigSpec addr, RTLIL::SigSpec mask) : read_port(name, clk_enable, clk_parity, transparent, clk, ena, addr), mask(mask) {
if (!clk.is_fully_def())
this->clk = SigSpec(RTLIL::Const(0));
if (!ena.is_fully_def())
this->ena = SigSpec(RTLIL::Const(0));
if (!mask.is_fully_def())
this->ena = SigSpec(RTLIL::Const(1));
}
string gen_read(const char * /* indent */) {
log_error("gen_read called on write_port: %s\n", name.c_str());
return stringf("gen_read called on write_port: %s\n", name.c_str());
}
string gen_write(const char * indent) {
string addr_expr = make_expr(addr);
string ena_expr = make_expr(ena);
string clk_expr = make_expr(clk);
string mask_expr = make_expr(mask);
string mask_str = stringf("%s%s.mask <= %s\n", indent, name.c_str(), mask_expr.c_str());
string addr_str = stringf("%s%s.addr <= %s\n", indent, name.c_str(), addr_expr.c_str());
string ena_str = stringf("%s%s.en <= %s\n", indent, name.c_str(), ena_expr.c_str());
string clk_str = stringf("%s%s.clk <= asClock(%s)\n", indent, name.c_str(), clk_expr.c_str());
return addr_str + ena_str + clk_str + mask_str;
}
};
/* Memories defined within this module. */
struct memory {
Cell *pCell; // for error reporting
string name; // memory name
int abits; // number of address bits
int size; // size (in units) of the memory
int width; // size (in bits) of each element
int read_latency;
int write_latency;
vector<read_port> read_ports;
vector<write_port> write_ports;
std::string init_file;
std::string init_file_srcFileSpec;
string srcLine;
memory(Cell *pCell, string name, int abits, int size, int width) : pCell(pCell), name(name), abits(abits), size(size), width(width), read_latency(0), write_latency(1), init_file(""), init_file_srcFileSpec("") {
// Provide defaults for abits or size if one (but not the other) is specified.
if (this->abits == 0 && this->size != 0) {
this->abits = ceil_log2(this->size);
} else if (this->abits != 0 && this->size == 0) {
this->size = 1 << this->abits;
}
// Sanity-check this construction.
if (this->name == "") {
log_error("Nameless memory%s\n", this->atLine());
}
if (this->abits == 0 && this->size == 0) {
log_error("Memory %s has zero address bits and size%s\n", this->name.c_str(), this->atLine());
}
if (this->width == 0) {
log_error("Memory %s has zero width%s\n", this->name.c_str(), this->atLine());
}
}
// We need a default constructor for the dict insert.
memory() : pCell(0), read_latency(0), write_latency(1), init_file(""), init_file_srcFileSpec(""){}
const char *atLine() {
if (srcLine == "") {
if (pCell) {
auto p = pCell->attributes.find(ID::src);
srcLine = " at " + p->second.decode_string();
}
}
return srcLine.c_str();
}
void add_memory_read_port(read_port &rp) {
read_ports.push_back(rp);
}
void add_memory_write_port(write_port &wp) {
write_ports.push_back(wp);
}
void add_memory_file(std::string init_file, std::string init_file_srcFileSpec) {
this->init_file = init_file;
this->init_file_srcFileSpec = init_file_srcFileSpec;
}
};
dict<string, memory> memories;
void register_memory(memory &m)
{
memories[m.name] = m;
}
void register_reverse_wire_map(string id, SigSpec sig)
{
for (int i = 0; i < GetSize(sig); i++)
@ -658,7 +539,11 @@ struct FirrtlWorker
{
std::string moduleFileinfo = getFileinfo(module);
f << stringf(" module %s: %s\n", make_id(module->name), moduleFileinfo.c_str());
vector<string> port_decls, wire_decls, cell_exprs, wire_exprs;
vector<string> port_decls, wire_decls, mem_exprs, cell_exprs, wire_exprs;
std::vector<Mem> memories = Mem::get_all_memories(module);
for (auto &mem : memories)
mem.narrow();
for (auto wire : module->wires())
{
@ -686,14 +571,15 @@ struct FirrtlWorker
for (auto cell : module->cells())
{
static Const ndef(0, 0);
Const ndef(0, 0);
// Is this cell is a module instance?
if (cell->type[0] != '$')
if (module->design->module(cell->type))
{
process_instance(cell, wire_exprs);
continue;
}
// Not a module instance. Set up cell properties
bool extract_y_bits = false; // Assume no extraction of final bits will be required.
int a_width = cell->parameters.at(ID::A_WIDTH, ndef).as_int(); // The width of "A"
@ -1004,126 +890,9 @@ struct FirrtlWorker
continue;
}
if (cell->type.in(ID($mem)))
if (cell->is_mem_cell())
{
string mem_id = make_id(cell->name);
int abits = cell->parameters.at(ID::ABITS).as_int();
int width = cell->parameters.at(ID::WIDTH).as_int();
int size = cell->parameters.at(ID::SIZE).as_int();
memory m(cell, mem_id, abits, size, width);
int rd_ports = cell->parameters.at(ID::RD_PORTS).as_int();
int wr_ports = cell->parameters.at(ID::WR_PORTS).as_int();
Const initdata = cell->parameters.at(ID::INIT);
for (State bit : initdata.bits)
if (bit != State::Sx)
log_error("Memory with initialization data: %s.%s\n", log_id(module), log_id(cell));
Const rd_clk_enable = cell->parameters.at(ID::RD_CLK_ENABLE);
Const wr_clk_enable = cell->parameters.at(ID::WR_CLK_ENABLE);
Const wr_clk_polarity = cell->parameters.at(ID::WR_CLK_POLARITY);
int offset = cell->parameters.at(ID::OFFSET).as_int();
if (offset != 0)
log_error("Memory with nonzero offset: %s.%s\n", log_id(module), log_id(cell));
for (int i = 0; i < rd_ports; i++)
{
if (rd_clk_enable[i] != State::S0)
log_error("Clocked read port %d on memory %s.%s.\n", i, log_id(module), log_id(cell));
SigSpec addr_sig = cell->getPort(ID::RD_ADDR).extract(i*abits, abits);
SigSpec data_sig = cell->getPort(ID::RD_DATA).extract(i*width, width);
string addr_expr = make_expr(addr_sig);
string name(stringf("%s.r%d", m.name.c_str(), i));
bool clk_enable = false;
bool clk_parity = true;
bool transparency = false;
SigSpec ena_sig = RTLIL::SigSpec(RTLIL::State::S1, 1);
SigSpec clk_sig = RTLIL::SigSpec(RTLIL::State::S0, 1);
read_port rp(name, clk_enable, clk_parity, transparency, clk_sig, ena_sig, addr_sig);
m.add_memory_read_port(rp);
cell_exprs.push_back(rp.gen_read(indent.c_str()));
register_reverse_wire_map(stringf("%s.data", name.c_str()), data_sig);
}
for (int i = 0; i < wr_ports; i++)
{
if (wr_clk_enable[i] != State::S1)
log_error("Unclocked write port %d on memory %s.%s.\n", i, log_id(module), log_id(cell));
if (wr_clk_polarity[i] != State::S1)
log_error("Negedge write port %d on memory %s.%s.\n", i, log_id(module), log_id(cell));
string name(stringf("%s.w%d", m.name.c_str(), i));
bool clk_enable = true;
bool clk_parity = true;
bool transparency = false;
SigSpec addr_sig =cell->getPort(ID::WR_ADDR).extract(i*abits, abits);
string addr_expr = make_expr(addr_sig);
SigSpec data_sig =cell->getPort(ID::WR_DATA).extract(i*width, width);
string data_expr = make_expr(data_sig);
SigSpec clk_sig = cell->getPort(ID::WR_CLK).extract(i);
string clk_expr = make_expr(clk_sig);
SigSpec wen_sig = cell->getPort(ID::WR_EN).extract(i*width, width);
string wen_expr = make_expr(wen_sig[0]);
for (int i = 1; i < GetSize(wen_sig); i++)
if (wen_sig[0] != wen_sig[i])
log_error("Complex write enable on port %d on memory %s.%s.\n", i, log_id(module), log_id(cell));
SigSpec mask_sig = RTLIL::SigSpec(RTLIL::State::S1, 1);
write_port wp(name, clk_enable, clk_parity, transparency, clk_sig, wen_sig[0], addr_sig, mask_sig);
m.add_memory_write_port(wp);
cell_exprs.push_back(stringf("%s%s.data <= %s\n", indent.c_str(), name.c_str(), data_expr.c_str()));
cell_exprs.push_back(wp.gen_write(indent.c_str()));
}
register_memory(m);
continue;
}
if (cell->type.in(ID($memwr), ID($memrd), ID($meminit)))
{
std::string cell_type = fid(cell->type);
std::string mem_id = make_id(cell->parameters[ID::MEMID].decode_string());
int abits = cell->parameters.at(ID::ABITS).as_int();
int width = cell->parameters.at(ID::WIDTH).as_int();
memory *mp = nullptr;
if (cell->type == ID($meminit) ) {
log_error("$meminit (%s.%s.%s) currently unsupported\n", log_id(module), log_id(cell), mem_id.c_str());
} else {
// It's a $memwr or $memrd. Remember the read/write port parameters for the eventual FIRRTL memory definition.
auto addrSig = cell->getPort(ID::ADDR);
auto dataSig = cell->getPort(ID::DATA);
auto enableSig = cell->getPort(ID::EN);
auto clockSig = cell->getPort(ID::CLK);
Const clk_enable = cell->parameters.at(ID::CLK_ENABLE);
Const clk_polarity = cell->parameters.at(ID::CLK_POLARITY);
// Do we already have an entry for this memory?
if (memories.count(mem_id) == 0) {
memory m(cell, mem_id, abits, 0, width);
register_memory(m);
}
mp = &memories.at(mem_id);
int portNum = 0;
bool transparency = false;
string data_expr = make_expr(dataSig);
if (cell->type.in(ID($memwr))) {
portNum = (int) mp->write_ports.size();
write_port wp(stringf("%s.w%d", mem_id.c_str(), portNum), clk_enable.as_bool(), clk_polarity.as_bool(), transparency, clockSig, enableSig, addrSig, dataSig);
mp->add_memory_write_port(wp);
cell_exprs.push_back(stringf("%s%s.data <= %s\n", indent.c_str(), wp.name.c_str(), data_expr.c_str()));
cell_exprs.push_back(wp.gen_write(indent.c_str()));
} else if (cell->type.in(ID($memrd))) {
portNum = (int) mp->read_ports.size();
read_port rp(stringf("%s.r%d", mem_id.c_str(), portNum), clk_enable.as_bool(), clk_polarity.as_bool(), transparency, clockSig, enableSig, addrSig);
mp->add_memory_read_port(rp);
cell_exprs.push_back(rp.gen_read(indent.c_str()));
register_reverse_wire_map(stringf("%s.data", rp.name.c_str()), dataSig);
}
}
// Will be handled below, as part of a Mem.
continue;
}
@ -1145,12 +914,6 @@ struct FirrtlWorker
continue;
}
// This may be a parameterized module - paramod.
if (cell->type.begins_with("$paramod"))
{
process_instance(cell, wire_exprs);
continue;
}
if (cell->type == ID($shiftx)) {
// assign y = a[b +: y_width];
// We'll extract the correct bits as part of the primop.
@ -1215,6 +978,82 @@ struct FirrtlWorker
log_error("Cell type not supported: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell));
}
for (auto &mem : memories) {
string mem_id = make_id(mem.memid);
Const init_data = mem.get_init_data();
if (!init_data.is_fully_undef())
log_error("Memory with initialization data: %s.%s\n", log_id(module), log_id(mem.memid));
if (mem.start_offset != 0)
log_error("Memory with nonzero offset: %s.%s\n", log_id(module), log_id(mem.memid));
for (int i = 0; i < GetSize(mem.rd_ports); i++)
{
auto &port = mem.rd_ports[i];
string port_name(stringf("%s.r%d", mem_id.c_str(), i));
if (port.clk_enable)
log_error("Clocked read port %d on memory %s.%s.\n", i, log_id(module), log_id(mem.memid));
std::ostringstream rpe;
string addr_expr = make_expr(port.addr);
string ena_expr = make_expr(State::S1);
string clk_expr = make_expr(State::S0);
rpe << stringf("%s%s.addr <= %s\n", indent.c_str(), port_name.c_str(), addr_expr.c_str());
rpe << stringf("%s%s.en <= %s\n", indent.c_str(), port_name.c_str(), ena_expr.c_str());
rpe << stringf("%s%s.clk <= asClock(%s)\n", indent.c_str(), port_name.c_str(), clk_expr.c_str());
cell_exprs.push_back(rpe.str());
register_reverse_wire_map(stringf("%s.data", port_name.c_str()), port.data);
}
for (int i = 0; i < GetSize(mem.wr_ports); i++)
{
auto &port = mem.wr_ports[i];
string port_name(stringf("%s.w%d", mem_id.c_str(), i));
if (!port.clk_enable)
log_error("Unclocked write port %d on memory %s.%s.\n", i, log_id(module), log_id(mem.memid));
if (!port.clk_polarity)
log_error("Negedge write port %d on memory %s.%s.\n", i, log_id(module), log_id(mem.memid));
for (int i = 1; i < GetSize(port.en); i++)
if (port.en[0] != port.en[i])
log_error("Complex write enable on port %d on memory %s.%s.\n", i, log_id(module), log_id(mem.memid));
std::ostringstream wpe;
string data_expr = make_expr(port.data);
string addr_expr = make_expr(port.addr);
string ena_expr = make_expr(port.en[0]);
string clk_expr = make_expr(port.clk);
string mask_expr = make_expr(State::S1);
wpe << stringf("%s%s.data <= %s\n", indent.c_str(), port_name.c_str(), data_expr.c_str());
wpe << stringf("%s%s.addr <= %s\n", indent.c_str(), port_name.c_str(), addr_expr.c_str());
wpe << stringf("%s%s.en <= %s\n", indent.c_str(), port_name.c_str(), ena_expr.c_str());
wpe << stringf("%s%s.clk <= asClock(%s)\n", indent.c_str(), port_name.c_str(), clk_expr.c_str());
wpe << stringf("%s%s.mask <= %s\n", indent.c_str(), port_name.c_str(), mask_expr.c_str());
cell_exprs.push_back(wpe.str());
}
std::ostringstream me;
me << stringf(" mem %s:\n", mem_id.c_str());
me << stringf(" data-type => UInt<%d>\n", mem.width);
me << stringf(" depth => %d\n", mem.size);
for (int i = 0; i < GetSize(mem.rd_ports); i++)
me << stringf(" reader => r%d\n", i);
for (int i = 0; i < GetSize(mem.wr_ports); i++)
me << stringf(" writer => w%d\n", i);
me << stringf(" read-latency => %d\n", 0);
me << stringf(" write-latency => %d\n", 1);
me << stringf(" read-under-write => undefined\n");
mem_exprs.push_back(me.str());
}
for (auto conn : module->connections())
{
string y_id = next_id();
@ -1316,22 +1155,9 @@ struct FirrtlWorker
f << stringf("\n");
// If we have any memory definitions, output them.
for (auto kv : memories) {
memory &m = kv.second;
f << stringf(" mem %s:\n", m.name.c_str());
f << stringf(" data-type => UInt<%d>\n", m.width);
f << stringf(" depth => %d\n", m.size);
for (int i = 0; i < (int) m.read_ports.size(); i += 1) {
f << stringf(" reader => r%d\n", i);
}
for (int i = 0; i < (int) m.write_ports.size(); i += 1) {
f << stringf(" writer => w%d\n", i);
}
f << stringf(" read-latency => %d\n", m.read_latency);
f << stringf(" write-latency => %d\n", m.write_latency);
f << stringf(" read-under-write => undefined\n");
}
for (auto str : mem_exprs)
f << str;
f << stringf("\n");
for (auto str : cell_exprs)
@ -1362,6 +1188,8 @@ struct FirrtlBackend : public Backend {
log("Write a FIRRTL netlist of the current design.\n");
log("The following commands are executed by this command:\n");
log(" pmuxtree\n");
log(" bmuxmap\n");
log(" demuxmap\n");
log("\n");
}
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
@ -1384,7 +1212,9 @@ struct FirrtlBackend : public Backend {
log_header(design, "Executing FIRRTL backend.\n");
log_push();
Pass::call(design, stringf("pmuxtree"));
Pass::call(design, "pmuxtree");
Pass::call(design, "bmuxmap");
Pass::call(design, "demuxmap");
namecache.clear();
autoid_counter = 0;

4
backends/intersynth/intersynth.cc
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -68,7 +68,7 @@ struct IntersynthBackend : public Backend {
log(" only write selected modules. modules must be selected entirely or\n");
log(" not at all.\n");
log("\n");
log("http://www.clifford.at/intersynth/\n");
log("http://bygone.clairexen.net/intersynth/\n");
log("\n");
}
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override

44
backends/json/json.cc
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -135,6 +135,10 @@ struct JsonWriter
// reserve 0 and 1 to avoid confusion with "0" and "1"
sigidcounter = 2;
if (module->has_processes()) {
log_error("Module %s contains processes, which are not supported by JSON backend (run `proc` first).\n", log_id(module));
}
f << stringf(" %s: {\n", get_name(module->name).c_str());
f << stringf(" \"attributes\": {");
@ -216,6 +220,27 @@ struct JsonWriter
}
f << stringf("\n },\n");
if (!module->memories.empty()) {
f << stringf(" \"memories\": {");
first = true;
for (auto &it : module->memories) {
if (use_selection && !module->selected(it.second))
continue;
f << stringf("%s\n", first ? "" : ",");
f << stringf(" %s: {\n", get_name(it.second->name).c_str());
f << stringf(" \"hide_name\": %s,\n", it.second->name[0] == '$' ? "1" : "0");
f << stringf(" \"attributes\": {");
write_parameters(it.second->attributes);
f << stringf("\n },\n");
f << stringf(" \"width\": %d,\n", it.second->width);
f << stringf(" \"start_offset\": %d,\n", it.second->start_offset);
f << stringf(" \"size\": %d\n", it.second->size);
f << stringf(" }");
first = false;
}
f << stringf("\n },\n");
}
f << stringf(" \"netnames\": {");
first = true;
for (auto w : module->wires()) {
@ -332,6 +357,10 @@ struct JsonBackend : public Backend {
log(" <cell_name>: <cell_details>,\n");
log(" ...\n");
log(" },\n");
log(" \"memories\": {\n");
log(" <memory_name>: <memory_details>,\n");
log(" ...\n");
log(" },\n");
log(" \"netnames\": {\n");
log(" <net_name>: <net_details>,\n");
log(" ...\n");
@ -379,6 +408,19 @@ struct JsonBackend : public Backend {
log(" },\n");
log(" }\n");
log("\n");
log("And <memory_details> is:\n");
log("\n");
log(" {\n");
log(" \"hide_name\": <1 | 0>,\n");
log(" \"attributes\": {\n");
log(" <attribute_name>: <attribute_value>,\n");
log(" ...\n");
log(" },\n");
log(" \"width\": <memory width>\n");
log(" \"start_offset\": <the lowest valid memory address>\n");
log(" \"size\": <memory size>\n");
log(" }\n");
log("\n");
log("And <net_details> is:\n");
log("\n");
log(" {\n");

2
backends/protobuf/Makefile.inc
View File

@ -3,6 +3,8 @@ ifeq ($(ENABLE_PROTOBUF),1)
backends/protobuf/yosys.pb.cc backends/protobuf/yosys.pb.h: misc/yosys.proto
$(Q) cd misc && protoc --cpp_out "../backends/protobuf" yosys.proto
backends/protobuf/protobuf.cc: backends/protobuf/yosys.pb.h
OBJS += backends/protobuf/protobuf.o backends/protobuf/yosys.pb.o
endif

2
backends/protobuf/protobuf.cc
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
* Copyright (C) 2018 Serge Bazanski <q3k@symbioticeda.com>
*
* Permission to use, copy, modify, and/or distribute this software for any

51
backends/rtlil/rtlil_backend.cc
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -51,15 +51,19 @@ void RTLIL_BACKEND::dump_const(std::ostream &f, const RTLIL::Const &data, int wi
}
}
f << stringf("%d'", width);
for (int i = offset+width-1; i >= offset; i--) {
log_assert(i < (int)data.bits.size());
switch (data.bits[i]) {
case State::S0: f << stringf("0"); break;
case State::S1: f << stringf("1"); break;
case RTLIL::Sx: f << stringf("x"); break;
case RTLIL::Sz: f << stringf("z"); break;
case RTLIL::Sa: f << stringf("-"); break;
case RTLIL::Sm: f << stringf("m"); break;
if (data.is_fully_undef()) {
f << "x";
} else {
for (int i = offset+width-1; i >= offset; i--) {
log_assert(i < (int)data.bits.size());
switch (data.bits[i]) {
case State::S0: f << stringf("0"); break;
case State::S1: f << stringf("1"); break;
case RTLIL::Sx: f << stringf("x"); break;
case RTLIL::Sz: f << stringf("z"); break;
case RTLIL::Sa: f << stringf("-"); break;
case RTLIL::Sm: f << stringf("m"); break;
}
}
}
} else {
@ -242,11 +246,28 @@ void RTLIL_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RT
case RTLIL::STi: f << stringf("init\n"); break;
}
for (auto it = sy->actions.begin(); it != sy->actions.end(); ++it) {
for (auto &it: sy->actions) {
f << stringf("%s update ", indent.c_str());
dump_sigspec(f, it->first);
dump_sigspec(f, it.first);
f << stringf(" ");
dump_sigspec(f, it->second);
dump_sigspec(f, it.second);
f << stringf("\n");
}
for (auto &it: sy->mem_write_actions) {
for (auto it2 = it.attributes.begin(); it2 != it.attributes.end(); ++it2) {
f << stringf("%s attribute %s ", indent.c_str(), it2->first.c_str());
dump_const(f, it2->second);
f << stringf("\n");
}
f << stringf("%s memwr %s ", indent.c_str(), it.memid.c_str());
dump_sigspec(f, it.address);
f << stringf(" ");
dump_sigspec(f, it.data);
f << stringf(" ");
dump_sigspec(f, it.enable);
f << stringf(" ");
dump_const(f, it.priority_mask);
f << stringf("\n");
}
}
@ -337,8 +358,8 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu
bool first_conn_line = true;
for (auto it = module->connections().begin(); it != module->connections().end(); ++it) {
bool show_conn = !only_selected;
if (only_selected) {
bool show_conn = !only_selected || design->selected_whole_module(module->name);
if (!show_conn) {
RTLIL::SigSpec sigs = it->first;
sigs.append(it->second);
for (auto &c : sigs.chunks()) {

2
backends/rtlil/rtlil_backend.h
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

2
backends/simplec/simplec.cc
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

14
backends/smt2/smt2.cc
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -124,6 +124,7 @@ struct Smt2Worker
memories = Mem::get_all_memories(module);
for (auto &mem : memories)
{
mem.narrow();
mem_dict[mem.memid] = &mem;
for (auto &port : mem.wr_ports)
{
@ -182,7 +183,7 @@ struct Smt2Worker
continue;
// Handled above.
if (cell->type.in(ID($mem), ID($memrd), ID($memwr), ID($meminit))) {
if (cell->is_mem_cell()) {
mem_cells[cell] = mem_dict[cell->parameters.at(ID::MEMID).decode_string()];
continue;
}
@ -694,7 +695,7 @@ struct Smt2Worker
// FIXME: $slice $concat
}
if (memmode && cell->type.in(ID($mem), ID($memrd), ID($memwr), ID($meminit)))
if (memmode && cell->is_mem_cell())
{
Mem *mem = mem_cells[cell];
@ -859,7 +860,7 @@ struct Smt2Worker
log_error("Unsupported cell type %s for cell %s.%s -- please run `dffunmap` before `write_smt2`.\n",
log_id(cell->type), log_id(module), log_id(cell));
}
if (cell->type.in(ID($adff), ID($adffe), ID($dffsr), ID($dffsre)) || cell->type.str().substr(0, 5) == "$_DFF") {
if (cell->type.in(ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($dffsr), ID($dffsre)) || cell->type.str().substr(0, 5) == "$_DFF" || cell->type.str().substr(0, 7) == "$_ALDFF") {
log_error("Unsupported cell type %s for cell %s.%s -- please run `async2sync; dffunmap` or `clk2fflogic` before `write_smt2`.\n",
log_id(cell->type), log_id(module), log_id(cell));
}
@ -1530,6 +1531,11 @@ struct Smt2Backend : public Backend {
log_header(design, "Executing SMT2 backend.\n");
log_push();
Pass::call(design, "bmuxmap");
Pass::call(design, "demuxmap");
log_pop();
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{

10
backends/smt2/smtbmc.py
View File

@ -2,7 +2,7 @@
#
# yosys -- Yosys Open SYnthesis Suite
#
# Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
# Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
@ -771,12 +771,12 @@ def write_vcd_trace(steps_start, steps_stop, index):
if gotread:
buf = data[:]
for i in reversed(range(len(tdata))):
for ii in reversed(range(len(tdata))):
for k in range(width):
if tdata[i][k] == "x":
tdata[i][k] = buf[k]
if tdata[ii][k] == "x":
tdata[ii][k] = buf[k]
else:
buf[k] = tdata[i][k]
buf[k] = tdata[ii][k]
if not asyncwr:
tdata.append(data[:])

12
backends/smt2/smtio.py
View File

@ -1,7 +1,7 @@
#
# yosys -- Yosys Open SYnthesis Suite
#
# Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
# Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
@ -203,14 +203,14 @@ class SmtIo:
print('timeout option is not supported for mathsat.')
sys.exit(1)
if self.solver == "boolector":
if self.solver in ["boolector", "bitwuzla"]:
if self.noincr:
self.popen_vargs = ['boolector', '--smt2'] + self.solver_opts
self.popen_vargs = [self.solver, '--smt2'] + self.solver_opts
else:
self.popen_vargs = ['boolector', '--smt2', '-i'] + self.solver_opts
self.popen_vargs = [self.solver, '--smt2', '-i'] + self.solver_opts
self.unroll = True
if self.timeout != 0:
print('timeout option is not supported for boolector.')
print('timeout option is not supported for %s.' % self.solver)
sys.exit(1)
if self.solver == "abc":
@ -1010,7 +1010,7 @@ class SmtOpts:
def helpmsg(self):
return """
-s <solver>
set SMT solver: z3, yices, boolector, cvc4, mathsat, dummy
set SMT solver: z3, yices, boolector, bitwuzla, cvc4, mathsat, dummy
default: yices
-S <opt>

9
backends/smv/smv.cc
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -578,7 +578,7 @@ struct SmvWorker
log_error("Unsupported cell type %s for cell %s.%s -- please run `dffunmap` before `write_smv`.\n",
log_id(cell->type), log_id(module), log_id(cell));
}
if (cell->type.in(ID($adff), ID($adffe), ID($dffsr), ID($dffsre)) || cell->type.str().substr(0, 5) == "$_DFF") {
if (cell->type.in(ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($dffsr), ID($dffsre)) || cell->type.str().substr(0, 5) == "$_DFF" || cell->type.str().substr(0, 7) == "$_ALDFF") {
log_error("Unsupported cell type %s for cell %s.%s -- please run `async2sync; dffunmap` or `clk2fflogic` before `write_smv`.\n",
log_id(cell->type), log_id(module), log_id(cell));
}
@ -741,6 +741,11 @@ struct SmvBackend : public Backend {
log_header(design, "Executing SMV backend.\n");
log_push();
Pass::call(design, "bmuxmap");
Pass::call(design, "demuxmap");
log_pop();
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{

2
backends/spice/spice.cc
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

2
backends/table/table.cc
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

518
backends/verilog/verilog_backend.cc
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -44,6 +44,7 @@ std::string auto_prefix, extmem_prefix;
RTLIL::Module *active_module;
dict<RTLIL::SigBit, RTLIL::State> active_initdata;
SigMap active_sigmap;
IdString initial_id;
void reset_auto_counter_id(RTLIL::IdString id, bool may_rename)
{
@ -357,7 +358,8 @@ void dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool no_decima
void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig)
{
if (GetSize(sig) == 0) {
f << "\"\"";
// See IEEE 1364-2005 Clause 5.1.14.
f << "{0{1'b0}}";
return;
}
if (sig.is_chunk()) {
@ -430,7 +432,7 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
dump_const(f, wire->attributes.at(ID::init));
}
f << stringf(";\n");
} else if (!wire->port_input && !wire->port_output)
} else
f << stringf("%s" "wire%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
#endif
}
@ -504,9 +506,24 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem)
int start = init.addr.as_int();
for (int i=0; i<words; i++)
{
f << stringf("%s" " %s[%d] = ", indent.c_str(), mem_id.c_str(), i + start);
dump_const(f, init.data.extract(i*mem.width, mem.width));
f << stringf(";\n");
for (int j = 0; j < mem.width; j++)
{
if (init.en[j] != State::S1)
continue;
int start_j = j, width = 1;
while (j+1 < mem.width && init.en[j+1] == State::S1)
j++, width++;
if (width == mem.width) {
f << stringf("%s" " %s[%d] = ", indent.c_str(), mem_id.c_str(), i + start);
} else {
f << stringf("%s" " %s[%d][%d:%d] = ", indent.c_str(), mem_id.c_str(), i + start, j, start_j);
}
dump_const(f, init.data.extract(i*mem.width+start_j, width));
f << stringf(";\n");
}
}
}
f << stringf("%s" "end\n", indent.c_str());
@ -515,6 +532,8 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem)
// create a map : "edge clk" -> expressions within that clock domain
dict<std::string, std::vector<std::string>> clk_to_lof_body;
dict<std::string, std::string> clk_to_arst_cond;
dict<std::string, std::vector<std::string>> clk_to_arst_body;
clk_to_lof_body[""] = std::vector<std::string>();
std::string clk_domain_str;
// create a list of reg declarations
@ -529,10 +548,27 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem)
std::ostringstream os;
dump_sigspec(os, port.clk);
clk_domain_str = stringf("%sedge %s", port.clk_polarity ? "pos" : "neg", os.str().c_str());
if( clk_to_lof_body.count(clk_domain_str) == 0 )
clk_to_lof_body[clk_domain_str] = std::vector<std::string>();
if (port.arst != State::S0) {
std::ostringstream os2;
dump_sigspec(os2, port.arst);
clk_domain_str += stringf(", posedge %s", os2.str().c_str());
clk_to_arst_cond[clk_domain_str] = os2.str();
}
}
if (!port.transparent)
// Decide how to represent the transparency; same idea as Mem::extract_rdff.
bool trans_use_addr = true;
for (auto bit : port.transparency_mask)
if (!bit)
trans_use_addr = false;
if (GetSize(mem.wr_ports) == 0)
trans_use_addr = false;
if (port.en != State::S1 || port.srst != State::S0 || port.arst != State::S0 || !port.init_value.is_fully_undef())
trans_use_addr = false;
if (!trans_use_addr)
{
// for clocked read ports make something like:
// reg [..] temp_id;
@ -541,19 +577,148 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem)
// assign r_data = temp_id;
std::string temp_id = next_auto_id();
lof_reg_declarations.push_back( stringf("reg [%d:0] %s;\n", port.data.size() - 1, temp_id.c_str()) );
{
bool has_indent = false;
if (port.arst != State::S0) {
std::ostringstream os;
if (port.en != RTLIL::SigBit(true))
{
os << stringf("if (");
dump_sigspec(os, port.en);
os << stringf(") ");
os << stringf("%s <= ", temp_id.c_str());
dump_sigspec(os, port.arst_value);
os << ";\n";
clk_to_arst_body[clk_domain_str].push_back(os.str());
}
if (port.srst != State::S0 && !port.ce_over_srst) {
std::ostringstream os;
os << stringf("if (");
dump_sigspec(os, port.srst);
os << stringf(")\n");
clk_to_lof_body[clk_domain_str].push_back(os.str());
std::ostringstream os2;
os2 << stringf("%s" "%s <= ", indent.c_str(), temp_id.c_str());
dump_sigspec(os2, port.srst_value);
os2 << ";\n";
clk_to_lof_body[clk_domain_str].push_back(os2.str());
std::ostringstream os3;
if (port.en == State::S1) {
os3 << "else begin\n";
} else {
os3 << "else if (";
dump_sigspec(os3, port.en);
os3 << ") begin\n";
}
os << stringf("%s <= %s[", temp_id.c_str(), mem_id.c_str());
dump_sigspec(os, port.addr);
clk_to_lof_body[clk_domain_str].push_back(os3.str());
has_indent = true;
} else if (port.en != State::S1) {
std::ostringstream os;
os << stringf("if (");
dump_sigspec(os, port.en);
os << stringf(") begin\n");
clk_to_lof_body[clk_domain_str].push_back(os.str());
has_indent = true;
}
for (int sub = 0; sub < (1 << port.wide_log2); sub++)
{
SigSpec addr = port.sub_addr(sub);
std::ostringstream os;
if (has_indent)
os << indent;
os << temp_id;
if (port.wide_log2)
os << stringf("[%d:%d]", (sub + 1) * mem.width - 1, sub * mem.width);
os << stringf(" <= %s[", mem_id.c_str());
dump_sigspec(os, addr);
os << stringf("];\n");
clk_to_lof_body[clk_domain_str].push_back(os.str());
}
for (int i = 0; i < GetSize(mem.wr_ports); i++) {
auto &wport = mem.wr_ports[i];
if (!port.transparency_mask[i] && !port.collision_x_mask[i])
continue;
int min_wide_log2 = std::min(port.wide_log2, wport.wide_log2);
int max_wide_log2 = std::max(port.wide_log2, wport.wide_log2);
bool wide_write = wport.wide_log2 > port.wide_log2;
for (int sub = 0; sub < (1 << max_wide_log2); sub += (1 << min_wide_log2)) {
SigSpec raddr = port.addr;
SigSpec waddr = wport.addr;
if (wide_write)
waddr = wport.sub_addr(sub);
else
raddr = port.sub_addr(sub);
int pos = 0;
int ewidth = mem.width << min_wide_log2;
int wsub = wide_write ? sub : 0;
int rsub = wide_write ? 0 : sub;
while (pos < ewidth) {
int epos = pos;
while (epos < ewidth && wport.en[epos + wsub * mem.width] == wport.en[pos + wsub * mem.width])
epos++;
std::ostringstream os;
if (has_indent)
os << indent;
os << "if (";
dump_sigspec(os, wport.en[pos + wsub * mem.width]);
if (raddr != waddr) {
os << " && ";
dump_sigspec(os, raddr);
os << " == ";
dump_sigspec(os, waddr);
}
os << ")\n";
clk_to_lof_body[clk_domain_str].push_back(os.str());
std::ostringstream os2;
if (has_indent)
os2 << indent;
os2 << indent;
os2 << temp_id;
if (epos-pos != GetSize(port.data))
os2 << stringf("[%d:%d]", rsub * mem.width + epos-1, rsub * mem.width + pos);
os2 << " <= ";
if (port.transparency_mask[i])
dump_sigspec(os2, wport.data.extract(wsub * mem.width + pos, epos-pos));
else
dump_sigspec(os2, Const(State::Sx, epos - pos));
os2 << ";\n";
clk_to_lof_body[clk_domain_str].push_back(os2.str());
pos = epos;
}
}
}
if (port.srst != State::S0 && port.ce_over_srst)
{
std::ostringstream os;
if (has_indent)
os << indent;
os << stringf("if (");
dump_sigspec(os, port.srst);
os << stringf(")\n");
clk_to_lof_body[clk_domain_str].push_back(os.str());
std::ostringstream os2;
if (has_indent)
os2 << indent;
os2 << stringf("%s" "%s <= ", indent.c_str(), temp_id.c_str());
dump_sigspec(os2, port.srst_value);
os2 << ";\n";
clk_to_lof_body[clk_domain_str].push_back(os2.str());
}
if (has_indent)
clk_to_lof_body[clk_domain_str].push_back("end\n");
if (!port.init_value.is_fully_undef())
{
std::ostringstream os;
dump_sigspec(os, port.init_value);
std::string line = stringf("initial %s = %s;\n", temp_id.c_str(), os.str().c_str());
clk_to_lof_body[""].push_back(line);
}
{
std::ostringstream os;
dump_sigspec(os, port.data);
@ -569,73 +734,153 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem)
// temp_id <= r_addr;
// assign r_data = array_reg[temp_id];
std::string temp_id = next_auto_id();
lof_reg_declarations.push_back( stringf("reg [%d:0] %s;\n", port.addr.size() - 1, temp_id.c_str()) );
lof_reg_declarations.push_back( stringf("reg [%d:0] %s;\n", port.addr.size() - 1 - port.wide_log2, temp_id.c_str()) );
{
std::ostringstream os;
dump_sigspec(os, port.addr);
dump_sigspec(os, port.addr.extract_end(port.wide_log2));
std::string line = stringf("%s <= %s;\n", temp_id.c_str(), os.str().c_str());
clk_to_lof_body[clk_domain_str].push_back(line);
}
for (int sub = 0; sub < (1 << port.wide_log2); sub++)
{
std::ostringstream os;
dump_sigspec(os, port.data);
std::string line = stringf("assign %s = %s[%s];\n", os.str().c_str(), mem_id.c_str(), temp_id.c_str());
clk_to_lof_body[""].push_back(line);
os << "assign ";
dump_sigspec(os, port.data.extract(sub * mem.width, mem.width));
os << stringf(" = %s[", mem_id.c_str());;
if (port.wide_log2) {
Const addr_lo;
for (int i = 0; i < port.wide_log2; i++)
addr_lo.bits.push_back(State(sub >> i & 1));
os << "{";
os << temp_id;
os << ", ";
dump_const(os, addr_lo);
os << "}";
} else {
os << temp_id;
}
os << "];\n";
clk_to_lof_body[""].push_back(os.str());
}
}
} else {
// for non-clocked read-ports make something like:
// assign r_data = array_reg[r_addr];
std::ostringstream os, os2;
dump_sigspec(os, port.data);
dump_sigspec(os2, port.addr);
std::string line = stringf("assign %s = %s[%s];\n", os.str().c_str(), mem_id.c_str(), os2.str().c_str());
clk_to_lof_body[""].push_back(line);
for (int sub = 0; sub < (1 << port.wide_log2); sub++)
{
SigSpec addr = port.sub_addr(sub);
std::ostringstream os, os2;
dump_sigspec(os, port.data.extract(sub * mem.width, mem.width));
dump_sigspec(os2, addr);
std::string line = stringf("assign %s = %s[%s];\n", os.str().c_str(), mem_id.c_str(), os2.str().c_str());
clk_to_lof_body[""].push_back(line);
}
}
}
// write ports
for (auto &port : mem.wr_ports)
// Write ports. Those are messy because we try to preserve priority, as much as we can:
//
// 1. We split all ports into several disjoint processes.
// 2. If a port has priority over another port, the two ports need to share
// a process, so that priority can be reconstructed on the other end.
// 3. We want each process to be as small as possible, to avoid extra
// priorities inferred on the other end.
pool<int> wr_ports_done;
for (int ridx = 0; ridx < GetSize(mem.wr_ports); ridx++)
{
if (wr_ports_done.count(ridx))
continue;
auto &root = mem.wr_ports[ridx];
// Start from a root.
pool<int> wr_ports_now;
wr_ports_now.insert(ridx);
// Transitively fill list of ports in this process by following priority edges.
while (true)
{
std::ostringstream os;
dump_sigspec(os, port.clk);
clk_domain_str = stringf("%sedge %s", port.clk_polarity ? "pos" : "neg", os.str().c_str());
if( clk_to_lof_body.count(clk_domain_str) == 0 )
clk_to_lof_body[clk_domain_str] = std::vector<std::string>();
}
// make something like:
// always @(posedge clk)
// if (wr_en_bit) memid[w_addr][??] <= w_data[??];
// ...
for (int i = 0; i < GetSize(port.en); i++)
{
int start_i = i, width = 1;
SigBit wen_bit = port.en[i];
bool changed = false;
while (i+1 < GetSize(port.en) && active_sigmap(port.en[i+1]) == active_sigmap(wen_bit))
i++, width++;
if (wen_bit == State::S0)
continue;
std::ostringstream os;
if (wen_bit != State::S1)
for (int i = 0; i < GetSize(mem.wr_ports); i++)
for (int j = 0; j < i; j++)
if (mem.wr_ports[i].priority_mask[j])
{
os << stringf("if (");
dump_sigspec(os, wen_bit);
os << stringf(") ");
if (wr_ports_now.count(i) && !wr_ports_now.count(j)) {
wr_ports_now.insert(j);
changed = true;
}
if (!wr_ports_now.count(i) && wr_ports_now.count(j)) {
wr_ports_now.insert(i);
changed = true;
}
}
os << stringf("%s[", mem_id.c_str());
dump_sigspec(os, port.addr);
if (width == GetSize(port.en))
os << stringf("] <= ");
else
os << stringf("][%d:%d] <= ", i, start_i);
dump_sigspec(os, port.data.extract(start_i, width));
os << stringf(";\n");
clk_to_lof_body[clk_domain_str].push_back(os.str());
if (!changed)
break;
}
if (root.clk_enable) {
f << stringf("%s" "always%s @(%sedge ", indent.c_str(), systemverilog ? "_ff" : "", root.clk_polarity ? "pos" : "neg");
dump_sigspec(f, root.clk);
f << ") begin\n";
} else {
f << stringf("%s" "always%s begin\n", indent.c_str(), systemverilog ? "_latch" : " @*");
}
for (int pidx = 0; pidx < GetSize(mem.wr_ports); pidx++)
{
if (!wr_ports_now.count(pidx))
continue;
wr_ports_done.insert(pidx);
auto &port = mem.wr_ports[pidx];
log_assert(port.clk_enable == root.clk_enable);
if (port.clk_enable) {
log_assert(port.clk == root.clk);
log_assert(port.clk_polarity == root.clk_polarity);
}
// make something like:
// always @(posedge clk)
// if (wr_en_bit) memid[w_addr][??] <= w_data[??];
// ...
for (int sub = 0; sub < (1 << port.wide_log2); sub++)
{
SigSpec addr = port.sub_addr(sub);
for (int i = 0; i < mem.width; i++)
{
int start_i = i, width = 1;
SigBit wen_bit = port.en[sub * mem.width + i];
while (i+1 < mem.width && active_sigmap(port.en[sub * mem.width + i+1]) == active_sigmap(wen_bit))
i++, width++;
if (wen_bit == State::S0)
continue;
f << stringf("%s%s", indent.c_str(), indent.c_str());
if (wen_bit != State::S1)
{
f << stringf("if (");
dump_sigspec(f, wen_bit);
f << stringf(")\n");
f << stringf("%s%s%s", indent.c_str(), indent.c_str(), indent.c_str());
}
f << stringf("%s[", mem_id.c_str());
dump_sigspec(f, addr);
if (width == GetSize(port.en))
f << stringf("] <= ");
else
f << stringf("][%d:%d] <= ", i, start_i);
dump_sigspec(f, port.data.extract(sub * mem.width + start_i, width));
f << stringf(";\n");
}
}
}
f << stringf("%s" "end\n", indent.c_str());
}
// Output Verilog that looks something like this:
// reg [..] _3_;
@ -668,8 +913,19 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem)
if( clk_domain != "")
{
f << stringf("%s" "always%s @(%s) begin\n", indent.c_str(), systemverilog ? "_ff" : "", clk_domain.c_str());
for(auto &line : lof_lines)
f << stringf("%s%s" "%s", indent.c_str(), indent.c_str(), line.c_str());
bool has_arst = clk_to_arst_cond.count(clk_domain) != 0;
if (has_arst) {
f << stringf("%s%s" "if (%s) begin\n", indent.c_str(), indent.c_str(), clk_to_arst_cond[clk_domain].c_str());
for(auto &line : clk_to_arst_body[clk_domain])
f << stringf("%s%s%s" "%s", indent.c_str(), indent.c_str(), indent.c_str(), line.c_str());
f << stringf("%s%s" "end else begin\n", indent.c_str(), indent.c_str());
for(auto &line : lof_lines)
f << stringf("%s%s%s" "%s", indent.c_str(), indent.c_str(), indent.c_str(), line.c_str());
f << stringf("%s%s" "end\n", indent.c_str(), indent.c_str());
} else {
for(auto &line : lof_lines)
f << stringf("%s%s" "%s", indent.c_str(), indent.c_str(), line.c_str());
}
f << stringf("%s" "end\n", indent.c_str());
}
else
@ -1144,7 +1400,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
FfData ff(nullptr, cell);
// $ff / $_FF_ cell: not supported.
if (ff.has_d && !ff.has_clk && !ff.has_en)
if (ff.has_gclk)
return false;
std::string reg_name = cellname(cell);
@ -1165,17 +1421,19 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
for (int i = 0; i < chunks; i++)
{
SigSpec sig_d;
SigSpec sig_d, sig_ad;
Const val_arst, val_srst;
std::string reg_bit_name, sig_set_name, sig_clr_name, sig_arst_name;
std::string reg_bit_name, sig_set_name, sig_clr_name, sig_arst_name, sig_aload_name;
if (chunky) {
reg_bit_name = stringf("%s[%d]", reg_name.c_str(), i);
if (ff.has_d)
if (ff.has_gclk || ff.has_clk)
sig_d = ff.sig_d[i];
if (ff.has_aload)
sig_ad = ff.sig_ad[i];
} else {
reg_bit_name = reg_name;
if (ff.has_d)
sig_d = ff.sig_d;
sig_d = ff.sig_d;
sig_ad = ff.sig_ad;
}
if (ff.has_arst)
val_arst = chunky ? ff.val_arst[i] : ff.val_arst;
@ -1183,28 +1441,38 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
val_srst = chunky ? ff.val_srst[i] : ff.val_srst;
// If there are constants in the sensitivity list, replace them with an intermediate wire
if (ff.has_sr) {
if (ff.sig_set[i].wire == NULL)
{
sig_set_name = next_auto_id();
f << stringf("%s" "wire %s = ", indent.c_str(), sig_set_name.c_str());
dump_const(f, ff.sig_set[i].data);
f << stringf(";\n");
}
if (ff.sig_clr[i].wire == NULL)
{
sig_clr_name = next_auto_id();
f << stringf("%s" "wire %s = ", indent.c_str(), sig_clr_name.c_str());
dump_const(f, ff.sig_clr[i].data);
f << stringf(";\n");
}
} else if (ff.has_arst) {
if (ff.sig_arst[i].wire == NULL)
{
sig_arst_name = next_auto_id();
f << stringf("%s" "wire %s = ", indent.c_str(), sig_arst_name.c_str());
dump_const(f, ff.sig_arst[i].data);
f << stringf(";\n");
if (ff.has_clk) {
if (ff.has_sr) {
if (ff.sig_set[i].wire == NULL)
{
sig_set_name = next_auto_id();
f << stringf("%s" "wire %s = ", indent.c_str(), sig_set_name.c_str());
dump_const(f, ff.sig_set[i].data);
f << stringf(";\n");
}
if (ff.sig_clr[i].wire == NULL)
{
sig_clr_name = next_auto_id();
f << stringf("%s" "wire %s = ", indent.c_str(), sig_clr_name.c_str());
dump_const(f, ff.sig_clr[i].data);
f << stringf(";\n");
}
} else if (ff.has_arst) {
if (ff.sig_arst[0].wire == NULL)
{
sig_arst_name = next_auto_id();
f << stringf("%s" "wire %s = ", indent.c_str(), sig_arst_name.c_str());
dump_const(f, ff.sig_arst[0].data);
f << stringf(";\n");
}
} else if (ff.has_aload) {
if (ff.sig_aload[0].wire == NULL)
{
sig_aload_name = next_auto_id();
f << stringf("%s" "wire %s = ", indent.c_str(), sig_aload_name.c_str());
dump_const(f, ff.sig_aload[0].data);
f << stringf(";\n");
}
}
}
@ -1226,13 +1494,18 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
f << stringf("%s", sig_clr_name.c_str());
else
dump_sigspec(f, ff.sig_clr[i]);
} else if (ff.has_arst) {
f << stringf(", %sedge ", ff.pol_arst ? "pos" : "neg");
if (ff.sig_arst[i].wire == NULL)
if (ff.sig_arst[0].wire == NULL)
f << stringf("%s", sig_arst_name.c_str());
else
dump_sigspec(f, ff.sig_arst);
} else if (ff.has_aload) {
f << stringf(", %sedge ", ff.pol_aload ? "pos" : "neg");
if (ff.sig_aload[0].wire == NULL)
f << stringf("%s", sig_aload_name.c_str());
else
dump_sigspec(f, ff.sig_aload);
}
f << stringf(")\n");
@ -1253,7 +1526,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
f << stringf("%s" " else ", indent.c_str());
} else if (ff.has_arst) {
f << stringf("if (%s", ff.pol_arst ? "" : "!");
if (ff.sig_arst[i].wire == NULL)
if (ff.sig_arst[0].wire == NULL)
f << stringf("%s", sig_arst_name.c_str());
else
dump_sigspec(f, ff.sig_arst);
@ -1261,11 +1534,21 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
dump_sigspec(f, val_arst);
f << stringf(";\n");
f << stringf("%s" " else ", indent.c_str());
} else if (ff.has_aload) {
f << stringf("if (%s", ff.pol_aload ? "" : "!");
if (ff.sig_aload[0].wire == NULL)
f << stringf("%s", sig_aload_name.c_str());
else
dump_sigspec(f, ff.sig_aload);
f << stringf(") %s <= ", reg_bit_name.c_str());
dump_sigspec(f, sig_ad);
f << stringf(";\n");
f << stringf("%s" " else ", indent.c_str());
}
if (ff.has_srst && ff.has_en && ff.ce_over_srst) {
f << stringf("if (%s", ff.pol_en ? "" : "!");
dump_sigspec(f, ff.sig_en);
if (ff.has_srst && ff.has_ce && ff.ce_over_srst) {
f << stringf("if (%s", ff.pol_ce ? "" : "!");
dump_sigspec(f, ff.sig_ce);
f << stringf(")\n");
f << stringf("%s" " if (%s", indent.c_str(), ff.pol_srst ? "" : "!");
dump_sigspec(f, ff.sig_srst);
@ -1282,9 +1565,9 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
f << stringf(";\n");
f << stringf("%s" " else ", indent.c_str());
}
if (ff.has_en) {
f << stringf("if (%s", ff.pol_en ? "" : "!");
dump_sigspec(f, ff.sig_en);
if (ff.has_ce) {
f << stringf("if (%s", ff.pol_ce ? "" : "!");
dump_sigspec(f, ff.sig_ce);
f << stringf(") ");
}
}
@ -1306,7 +1589,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
f << stringf("%s" " else if (%s", indent.c_str(), ff.pol_set ? "" : "!");
dump_sigspec(f, ff.sig_set[i]);
f << stringf(") %s = 1'b1;\n", reg_bit_name.c_str());
if (ff.has_d)
if (ff.has_aload)
f << stringf("%s" " else ", indent.c_str());
} else if (ff.has_arst) {
f << stringf("if (%s", ff.pol_arst ? "" : "!");
@ -1314,14 +1597,14 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
f << stringf(") %s = ", reg_bit_name.c_str());
dump_sigspec(f, val_arst);
f << stringf(";\n");
if (ff.has_d)
if (ff.has_aload)
f << stringf("%s" " else ", indent.c_str());
}
if (ff.has_d) {
f << stringf("if (%s", ff.pol_en ? "" : "!");
dump_sigspec(f, ff.sig_en);
if (ff.has_aload) {
f << stringf("if (%s", ff.pol_aload ? "" : "!");
dump_sigspec(f, ff.sig_aload);
f << stringf(") %s = ", reg_bit_name.c_str());
dump_sigspec(f, sig_d);
dump_sigspec(f, sig_ad);
f << stringf(";\n");
}
}
@ -1464,7 +1747,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
{
// Handled by dump_memory
if (cell->type.in(ID($mem), ID($memwr), ID($memrd), ID($meminit)))
if (cell->is_mem_cell())
return;
if (cell->type[0] == '$' && !noexpr) {
@ -1662,7 +1945,7 @@ void dump_process(std::ostream &f, std::string indent, RTLIL::Process *proc, boo
f << stringf("%s" "always%s begin\n", indent.c_str(), systemverilog ? "_comb" : " @*");
if (!systemverilog)
f << indent + " " << "if (" << id("\\initial") << ") begin end\n";
f << indent + " " << "if (" << id(initial_id) << ") begin end\n";
dump_case_body(f, indent, &proc->root_case, true);
std::string backup_indent = indent;
@ -1781,6 +2064,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
dump_attributes(f, indent, module->attributes, '\n', /*modattr=*/true);
f << stringf("%s" "module %s(", indent.c_str(), id(module->name, false).c_str());
bool keep_running = true;
int cnt = 0;
for (int port_id = 1; keep_running; port_id++) {
keep_running = false;
for (auto wire : module->wires()) {
@ -1789,14 +2073,16 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
f << stringf(", ");
f << stringf("%s", id(wire->name).c_str());
keep_running = true;
if (cnt==20) { f << stringf("\n"); cnt = 0; } else cnt++;
continue;
}
}
}
f << stringf(");\n");
if (!systemverilog && !module->processes.empty())
f << indent + " " << "reg " << id("\\initial") << " = 0;\n";
if (!systemverilog && !module->processes.empty()) {
initial_id = NEW_ID;
f << indent + " " << "reg " << id(initial_id) << " = 0;\n";
}
for (auto w : module->wires())
dump_wire(f, indent + " ", w);
@ -2014,6 +2300,12 @@ struct VerilogBackend : public Backend {
extmem_prefix = filename.substr(0, filename.rfind('.'));
}
log_push();
Pass::call(design, "bmuxmap");
Pass::call(design, "demuxmap");
Pass::call(design, "clean_zerowidth");
log_pop();
design->sort();
*f << stringf("/* Generated by %s */\n", yosys_version_str);

6
examples/smtbmc/Makefile
View File

@ -1,5 +1,5 @@
all: demo1 demo2 demo3 demo4 demo5 demo6 demo7 demo8 demo9
all: demo1 demo2 demo3 demo4 demo5 demo6 demo7 demo8 demo9 glift_mux
demo1: demo1.smt2
yosys-smtbmc --dump-vcd demo1.vcd demo1.smt2
@ -31,6 +31,9 @@ demo8: demo8.smt2
demo9: demo9.smt2
yosys-smtbmc -s z3 -t 1 -g demo9.smt2
glift_mux:
yosys -ql glift_mux.yslog glift/mux2.ys
demo1.smt2: demo1.v
yosys -ql demo1.yslog -p 'read_verilog -formal demo1.v; prep -top demo1 -nordff; write_smt2 -wires demo1.smt2'
@ -68,6 +71,7 @@ clean:
rm -f demo7.yslog demo7.smt2
rm -f demo8.yslog demo8.smt2
rm -f demo9.yslog demo9.smt2
rm -f glift_mux.ys
.PHONY: demo1 demo2 demo3 demo4 demo5 demo6 demo7 demo8 demo9 clean

4194
examples/smtbmc/glift/C7552.v Executable file
View File

File diff suppressed because it is too large Load Diff

41
examples/smtbmc/glift/C7552.ys Normal file
View File

@ -0,0 +1,41 @@
read_verilog C7552.v
techmap
flatten
select C7552_lev2
glift -create-instrumented-model
techmap
opt
rename C7552_lev2 uut
cd ..
delete [AIONX][NVXR]2
read_verilog C7552.v
techmap
flatten
select C7552_lev2
glift -create-precise-model
techmap
opt
rename C7552_lev2 spec
cd ..
delete [AIONX][NVXR]2
design -push-copy
miter -equiv spec uut miter
flatten
delete uut spec
techmap
opt
stat miter
qbfsat -O2 -write-solution C7552.soln -solver yices -timeout 3600 -nocleanup -assume-outputs -assume-negative-polarity miter
design -pop
stat
copy uut solved
qbfsat -specialize-from-file C7552.soln solved
opt solved
miter -equiv spec solved satmiter
flatten
sat -prove trigger 0 satmiter
delete satmiter
stat
shell

451
examples/smtbmc/glift/C880.v Executable file
View File

@ -0,0 +1,451 @@
module C880_lev2(pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09,
pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19,
pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29,
pi30, pi31, pi32, pi33, pi34, pi35, pi36, pi37, pi38, pi39,
pi40, pi41, pi42, pi43, pi44, pi45, pi46, pi47, pi48, pi49,
pi50, pi51, pi52, pi53, pi54, pi55, pi56, pi57, pi58, pi59,
po00, po01, po02, po03, po04, po05, po06, po07, po08, po09,
po10, po11, po12, po13, po14, po15, po16, po17, po18, po19,
po20, po21, po22, po23, po24, po25);
input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09,
pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19,
pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29,
pi30, pi31, pi32, pi33, pi34, pi35, pi36, pi37, pi38, pi39,
pi40, pi41, pi42, pi43, pi44, pi45, pi46, pi47, pi48, pi49,
pi50, pi51, pi52, pi53, pi54, pi55, pi56, pi57, pi58, pi59;
output po00, po01, po02, po03, po04, po05, po06, po07, po08, po09,
po10, po11, po12, po13, po14, po15, po16, po17, po18, po19,
po20, po21, po22, po23, po24, po25;
wire n137, n346, n364, n415, n295, n427, n351, n377, n454, n357,
n358, n359, n360, n361, n362, n363, n365, n366, n367, n368,
n369, n370, n371, n372, n373, n374, n375, n376, n378, n379,
n380, n381, n382, n383, n384, n385, n386, n387, n388, n389,
n390, n391, n392, n393, n394, n395, n396, n397, n398, n399,
n400, n401, n402, n403, n404, n405, n406, n407, n408, n409,
n410, n411, n412, n413, n414, n416, n417, n418, n419, n420,
n421, n422, n423, n424, n425, n426, n428, n429, n430, n431,
n432, n433, n434, n435, n436, n437, n438, n439, n440, n441,
n442, n443, n444, n445, n446, n447, n448, n449, n450, n451,
n452, n453, n455, n456, n457, n458, n459, n460, n461, n462,
n463, n464, n465, n466, n467, n468, n469, n470, n471, n472,
n473, n474, n475, n476, n477, n478, n479, n480, n481, n482,
n483, n484, n485, n486, n487, n488, n489, n490, n491, n492,
n493, n494, n495, n496, n497, n498, n499, n500, n501, n502,
n503, n504, n505, n506, n507, n508, n509, n510, n511, n512,
n513, n514, n515, n516, n517, n518, n519, n520, n521, n522,
n523, n524, n525, n526, n527, n528, n529, n530, n531, n532,
n533, n534, n535, n536, n537, n538, n539, n540, n541, n542,
n543, n544, n545, n546, n547, n548, n549, n550, n551, n552,
n553, n554, n555, n556, n557, n558, n559, n560, n561, n562,
n563, n564, n565, n566, n567, n568, n569, n570, n571, n572,
n573, n574, n575, n576, n577, n578, n579, n580, n581, n582,
n583, n584, n585, n586, n587, n588, n589, n590, n591, n592,
n593, n594, n595, n596, n597, n598, n599, n600, n601, n602,
n603, n604, n605, n606, n607, n608, n609, n610, n611, n612,
n613, n614, n615, n616, n617, n618, n619, n620, n621, n622,
n623, n624, n625, n626, n627, n628, n629, n630, n631, n632,
n633, n634, n635, n636, n637, n638, n639, n640, n641, n642,
n643, n644, n645, n646, n647, n648, n649, n650, n651, n652,
n653, n654, n655, n656, n657, n658, n659, n660, n661, n662,
n663, n664, n665, n666, n667, n668, n669, n670, n671, n672,
n673, n674, n675, n676, n677, n678, n679, n680, n681, n682,
n683, n684, n685, n686, n687, n688, n689, n690, n691, n692,
n693, n694, n695, n696;
assign po22 = n137;
assign po19 = n346;
assign po16 = n364;
assign po17 = n415;
assign po18 = n295;
assign po00 = n427;
assign po09 = n351;
assign po04 = n377;
assign po06 = n454;
AN2 U371 ( .A(pi11), .B(pi08), .Z(n357));
AN2 U372 ( .A(pi28), .B(n357), .Z(n346));
AN2 U373 ( .A(pi41), .B(pi25), .Z(n369));
AN2 U374 ( .A(pi52), .B(n369), .Z(n361));
AN2 U375 ( .A(pi51), .B(pi54), .Z(n359));
AN2 U376 ( .A(pi28), .B(pi31), .Z(n604));
AN2 U377 ( .A(n604), .B(pi55), .Z(n358));
AN2 U378 ( .A(n359), .B(n358), .Z(n602));
AN2 U379 ( .A(pi53), .B(n602), .Z(n360));
AN2 U380 ( .A(n361), .B(n360), .Z(n577));
IV2 U381 ( .A(pi20), .Z(n607));
OR2 U382 ( .A(n607), .B(pi25), .Z(n362));
IV2 U383 ( .A(n362), .Z(n365));
AN2 U384 ( .A(pi25), .B(n607), .Z(n363));
OR2 U385 ( .A(n365), .B(n363), .Z(n367));
AN2 U386 ( .A(pi41), .B(pi24), .Z(n378));
AN2 U387 ( .A(n346), .B(n378), .Z(n366));
AN2 U388 ( .A(n367), .B(n366), .Z(n373));
AN2 U389 ( .A(pi28), .B(pi54), .Z(n368));
AN2 U390 ( .A(pi20), .B(n368), .Z(n603));
AN2 U391 ( .A(pi08), .B(n603), .Z(n371));
IV2 U392 ( .A(pi56), .Z(n694));
IV2 U393 ( .A(n369), .Z(n692));
OR2 U394 ( .A(n694), .B(n692), .Z(n370));
AN2 U395 ( .A(n371), .B(n370), .Z(n372));
OR2 U396 ( .A(n373), .B(n372), .Z(n424));
AN2 U397 ( .A(pi14), .B(n424), .Z(n384));
AN2 U398 ( .A(pi56), .B(pi48), .Z(n608));
AN2 U399 ( .A(n608), .B(n346), .Z(n374));
AN2 U400 ( .A(pi07), .B(n374), .Z(n376));
IV2 U401 ( .A(pi43), .Z(n375));
AN2 U402 ( .A(n376), .B(n375), .Z(n406));
AN2 U403 ( .A(pi20), .B(n406), .Z(n403));
IV2 U404 ( .A(n378), .Z(n379));
AN2 U405 ( .A(n346), .B(n379), .Z(n407));
AN2 U406 ( .A(pi55), .B(n407), .Z(n399));
AN2 U407 ( .A(pi44), .B(n399), .Z(n381));
AN2 U408 ( .A(pi37), .B(pi54), .Z(n380));
OR2 U409 ( .A(n381), .B(n380), .Z(n382));
OR2 U410 ( .A(n403), .B(n382), .Z(n383));
OR2 U411 ( .A(n384), .B(n383), .Z(n436));
AN2 U412 ( .A(pi26), .B(n436), .Z(n385));
OR2 U413 ( .A(n577), .B(n385), .Z(n386));
AN2 U414 ( .A(pi34), .B(n386), .Z(n448));
AN2 U415 ( .A(pi43), .B(pi05), .Z(n388));
AN2 U416 ( .A(pi32), .B(n436), .Z(n387));
OR2 U417 ( .A(n388), .B(n387), .Z(n446));
AN2 U418 ( .A(pi08), .B(pi37), .Z(n393));
AN2 U419 ( .A(pi50), .B(n399), .Z(n390));
AN2 U420 ( .A(pi18), .B(n424), .Z(n389));
OR2 U421 ( .A(n390), .B(n389), .Z(n391));
OR2 U422 ( .A(n403), .B(n391), .Z(n392));
OR2 U423 ( .A(n393), .B(n392), .Z(n494));
AN2 U424 ( .A(pi27), .B(n494), .Z(n497));
OR2 U425 ( .A(pi27), .B(n494), .Z(n499));
AN2 U426 ( .A(pi20), .B(pi37), .Z(n398));
AN2 U427 ( .A(pi45), .B(n399), .Z(n395));
AN2 U428 ( .A(pi22), .B(n424), .Z(n394));
OR2 U429 ( .A(n395), .B(n394), .Z(n396));
OR2 U430 ( .A(n403), .B(n396), .Z(n397));
OR2 U431 ( .A(n398), .B(n397), .Z(n536));
AN2 U432 ( .A(pi17), .B(n536), .Z(n539));
OR2 U433 ( .A(pi17), .B(n536), .Z(n541));
AN2 U434 ( .A(pi23), .B(n424), .Z(n405));
AN2 U435 ( .A(pi30), .B(pi37), .Z(n401));
AN2 U436 ( .A(pi29), .B(n399), .Z(n400));
OR2 U437 ( .A(n401), .B(n400), .Z(n402));
OR2 U438 ( .A(n403), .B(n402), .Z(n404));
OR2 U439 ( .A(n405), .B(n404), .Z(n579));
AN2 U440 ( .A(pi21), .B(n579), .Z(n582));
OR2 U441 ( .A(pi21), .B(n579), .Z(n584));
AN2 U442 ( .A(n406), .B(pi55), .Z(n429));
IV2 U443 ( .A(pi28), .Z(n409));
AN2 U444 ( .A(n407), .B(pi20), .Z(n408));
OR2 U445 ( .A(n409), .B(n408), .Z(n423));
AN2 U446 ( .A(pi50), .B(n423), .Z(n411));
AN2 U447 ( .A(pi42), .B(n424), .Z(n410));
OR2 U448 ( .A(n411), .B(n410), .Z(n412));
OR2 U449 ( .A(n429), .B(n412), .Z(n514));
AN2 U450 ( .A(pi15), .B(n514), .Z(n517));
OR2 U451 ( .A(pi15), .B(n514), .Z(n519));
AN2 U452 ( .A(pi45), .B(n423), .Z(n414));
AN2 U453 ( .A(pi40), .B(n424), .Z(n413));
OR2 U454 ( .A(n414), .B(n413), .Z(n416));
OR2 U455 ( .A(n429), .B(n416), .Z(n556));
AN2 U456 ( .A(pi03), .B(n556), .Z(n559));
OR2 U457 ( .A(pi03), .B(n556), .Z(n561));
AN2 U458 ( .A(pi29), .B(n423), .Z(n418));
AN2 U459 ( .A(pi04), .B(n424), .Z(n417));
OR2 U460 ( .A(n418), .B(n417), .Z(n419));
OR2 U461 ( .A(n429), .B(n419), .Z(n471));
AN2 U462 ( .A(pi10), .B(n471), .Z(n480));
OR2 U463 ( .A(pi10), .B(n471), .Z(n482));
AN2 U464 ( .A(pi46), .B(n482), .Z(n420));
OR2 U465 ( .A(n480), .B(n420), .Z(n562));
AN2 U466 ( .A(n561), .B(n562), .Z(n421));
OR2 U467 ( .A(n559), .B(n421), .Z(n520));
AN2 U468 ( .A(n519), .B(n520), .Z(n422));
OR2 U469 ( .A(n517), .B(n422), .Z(n449));
AN2 U470 ( .A(pi44), .B(n423), .Z(n426));
AN2 U471 ( .A(pi49), .B(n424), .Z(n425));
OR2 U472 ( .A(n426), .B(n425), .Z(n428));
OR2 U473 ( .A(n429), .B(n428), .Z(n464));
AN2 U474 ( .A(n449), .B(n464), .Z(n432));
OR2 U475 ( .A(n449), .B(n464), .Z(n430));
AN2 U476 ( .A(pi09), .B(n430), .Z(n431));
OR2 U477 ( .A(n432), .B(n431), .Z(n585));
AN2 U478 ( .A(n584), .B(n585), .Z(n433));
OR2 U479 ( .A(n582), .B(n433), .Z(n542));
AN2 U480 ( .A(n541), .B(n542), .Z(n434));
OR2 U481 ( .A(n539), .B(n434), .Z(n500));
AN2 U482 ( .A(n499), .B(n500), .Z(n435));
OR2 U483 ( .A(n497), .B(n435), .Z(n597));
OR2 U484 ( .A(pi34), .B(n436), .Z(n598));
AN2 U485 ( .A(n436), .B(pi34), .Z(n600));
IV2 U486 ( .A(n600), .Z(n437));
AN2 U487 ( .A(n598), .B(n437), .Z(n442));
OR2 U488 ( .A(n597), .B(n442), .Z(n440));
AN2 U489 ( .A(n597), .B(n442), .Z(n438));
IV2 U490 ( .A(n438), .Z(n439));
AN2 U491 ( .A(n440), .B(n439), .Z(n441));
AN2 U492 ( .A(pi12), .B(n441), .Z(n444));
AN2 U493 ( .A(n442), .B(pi19), .Z(n443));
OR2 U494 ( .A(n444), .B(n443), .Z(n445));
OR2 U495 ( .A(n446), .B(n445), .Z(n447));
OR2 U496 ( .A(n448), .B(n447), .Z(n137));
IV2 U497 ( .A(n464), .Z(n459));
AN2 U498 ( .A(pi12), .B(n449), .Z(n456));
AN2 U499 ( .A(n459), .B(n456), .Z(n453));
IV2 U500 ( .A(n449), .Z(n450));
AN2 U501 ( .A(n450), .B(pi12), .Z(n451));
OR2 U502 ( .A(pi19), .B(n451), .Z(n458));
AN2 U503 ( .A(n464), .B(n458), .Z(n452));
OR2 U504 ( .A(n453), .B(n452), .Z(n455));
IV2 U505 ( .A(pi09), .Z(n612));
AN2 U506 ( .A(n455), .B(n612), .Z(n470));
OR2 U507 ( .A(pi26), .B(n456), .Z(n457));
AN2 U508 ( .A(n464), .B(n457), .Z(n462));
AN2 U509 ( .A(n459), .B(n458), .Z(n460));
OR2 U510 ( .A(n577), .B(n460), .Z(n461));
OR2 U511 ( .A(n462), .B(n461), .Z(n463));
AN2 U512 ( .A(pi09), .B(n463), .Z(n468));
AN2 U513 ( .A(pi23), .B(pi05), .Z(n466));
AN2 U514 ( .A(pi32), .B(n464), .Z(n465));
OR2 U515 ( .A(n466), .B(n465), .Z(n467));
OR2 U516 ( .A(n468), .B(n467), .Z(n469));
OR2 U517 ( .A(n470), .B(n469), .Z(n295));
AN2 U518 ( .A(pi26), .B(n480), .Z(n479));
AN2 U519 ( .A(pi40), .B(pi05), .Z(n473));
AN2 U520 ( .A(pi32), .B(n471), .Z(n472));
OR2 U521 ( .A(n473), .B(n472), .Z(n477));
AN2 U522 ( .A(pi38), .B(pi36), .Z(n475));
AN2 U523 ( .A(pi10), .B(n577), .Z(n474));
OR2 U524 ( .A(n475), .B(n474), .Z(n476));
OR2 U525 ( .A(n477), .B(n476), .Z(n478));
OR2 U526 ( .A(n479), .B(n478), .Z(n491));
IV2 U527 ( .A(n480), .Z(n481));
AN2 U528 ( .A(n482), .B(n481), .Z(n487));
OR2 U529 ( .A(pi46), .B(n487), .Z(n485));
AN2 U530 ( .A(pi46), .B(n487), .Z(n483));
IV2 U531 ( .A(n483), .Z(n484));
AN2 U532 ( .A(n485), .B(n484), .Z(n486));
AN2 U533 ( .A(pi12), .B(n486), .Z(n489));
AN2 U534 ( .A(n487), .B(pi19), .Z(n488));
OR2 U535 ( .A(n489), .B(n488), .Z(n490));
OR2 U536 ( .A(n491), .B(n490), .Z(n351));
AN2 U537 ( .A(pi26), .B(n494), .Z(n492));
OR2 U538 ( .A(n577), .B(n492), .Z(n493));
AN2 U539 ( .A(pi27), .B(n493), .Z(n511));
AN2 U540 ( .A(pi14), .B(pi05), .Z(n496));
AN2 U541 ( .A(pi32), .B(n494), .Z(n495));
OR2 U542 ( .A(n496), .B(n495), .Z(n509));
IV2 U543 ( .A(n497), .Z(n498));
AN2 U544 ( .A(n499), .B(n498), .Z(n505));
OR2 U545 ( .A(n500), .B(n505), .Z(n503));
AN2 U546 ( .A(n500), .B(n505), .Z(n501));
IV2 U547 ( .A(n501), .Z(n502));
AN2 U548 ( .A(n503), .B(n502), .Z(n504));
AN2 U549 ( .A(pi12), .B(n504), .Z(n507));
AN2 U550 ( .A(n505), .B(pi19), .Z(n506));
OR2 U551 ( .A(n507), .B(n506), .Z(n508));
OR2 U552 ( .A(n509), .B(n508), .Z(n510));
OR2 U553 ( .A(n511), .B(n510), .Z(n364));
AN2 U554 ( .A(pi26), .B(n514), .Z(n512));
OR2 U555 ( .A(n577), .B(n512), .Z(n513));
AN2 U556 ( .A(pi15), .B(n513), .Z(n533));
AN2 U557 ( .A(pi49), .B(pi05), .Z(n531));
AN2 U558 ( .A(pi33), .B(pi36), .Z(n516));
AN2 U559 ( .A(pi32), .B(n514), .Z(n515));
OR2 U560 ( .A(n516), .B(n515), .Z(n529));
IV2 U561 ( .A(n517), .Z(n518));
AN2 U562 ( .A(n519), .B(n518), .Z(n525));
OR2 U563 ( .A(n520), .B(n525), .Z(n523));
AN2 U564 ( .A(n520), .B(n525), .Z(n521));
IV2 U565 ( .A(n521), .Z(n522));
AN2 U566 ( .A(n523), .B(n522), .Z(n524));
AN2 U567 ( .A(pi12), .B(n524), .Z(n527));
AN2 U568 ( .A(n525), .B(pi19), .Z(n526));
OR2 U569 ( .A(n527), .B(n526), .Z(n528));
OR2 U570 ( .A(n529), .B(n528), .Z(n530));
OR2 U571 ( .A(n531), .B(n530), .Z(n532));
OR2 U572 ( .A(n533), .B(n532), .Z(n377));
AN2 U573 ( .A(pi26), .B(n536), .Z(n534));
OR2 U574 ( .A(n577), .B(n534), .Z(n535));
AN2 U575 ( .A(pi17), .B(n535), .Z(n553));
AN2 U576 ( .A(pi18), .B(pi05), .Z(n538));
AN2 U577 ( .A(pi32), .B(n536), .Z(n537));
OR2 U578 ( .A(n538), .B(n537), .Z(n551));
IV2 U579 ( .A(n539), .Z(n540));
AN2 U580 ( .A(n541), .B(n540), .Z(n547));
OR2 U581 ( .A(n542), .B(n547), .Z(n545));
AN2 U582 ( .A(n542), .B(n547), .Z(n543));
IV2 U583 ( .A(n543), .Z(n544));
AN2 U584 ( .A(n545), .B(n544), .Z(n546));
AN2 U585 ( .A(pi12), .B(n546), .Z(n549));
AN2 U586 ( .A(n547), .B(pi19), .Z(n548));
OR2 U587 ( .A(n549), .B(n548), .Z(n550));
OR2 U588 ( .A(n551), .B(n550), .Z(n552));
OR2 U589 ( .A(n553), .B(n552), .Z(n415));
AN2 U590 ( .A(pi26), .B(n556), .Z(n554));
OR2 U591 ( .A(n577), .B(n554), .Z(n555));
AN2 U592 ( .A(pi03), .B(n555), .Z(n575));
AN2 U593 ( .A(pi42), .B(pi05), .Z(n573));
AN2 U594 ( .A(pi47), .B(pi36), .Z(n558));
AN2 U595 ( .A(pi32), .B(n556), .Z(n557));
OR2 U596 ( .A(n558), .B(n557), .Z(n571));
IV2 U597 ( .A(n559), .Z(n560));
AN2 U598 ( .A(n561), .B(n560), .Z(n567));
OR2 U599 ( .A(n562), .B(n567), .Z(n565));
AN2 U600 ( .A(n562), .B(n567), .Z(n563));
IV2 U601 ( .A(n563), .Z(n564));
AN2 U602 ( .A(n565), .B(n564), .Z(n566));
AN2 U603 ( .A(pi12), .B(n566), .Z(n569));
AN2 U604 ( .A(n567), .B(pi19), .Z(n568));
OR2 U605 ( .A(n569), .B(n568), .Z(n570));
OR2 U606 ( .A(n571), .B(n570), .Z(n572));
OR2 U607 ( .A(n573), .B(n572), .Z(n574));
OR2 U608 ( .A(n575), .B(n574), .Z(n427));
AN2 U609 ( .A(pi26), .B(n579), .Z(n576));
OR2 U610 ( .A(n577), .B(n576), .Z(n578));
AN2 U611 ( .A(pi21), .B(n578), .Z(n596));
AN2 U612 ( .A(pi22), .B(pi05), .Z(n581));
AN2 U613 ( .A(pi32), .B(n579), .Z(n580));
OR2 U614 ( .A(n581), .B(n580), .Z(n594));
IV2 U615 ( .A(n582), .Z(n583));
AN2 U616 ( .A(n584), .B(n583), .Z(n590));
OR2 U617 ( .A(n585), .B(n590), .Z(n588));
AN2 U618 ( .A(n585), .B(n590), .Z(n586));
IV2 U619 ( .A(n586), .Z(n587));
AN2 U620 ( .A(n588), .B(n587), .Z(n589));
AN2 U621 ( .A(pi12), .B(n589), .Z(n592));
AN2 U622 ( .A(n590), .B(pi19), .Z(n591));
OR2 U623 ( .A(n592), .B(n591), .Z(n593));
OR2 U624 ( .A(n594), .B(n593), .Z(n595));
OR2 U625 ( .A(n596), .B(n595), .Z(n454));
AN2 U626 ( .A(n598), .B(n597), .Z(n599));
OR2 U627 ( .A(n600), .B(n599), .Z(po07));
OR2 U628 ( .A(pi58), .B(pi00), .Z(n609));
AN2 U629 ( .A(pi59), .B(n609), .Z(po24));
AN2 U630 ( .A(n602), .B(pi57), .Z(n601));
AN2 U631 ( .A(pi41), .B(n601), .Z(po13));
AN2 U632 ( .A(pi48), .B(n602), .Z(po08));
AN2 U633 ( .A(n603), .B(pi31), .Z(po03));
AN2 U634 ( .A(pi48), .B(pi16), .Z(n610));
AN2 U635 ( .A(pi25), .B(n610), .Z(po25));
AN2 U636 ( .A(pi11), .B(n604), .Z(n605));
IV2 U637 ( .A(n605), .Z(n606));
OR2 U638 ( .A(n607), .B(n606), .Z(n691));
OR2 U639 ( .A(po25), .B(n691), .Z(po02));
AN2 U640 ( .A(n608), .B(pi25), .Z(po10));
AN2 U641 ( .A(pi13), .B(n609), .Z(po12));
AN2 U642 ( .A(pi07), .B(n610), .Z(po14));
IV2 U643 ( .A(pi15), .Z(n611));
AN2 U644 ( .A(pi09), .B(n611), .Z(n614));
AN2 U645 ( .A(pi15), .B(n612), .Z(n613));
OR2 U646 ( .A(n614), .B(n613), .Z(n618));
IV2 U647 ( .A(pi35), .Z(n654));
OR2 U648 ( .A(n654), .B(pi06), .Z(n617));
IV2 U649 ( .A(pi06), .Z(n615));
OR2 U650 ( .A(n615), .B(pi35), .Z(n616));
AN2 U651 ( .A(n617), .B(n616), .Z(n619));
OR2 U652 ( .A(n618), .B(n619), .Z(n622));
AN2 U653 ( .A(n619), .B(n618), .Z(n620));
IV2 U654 ( .A(n620), .Z(n621));
AN2 U655 ( .A(n622), .B(n621), .Z(n628));
IV2 U656 ( .A(pi10), .Z(n624));
OR2 U657 ( .A(n624), .B(pi03), .Z(n623));
IV2 U658 ( .A(n623), .Z(n626));
AN2 U659 ( .A(pi03), .B(n624), .Z(n625));
OR2 U660 ( .A(n626), .B(n625), .Z(n627));
OR2 U661 ( .A(n628), .B(n627), .Z(n631));
AN2 U662 ( .A(n628), .B(n627), .Z(n629));
IV2 U663 ( .A(n629), .Z(n630));
AN2 U664 ( .A(n631), .B(n630), .Z(n637));
IV2 U665 ( .A(pi34), .Z(n632));
AN2 U666 ( .A(pi27), .B(n632), .Z(n635));
OR2 U667 ( .A(n632), .B(pi27), .Z(n633));
IV2 U668 ( .A(n633), .Z(n634));
OR2 U669 ( .A(n635), .B(n634), .Z(n636));
OR2 U670 ( .A(n637), .B(n636), .Z(n640));
AN2 U671 ( .A(n637), .B(n636), .Z(n638));
IV2 U672 ( .A(n638), .Z(n639));
AN2 U673 ( .A(n640), .B(n639), .Z(n647));
IV2 U674 ( .A(pi21), .Z(n642));
OR2 U675 ( .A(n642), .B(pi17), .Z(n641));
IV2 U676 ( .A(n641), .Z(n644));
AN2 U677 ( .A(pi17), .B(n642), .Z(n643));
OR2 U678 ( .A(n644), .B(n643), .Z(n646));
OR2 U679 ( .A(n647), .B(n646), .Z(n645));
IV2 U680 ( .A(n645), .Z(n649));
AN2 U681 ( .A(n647), .B(n646), .Z(n648));
OR2 U682 ( .A(n649), .B(n648), .Z(po15));
IV2 U683 ( .A(pi42), .Z(n650));
AN2 U684 ( .A(pi49), .B(n650), .Z(n653));
IV2 U685 ( .A(pi49), .Z(n651));
AN2 U686 ( .A(pi42), .B(n651), .Z(n652));
OR2 U687 ( .A(n653), .B(n652), .Z(n658));
OR2 U688 ( .A(n654), .B(pi39), .Z(n657));
IV2 U689 ( .A(pi39), .Z(n655));
OR2 U690 ( .A(n655), .B(pi35), .Z(n656));
AN2 U691 ( .A(n657), .B(n656), .Z(n659));
OR2 U692 ( .A(n658), .B(n659), .Z(n662));
AN2 U693 ( .A(n659), .B(n658), .Z(n660));
IV2 U694 ( .A(n660), .Z(n661));
AN2 U695 ( .A(n662), .B(n661), .Z(n668));
IV2 U696 ( .A(pi04), .Z(n664));
OR2 U697 ( .A(n664), .B(pi18), .Z(n663));
IV2 U698 ( .A(n663), .Z(n666));
AN2 U699 ( .A(pi18), .B(n664), .Z(n665));
OR2 U700 ( .A(n666), .B(n665), .Z(n667));
OR2 U701 ( .A(n668), .B(n667), .Z(n671));
AN2 U702 ( .A(n668), .B(n667), .Z(n669));
IV2 U703 ( .A(n669), .Z(n670));
AN2 U704 ( .A(n671), .B(n670), .Z(n677));
IV2 U705 ( .A(pi22), .Z(n673));
OR2 U706 ( .A(n673), .B(pi14), .Z(n672));
IV2 U707 ( .A(n672), .Z(n675));
AN2 U708 ( .A(pi14), .B(n673), .Z(n674));
OR2 U709 ( .A(n675), .B(n674), .Z(n676));
OR2 U710 ( .A(n677), .B(n676), .Z(n680));
AN2 U711 ( .A(n677), .B(n676), .Z(n678));
IV2 U712 ( .A(n678), .Z(n679));
AN2 U713 ( .A(n680), .B(n679), .Z(n687));
IV2 U714 ( .A(pi40), .Z(n682));
OR2 U715 ( .A(n682), .B(pi23), .Z(n681));
IV2 U716 ( .A(n681), .Z(n684));
AN2 U717 ( .A(pi23), .B(n682), .Z(n683));
OR2 U718 ( .A(n684), .B(n683), .Z(n686));
OR2 U719 ( .A(n687), .B(n686), .Z(n685));
IV2 U720 ( .A(n685), .Z(n689));
AN2 U721 ( .A(n687), .B(n686), .Z(n688));
OR2 U722 ( .A(n689), .B(n688), .Z(po20));
AN2 U723 ( .A(pi01), .B(pi02), .Z(po21));
IV2 U724 ( .A(po25), .Z(n690));
OR2 U725 ( .A(n691), .B(n690), .Z(po23));
IV2 U726 ( .A(pi16), .Z(n696));
OR2 U727 ( .A(n692), .B(n696), .Z(po11));
AN2 U728 ( .A(pi07), .B(pi41), .Z(n693));
IV2 U729 ( .A(n693), .Z(n695));
OR2 U730 ( .A(n694), .B(n695), .Z(po01));
OR2 U731 ( .A(n696), .B(n695), .Z(po05));
endmodule
module IV2(A, Z);
input A;
output Z;
assign Z = ~A;
endmodule
module AN2(A, B, Z);
input A, B;
output Z;
assign Z = A & B;
endmodule
module OR2(A, B, Z);
input A, B;
output Z;
assign Z = A | B;
endmodule

41
examples/smtbmc/glift/C880.ys Normal file
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read_verilog C880.v
techmap
flatten
select C880_lev2
glift -create-instrumented-model
techmap
opt
rename C880_lev2 uut
cd ..
delete [AIONX][NVXR]2
read_verilog C880.v
techmap
flatten
select C880_lev2
glift -create-precise-model
techmap
opt
rename C880_lev2 spec
cd ..
delete [AIONX][NVXR]2
design -push-copy
miter -equiv spec uut miter
flatten
delete uut spec
techmap
opt
stat miter
qbfsat -O2 -write-solution C880.soln -solver yices -timeout 3600 -nocleanup -assume-outputs -assume-negative-polarity miter
design -pop
stat
copy uut solved
qbfsat -specialize-from-file C880.soln solved
opt solved
miter -equiv spec solved satmiter
flatten
sat -prove trigger 0 satmiter
delete satmiter
stat
shell

400
examples/smtbmc/glift/alu2.v Executable file
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module alu2_lev2(pi0, pi1, pi2, pi3, pi4, pi5, pi6, pi7, pi8, pi9,
po0, po1, po2, po3, po4, po5);
input pi0, pi1, pi2, pi3, pi4, pi5, pi6, pi7, pi8, pi9;
output po0, po1, po2, po3, po4, po5;
wire n358, n359, n360, n361, n362, n363, n364, n365, n366, n367,
n368, n369, n370, n371, n372, n373, n374, n375, n376, n377,
n378, n379, n380, n381, n382, n383, n384, n385, n386, n387,
n388, n389, n390, n391, n392, n393, n394, n395, n396, n397,
n398, n399, n400, n401, n402, n403, n404, n405, n406, n407,
n408, n409, n410, n411, n412, n413, n414, n415, n416, n417,
n418, n419, n420, n421, n422, n423, n424, n425, n426, n427,
n428, n429, n430, n431, n432, n433, n434, n435, n436, n437,
n438, n439, n440, n441, n442, n443, n444, n445, n446, n447,
n448, n449, n450, n451, n452, n453, n454, n455, n456, n457,
n458, n459, n460, n461, n462, n463, n464, n465, n466, n467,
n468, n469, n470, n471, n472, n473, n474, n475, n476, n477,
n478, n479, n480, n481, n482, n483, n484, n485, n486, n487,
n488, n489, n490, n491, n492, n493, n494, n495, n496, n497,
n498, n499, n500, n501, n502, n503, n504, n505, n506, n507,
n508, n509, n510, n511, n512, n513, n514, n515, n516, n517,
n518, n519, n520, n521, n522, n523, n524, n525, n526, n527,
n528, n529, n530, n531, n532, n533, n534, n535, n536, n537,
n538, n539, n540, n541, n542, n543, n544, n545, n546, n547,
n548, n549, n550, n551, n552, n553, n554, n555, n556, n557,
n558, n559, n560, n561, n562, n563, n564, n565, n566, n567,
n568, n569, n570, n571, n572, n573, n574, n575, n576, n577,
n578, n579, n580, n581, n582, n583, n584, n585, n586, n587,
n588, n589, n590, n591, n592, n593, n594, n595, n596, n597,
n598, n599, n600, n601, n602, n603, n604, n605, n606, n607,
n608, n609, n610, n611, n612, n613, n614, n615, n616, n617,
n618, n619, n620, n621, n622, n623, n624, n625, n626, n627,
n628, n629, n630, n631, n632, n633, n634, n635, n636, n637,
n638, n639, n640, n641, n642, n643, n644, n645, n646, n647,
n648, n649, n650, n651, n652, n653, n654, n655, n656, n657,
n658, n659, n660, n661, n662, n663, n664, n665, n666, n667,
n668, n669, n670, n671, n672, n673, n674, n675, n676, n677,
n678, n679, n680, n681, n682, n683, n684, n685, n686, n687;
AN2 U363 ( .A(n358), .B(po2), .Z(po5));
OR2 U364 ( .A(n359), .B(n360), .Z(n358));
AN2 U365 ( .A(n361), .B(n362), .Z(n359));
AN2 U366 ( .A(pi9), .B(n363), .Z(po4));
OR2 U367 ( .A(n364), .B(n365), .Z(n363));
OR2 U368 ( .A(n366), .B(n367), .Z(n365));
AN2 U369 ( .A(pi6), .B(n368), .Z(n367));
OR2 U370 ( .A(n369), .B(n370), .Z(n368));
OR2 U371 ( .A(n371), .B(n372), .Z(n370));
OR2 U372 ( .A(n373), .B(n374), .Z(n372));
AN2 U373 ( .A(n375), .B(n376), .Z(n374));
AN2 U374 ( .A(n377), .B(n378), .Z(n375));
OR2 U375 ( .A(n379), .B(n380), .Z(n377));
OR2 U376 ( .A(n381), .B(n382), .Z(n380));
OR2 U377 ( .A(n383), .B(n384), .Z(n379));
AN2 U378 ( .A(n385), .B(pi5), .Z(n384));
AN2 U379 ( .A(n386), .B(n387), .Z(n383));
AN2 U380 ( .A(pi4), .B(n361), .Z(n386));
AN2 U381 ( .A(n388), .B(n389), .Z(n373));
OR2 U382 ( .A(n390), .B(n391), .Z(n388));
AN2 U383 ( .A(pi1), .B(n392), .Z(n390));
OR2 U384 ( .A(n393), .B(n394), .Z(n392));
OR2 U385 ( .A(pi7), .B(n395), .Z(n394));
AN2 U386 ( .A(n381), .B(n396), .Z(n395));
OR2 U387 ( .A(n397), .B(n398), .Z(n369));
AN2 U388 ( .A(n399), .B(n400), .Z(n398));
AN2 U389 ( .A(n387), .B(n401), .Z(n399));
AN2 U390 ( .A(n402), .B(n403), .Z(n397));
AN2 U391 ( .A(pi0), .B(n404), .Z(n402));
OR2 U392 ( .A(pi1), .B(n389), .Z(n404));
AN2 U393 ( .A(n405), .B(n406), .Z(n366));
OR2 U394 ( .A(n407), .B(n408), .Z(n406));
AN2 U395 ( .A(n360), .B(n409), .Z(n408));
OR2 U396 ( .A(n410), .B(n411), .Z(n409));
OR2 U397 ( .A(n412), .B(n413), .Z(n411));
AN2 U398 ( .A(n414), .B(pi3), .Z(n413));
AN2 U399 ( .A(n389), .B(n415), .Z(n410));
AN2 U400 ( .A(po3), .B(n416), .Z(n407));
OR2 U401 ( .A(n417), .B(n414), .Z(n416));
OR2 U402 ( .A(n418), .B(n419), .Z(n364));
OR2 U403 ( .A(n420), .B(n421), .Z(n419));
AN2 U404 ( .A(n422), .B(n382), .Z(n421));
AN2 U405 ( .A(pi7), .B(n389), .Z(n422));
AN2 U406 ( .A(n423), .B(n424), .Z(n418));
AN2 U407 ( .A(n425), .B(n426), .Z(n423));
OR2 U408 ( .A(n427), .B(po3), .Z(po2));
AN2 U409 ( .A(n428), .B(n429), .Z(n427));
OR2 U410 ( .A(n430), .B(n431), .Z(po1));
AN2 U411 ( .A(pi9), .B(n432), .Z(n431));
OR2 U412 ( .A(n433), .B(n434), .Z(n432));
OR2 U413 ( .A(n435), .B(n436), .Z(n434));
AN2 U414 ( .A(n437), .B(n438), .Z(n436));
IV2 U415 ( .A(n425), .Z(n438));
AN2 U416 ( .A(n424), .B(n426), .Z(n437));
OR2 U417 ( .A(n439), .B(n440), .Z(n424));
OR2 U418 ( .A(n441), .B(n442), .Z(n440));
AN2 U419 ( .A(n381), .B(n443), .Z(n442));
OR2 U420 ( .A(n444), .B(n445), .Z(n443));
AN2 U421 ( .A(n446), .B(n447), .Z(n441));
AN2 U422 ( .A(n387), .B(n361), .Z(n446));
AN2 U423 ( .A(n448), .B(n425), .Z(n435));
OR2 U424 ( .A(n449), .B(n450), .Z(n425));
OR2 U425 ( .A(n420), .B(n451), .Z(n450));
OR2 U426 ( .A(n452), .B(n453), .Z(n451));
AN2 U427 ( .A(pi6), .B(n454), .Z(n453));
OR2 U428 ( .A(n371), .B(n455), .Z(n454));
AN2 U429 ( .A(n376), .B(n456), .Z(n455));
OR2 U430 ( .A(n457), .B(n458), .Z(n456));
OR2 U431 ( .A(n459), .B(n460), .Z(n458));
AN2 U432 ( .A(n461), .B(n378), .Z(n460));
OR2 U433 ( .A(n462), .B(n463), .Z(n461));
AN2 U434 ( .A(n385), .B(n464), .Z(n462));
OR2 U435 ( .A(n465), .B(pi5), .Z(n464));
AN2 U436 ( .A(pi7), .B(n466), .Z(n459));
OR2 U437 ( .A(n467), .B(n468), .Z(n466));
OR2 U438 ( .A(n469), .B(n470), .Z(n468));
AN2 U439 ( .A(n381), .B(pi1), .Z(n470));
AN2 U440 ( .A(n471), .B(n428), .Z(n469));
AN2 U441 ( .A(pi0), .B(n387), .Z(n471));
AN2 U442 ( .A(n412), .B(n361), .Z(n467));
AN2 U443 ( .A(n472), .B(n473), .Z(n457));
AN2 U444 ( .A(n360), .B(n428), .Z(n472));
AN2 U445 ( .A(n463), .B(n428), .Z(n371));
AN2 U446 ( .A(n474), .B(n475), .Z(n452));
OR2 U447 ( .A(n476), .B(n477), .Z(n474));
OR2 U448 ( .A(n478), .B(n479), .Z(n477));
AN2 U449 ( .A(n480), .B(n428), .Z(n479));
AN2 U450 ( .A(n481), .B(n482), .Z(n480));
OR2 U451 ( .A(n360), .B(n389), .Z(n482));
OR2 U452 ( .A(n401), .B(n483), .Z(n481));
AN2 U453 ( .A(pi7), .B(n484), .Z(n483));
OR2 U454 ( .A(n393), .B(n485), .Z(n484));
AN2 U455 ( .A(n376), .B(n415), .Z(n485));
AN2 U456 ( .A(n414), .B(n429), .Z(n393));
AN2 U457 ( .A(n486), .B(n378), .Z(n478));
OR2 U458 ( .A(n412), .B(n389), .Z(n486));
AN2 U459 ( .A(n487), .B(pi1), .Z(n412));
OR2 U460 ( .A(n488), .B(n489), .Z(n476));
AN2 U461 ( .A(n490), .B(n401), .Z(n488));
AN2 U462 ( .A(pi1), .B(n429), .Z(n490));
AN2 U463 ( .A(n385), .B(n491), .Z(n420));
IV2 U464 ( .A(n492), .Z(n491));
OR2 U465 ( .A(n493), .B(n487), .Z(n492));
AN2 U466 ( .A(n494), .B(n495), .Z(n493));
OR2 U467 ( .A(pi6), .B(n389), .Z(n495));
OR2 U468 ( .A(pi7), .B(pi1), .Z(n494));
OR2 U469 ( .A(n496), .B(n497), .Z(n449));
AN2 U470 ( .A(n498), .B(n376), .Z(n497));
AN2 U471 ( .A(n381), .B(n382), .Z(n498));
AN2 U472 ( .A(n499), .B(n389), .Z(n496));
OR2 U473 ( .A(n500), .B(n501), .Z(n499));
OR2 U474 ( .A(n502), .B(n503), .Z(n501));
AN2 U475 ( .A(n385), .B(n504), .Z(n503));
OR2 U476 ( .A(n505), .B(n506), .Z(n504));
AN2 U477 ( .A(po3), .B(n400), .Z(n506));
AN2 U478 ( .A(n507), .B(n428), .Z(n505));
AN2 U479 ( .A(n508), .B(n387), .Z(n502));
OR2 U480 ( .A(n509), .B(n510), .Z(n508));
OR2 U481 ( .A(n489), .B(n511), .Z(n510));
OR2 U482 ( .A(n465), .B(n512), .Z(n511));
AN2 U483 ( .A(n513), .B(pi1), .Z(n512));
AN2 U484 ( .A(pi0), .B(n514), .Z(n513));
OR2 U485 ( .A(n507), .B(n515), .Z(n514));
AN2 U486 ( .A(n361), .B(n428), .Z(n465));
AN2 U487 ( .A(po3), .B(n360), .Z(n489));
OR2 U488 ( .A(n516), .B(n517), .Z(n509));
OR2 U489 ( .A(n518), .B(n519), .Z(n517));
AN2 U490 ( .A(n391), .B(n362), .Z(n519));
AN2 U491 ( .A(n428), .B(n400), .Z(n391));
AN2 U492 ( .A(n520), .B(n521), .Z(n518));
OR2 U493 ( .A(n522), .B(n362), .Z(n521));
AN2 U494 ( .A(n429), .B(n523), .Z(n520));
AN2 U495 ( .A(n417), .B(n378), .Z(n516));
AN2 U496 ( .A(n522), .B(n382), .Z(n500));
AN2 U497 ( .A(pi1), .B(n396), .Z(n382));
AN2 U498 ( .A(n361), .B(n378), .Z(n522));
OR2 U499 ( .A(n524), .B(n525), .Z(n448));
OR2 U500 ( .A(n526), .B(n527), .Z(n525));
OR2 U501 ( .A(pi8), .B(n528), .Z(n524));
AN2 U502 ( .A(n529), .B(n530), .Z(n430));
OR2 U503 ( .A(n531), .B(n532), .Z(n529));
OR2 U504 ( .A(n533), .B(n534), .Z(n532));
OR2 U505 ( .A(n535), .B(n536), .Z(n534));
AN2 U506 ( .A(n537), .B(n376), .Z(n536));
IV2 U507 ( .A(n389), .Z(n376));
AN2 U508 ( .A(n538), .B(n389), .Z(n535));
OR2 U509 ( .A(n539), .B(n540), .Z(n389));
OR2 U510 ( .A(n541), .B(n542), .Z(n540));
OR2 U511 ( .A(n543), .B(n544), .Z(n542));
AN2 U512 ( .A(pi1), .B(n545), .Z(n544));
AN2 U513 ( .A(n546), .B(n428), .Z(n543));
AN2 U514 ( .A(n547), .B(n548), .Z(n546));
OR2 U515 ( .A(pi3), .B(n396), .Z(n548));
AN2 U516 ( .A(pi9), .B(n549), .Z(n541));
OR2 U517 ( .A(n550), .B(n551), .Z(n549));
OR2 U518 ( .A(n552), .B(n553), .Z(n551));
AN2 U519 ( .A(n554), .B(n507), .Z(n553));
AN2 U520 ( .A(n396), .B(pi0), .Z(n554));
AN2 U521 ( .A(n555), .B(n556), .Z(n552));
AN2 U522 ( .A(n557), .B(n415), .Z(n556));
AN2 U523 ( .A(po3), .B(n558), .Z(n555));
OR2 U524 ( .A(n559), .B(n560), .Z(n550));
AN2 U525 ( .A(n561), .B(n429), .Z(n560));
AN2 U526 ( .A(n417), .B(n562), .Z(n561));
OR2 U527 ( .A(n563), .B(n564), .Z(n562));
AN2 U528 ( .A(n558), .B(n428), .Z(n564));
AN2 U529 ( .A(pi1), .B(n565), .Z(n563));
AN2 U530 ( .A(pi3), .B(n566), .Z(n559));
OR2 U531 ( .A(n567), .B(n414), .Z(n566));
AN2 U532 ( .A(n568), .B(n569), .Z(n567));
AN2 U533 ( .A(n565), .B(n428), .Z(n568));
OR2 U534 ( .A(n570), .B(n571), .Z(n539));
AN2 U535 ( .A(n572), .B(n429), .Z(n571));
AN2 U536 ( .A(po3), .B(n573), .Z(n570));
OR2 U537 ( .A(n574), .B(n575), .Z(n538));
OR2 U538 ( .A(n445), .B(n576), .Z(n575));
AN2 U539 ( .A(n577), .B(pi3), .Z(n576));
AN2 U540 ( .A(n578), .B(pi1), .Z(n574));
AN2 U541 ( .A(n507), .B(pi1), .Z(n533));
OR2 U542 ( .A(n579), .B(n580), .Z(n531));
OR2 U543 ( .A(n581), .B(n582), .Z(n580));
AN2 U544 ( .A(n444), .B(po3), .Z(n582));
AN2 U545 ( .A(pi1), .B(pi3), .Z(po3));
AN2 U546 ( .A(n583), .B(n557), .Z(n581));
AN2 U547 ( .A(n584), .B(n429), .Z(n583));
OR2 U548 ( .A(n585), .B(n414), .Z(n584));
AN2 U549 ( .A(n417), .B(n428), .Z(n585));
AN2 U550 ( .A(n586), .B(pi7), .Z(n579));
AN2 U551 ( .A(n587), .B(n588), .Z(n586));
OR2 U552 ( .A(pi3), .B(n589), .Z(n588));
AN2 U553 ( .A(pi1), .B(n523), .Z(n589));
OR2 U554 ( .A(n429), .B(n590), .Z(n587));
OR2 U555 ( .A(n417), .B(n591), .Z(n590));
AN2 U556 ( .A(n592), .B(n428), .Z(n591));
IV2 U557 ( .A(pi1), .Z(n428));
IV2 U558 ( .A(pi3), .Z(n429));
OR2 U559 ( .A(n593), .B(n594), .Z(po0));
OR2 U560 ( .A(n595), .B(n596), .Z(n594));
AN2 U561 ( .A(n597), .B(pi8), .Z(n596));
AN2 U562 ( .A(n598), .B(n381), .Z(n597));
AN2 U563 ( .A(pi0), .B(n385), .Z(n381));
AN2 U564 ( .A(n507), .B(n487), .Z(n598));
AN2 U565 ( .A(n528), .B(n426), .Z(n595));
AN2 U566 ( .A(pi6), .B(n599), .Z(n528));
IV2 U567 ( .A(n600), .Z(n599));
OR2 U568 ( .A(n601), .B(n361), .Z(n600));
AN2 U569 ( .A(n602), .B(n603), .Z(n601));
AN2 U570 ( .A(n604), .B(n605), .Z(n603));
OR2 U571 ( .A(pi7), .B(n606), .Z(n605));
OR2 U572 ( .A(n607), .B(n387), .Z(n606));
OR2 U573 ( .A(n378), .B(n487), .Z(n604));
AN2 U574 ( .A(n608), .B(n609), .Z(n602));
OR2 U575 ( .A(pi2), .B(n415), .Z(n608));
OR2 U576 ( .A(n610), .B(n611), .Z(n593));
AN2 U577 ( .A(pi9), .B(n612), .Z(n611));
OR2 U578 ( .A(n613), .B(n614), .Z(n612));
OR2 U579 ( .A(n433), .B(n615), .Z(n614));
AN2 U580 ( .A(n527), .B(n426), .Z(n615));
OR2 U581 ( .A(n616), .B(n617), .Z(n527));
AN2 U582 ( .A(n618), .B(n361), .Z(n617));
OR2 U583 ( .A(n619), .B(n620), .Z(n618));
OR2 U584 ( .A(n621), .B(n622), .Z(n620));
AN2 U585 ( .A(n592), .B(n362), .Z(n622));
AN2 U586 ( .A(n385), .B(n623), .Z(n621));
OR2 U587 ( .A(n624), .B(n625), .Z(n623));
AN2 U588 ( .A(n626), .B(n415), .Z(n625));
AN2 U589 ( .A(n507), .B(n523), .Z(n624));
AN2 U590 ( .A(n473), .B(n557), .Z(n619));
AN2 U591 ( .A(n523), .B(n387), .Z(n473));
AN2 U592 ( .A(n569), .B(n387), .Z(n616));
AN2 U593 ( .A(n578), .B(n627), .Z(n433));
AN2 U594 ( .A(n378), .B(n475), .Z(n627));
OR2 U595 ( .A(n628), .B(n629), .Z(n613));
AN2 U596 ( .A(n526), .B(n426), .Z(n629));
IV2 U597 ( .A(pi8), .Z(n426));
AN2 U598 ( .A(n360), .B(n405), .Z(n526));
AN2 U599 ( .A(pi8), .B(n630), .Z(n628));
OR2 U600 ( .A(n631), .B(n439), .Z(n630));
OR2 U601 ( .A(n632), .B(n633), .Z(n439));
OR2 U602 ( .A(n634), .B(n635), .Z(n633));
AN2 U603 ( .A(n636), .B(n378), .Z(n635));
OR2 U604 ( .A(n637), .B(n360), .Z(n636));
AN2 U605 ( .A(n387), .B(n475), .Z(n637));
AN2 U606 ( .A(n638), .B(n475), .Z(n634));
OR2 U607 ( .A(n639), .B(n640), .Z(n638));
AN2 U608 ( .A(n558), .B(pi4), .Z(n639));
OR2 U609 ( .A(n463), .B(n641), .Z(n632));
AN2 U610 ( .A(n642), .B(n385), .Z(n641));
AN2 U611 ( .A(n557), .B(n361), .Z(n642));
AN2 U612 ( .A(n361), .B(n578), .Z(n463));
AN2 U613 ( .A(n403), .B(n361), .Z(n631));
IV2 U614 ( .A(n609), .Z(n403));
OR2 U615 ( .A(n385), .B(n378), .Z(n609));
AN2 U616 ( .A(n643), .B(n530), .Z(n610));
OR2 U617 ( .A(n644), .B(n645), .Z(n643));
OR2 U618 ( .A(n646), .B(n647), .Z(n645));
OR2 U619 ( .A(n648), .B(n649), .Z(n647));
AN2 U620 ( .A(n537), .B(n385), .Z(n649));
IV2 U621 ( .A(n387), .Z(n385));
OR2 U622 ( .A(n650), .B(n651), .Z(n537));
AN2 U623 ( .A(n396), .B(pi6), .Z(n651));
AN2 U624 ( .A(n400), .B(n475), .Z(n650));
AN2 U625 ( .A(n652), .B(n387), .Z(n648));
OR2 U626 ( .A(n653), .B(n654), .Z(n387));
OR2 U627 ( .A(n655), .B(n656), .Z(n654));
OR2 U628 ( .A(n657), .B(n658), .Z(n656));
AN2 U629 ( .A(n360), .B(n573), .Z(n658));
OR2 U630 ( .A(n659), .B(n660), .Z(n573));
AN2 U631 ( .A(n405), .B(n578), .Z(n660));
AN2 U632 ( .A(n396), .B(n661), .Z(n659));
OR2 U633 ( .A(n405), .B(n557), .Z(n661));
AN2 U634 ( .A(n475), .B(pi7), .Z(n405));
IV2 U635 ( .A(n607), .Z(n396));
OR2 U636 ( .A(pi5), .B(pi4), .Z(n607));
AN2 U637 ( .A(n640), .B(n417), .Z(n657));
AN2 U638 ( .A(n572), .B(n362), .Z(n655));
OR2 U639 ( .A(n662), .B(n663), .Z(n572));
OR2 U640 ( .A(n664), .B(n665), .Z(n663));
AN2 U641 ( .A(n578), .B(n557), .Z(n665));
AN2 U642 ( .A(n417), .B(n626), .Z(n664));
AN2 U643 ( .A(n507), .B(n530), .Z(n662));
OR2 U644 ( .A(n666), .B(n667), .Z(n653));
OR2 U645 ( .A(n668), .B(n669), .Z(n667));
AN2 U646 ( .A(n670), .B(n545), .Z(n669));
OR2 U647 ( .A(n400), .B(n671), .Z(n545));
AN2 U648 ( .A(pi9), .B(n414), .Z(n671));
AN2 U649 ( .A(n378), .B(n414), .Z(n400));
IV2 U650 ( .A(pi7), .Z(n378));
OR2 U651 ( .A(pi0), .B(pi2), .Z(n670));
AN2 U652 ( .A(n672), .B(n547), .Z(n668));
AN2 U653 ( .A(n475), .B(n530), .Z(n547));
IV2 U654 ( .A(pi9), .Z(n530));
AN2 U655 ( .A(n361), .B(n415), .Z(n672));
AN2 U656 ( .A(n558), .B(n569), .Z(n666));
AN2 U657 ( .A(n557), .B(n417), .Z(n569));
OR2 U658 ( .A(n673), .B(n674), .Z(n652));
OR2 U659 ( .A(n445), .B(n675), .Z(n674));
AN2 U660 ( .A(n577), .B(pi2), .Z(n675));
AN2 U661 ( .A(n523), .B(n447), .Z(n445));
OR2 U662 ( .A(n577), .B(n507), .Z(n447));
AN2 U663 ( .A(n475), .B(n415), .Z(n577));
AN2 U664 ( .A(n578), .B(pi0), .Z(n673));
IV2 U665 ( .A(n487), .Z(n578));
OR2 U666 ( .A(n415), .B(n523), .Z(n487));
AN2 U667 ( .A(n507), .B(pi0), .Z(n646));
AN2 U668 ( .A(pi6), .B(pi7), .Z(n507));
OR2 U669 ( .A(n676), .B(n677), .Z(n644));
OR2 U670 ( .A(n678), .B(n679), .Z(n677));
AN2 U671 ( .A(n444), .B(n360), .Z(n679));
IV2 U672 ( .A(n401), .Z(n360));
OR2 U673 ( .A(n362), .B(n361), .Z(n401));
AN2 U674 ( .A(pi6), .B(n417), .Z(n444));
AN2 U675 ( .A(n680), .B(n557), .Z(n678));
IV2 U676 ( .A(n626), .Z(n557));
OR2 U677 ( .A(pi7), .B(n475), .Z(n626));
AN2 U678 ( .A(n681), .B(n362), .Z(n680));
OR2 U679 ( .A(n682), .B(n414), .Z(n681));
AN2 U680 ( .A(n417), .B(n361), .Z(n682));
IV2 U681 ( .A(pi0), .Z(n361));
AN2 U682 ( .A(pi7), .B(n683), .Z(n676));
OR2 U683 ( .A(n684), .B(n685), .Z(n683));
OR2 U684 ( .A(n686), .B(n687), .Z(n685));
AN2 U685 ( .A(n592), .B(n558), .Z(n687));
IV2 U686 ( .A(n565), .Z(n558));
OR2 U687 ( .A(pi0), .B(n362), .Z(n565));
AN2 U688 ( .A(n475), .B(n414), .Z(n592));
IV2 U689 ( .A(n515), .Z(n414));
OR2 U690 ( .A(pi5), .B(n415), .Z(n515));
IV2 U691 ( .A(pi6), .Z(n475));
AN2 U692 ( .A(n640), .B(n523), .Z(n686));
IV2 U693 ( .A(pi5), .Z(n523));
AN2 U694 ( .A(n362), .B(pi0), .Z(n640));
IV2 U695 ( .A(pi2), .Z(n362));
AN2 U696 ( .A(n417), .B(pi2), .Z(n684));
AN2 U697 ( .A(n415), .B(pi5), .Z(n417));
IV2 U698 ( .A(pi4), .Z(n415));
endmodule
module IV2(A, Z);
input A;
output Z;
assign Z = ~A;
endmodule
module AN2(A, B, Z);
input A, B;
output Z;
assign Z = A & B;
endmodule
module OR2(A, B, Z);
input A, B;
output Z;
assign Z = A | B;
endmodule

41
examples/smtbmc/glift/alu2.ys Normal file
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@ -0,0 +1,41 @@
read_verilog alu2.v
techmap
flatten
select alu2_lev2
glift -create-instrumented-model
techmap
opt
rename alu2_lev2 uut
cd ..
delete [AIONX][NVXR]2
read_verilog alu2.v
techmap
flatten
select alu2_lev2
glift -create-precise-model
techmap
opt
rename alu2_lev2 spec
cd ..
delete [AIONX][NVXR]2
design -push-copy
miter -equiv spec uut miter
flatten
delete uut spec
techmap
opt
stat miter
qbfsat -O2 -write-solution alu2.soln -solver yices -timeout 3600 -nocleanup -assume-outputs -assume-negative-polarity miter
design -pop
stat
copy uut solved
qbfsat -specialize-from-file alu2.soln solved
opt solved
miter -equiv spec solved satmiter
flatten
sat -prove trigger 0 satmiter
delete satmiter
stat
shell

802
examples/smtbmc/glift/alu4.v Executable file
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module alu4_lev2(pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09,
pi10, pi11, pi12, pi13, po0, po1, po2, po3, po4, po5, po6, po7);
input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09,
pi10, pi11, pi12, pi13;
output po0, po1, po2, po3, po4, po5, po6, po7;
wire n705, n706, n707, n708, n709, n710, n711, n712, n713, n714,
n715, n716, n717, n718, n719, n720, n721, n722, n723, n724,
n725, n726, n727, n728, n729, n730, n731, n732, n733, n734,
n735, n736, n737, n738, n739, n740, n741, n742, n743, n744,
n745, n746, n747, n748, n749, n750, n751, n752, n753, n754,
n755, n756, n757, n758, n759, n760, n761, n762, n763, n764,
n765, n766, n767, n768, n769, n770, n771, n772, n773, n774,
n775, n776, n777, n778, n779, n780, n781, n782, n783, n784,
n785, n786, n787, n788, n789, n790, n791, n792, n793, n794,
n795, n796, n797, n798, n799, n800, n801, n802, n803, n804,
n805, n806, n807, n808, n809, n810, n811, n812, n813, n814,
n815, n816, n817, n818, n819, n820, n821, n822, n823, n824,
n825, n826, n827, n828, n829, n830, n831, n832, n833, n834,
n835, n836, n837, n838, n839, n840, n841, n842, n843, n844,
n845, n846, n847, n848, n849, n850, n851, n852, n853, n854,
n855, n856, n857, n858, n859, n860, n861, n862, n863, n864,
n865, n866, n867, n868, n869, n870, n871, n872, n873, n874,
n875, n876, n877, n878, n879, n880, n881, n882, n883, n884,
n885, n886, n887, n888, n889, n890, n891, n892, n893, n894,
n895, n896, n897, n898, n899, n900, n901, n902, n903, n904,
n905, n906, n907, n908, n909, n910, n911, n912, n913, n914,
n915, n916, n917, n918, n919, n920, n921, n922, n923, n924,
n925, n926, n927, n928, n929, n930, n931, n932, n933, n934,
n935, n936, n937, n938, n939, n940, n941, n942, n943, n944,
n945, n946, n947, n948, n949, n950, n951, n952, n953, n954,
n955, n956, n957, n958, n959, n960, n961, n962, n963, n964,
n965, n966, n967, n968, n969, n970, n971, n972, n973, n974,
n975, n976, n977, n978, n979, n980, n981, n982, n983, n984,
n985, n986, n987, n988, n989, n990, n991, n992, n993, n994,
n995, n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004,
n1005, n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014,
n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024,
n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034,
n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044,
n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054,
n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064,
n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074,
n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084,
n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094,
n1095, n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104,
n1105, n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114,
n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124,
n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134,
n1135, n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144,
n1145, n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154,
n1155, n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164,
n1165, n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174,
n1175, n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184,
n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194,
n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204,
n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214,
n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224,
n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234,
n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244,
n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254,
n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264,
n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274,
n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284,
n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294,
n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304,
n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314,
n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324,
n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334,
n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344,
n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354,
n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364,
n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374,
n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384,
n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394,
n1395, n1396;
AN2 U712 ( .A(n705), .B(po4), .Z(po7));
OR2 U713 ( .A(n706), .B(n707), .Z(n705));
AN2 U714 ( .A(n708), .B(n709), .Z(n707));
OR2 U715 ( .A(n710), .B(n711), .Z(n708));
AN2 U716 ( .A(n712), .B(n713), .Z(n711));
AN2 U717 ( .A(n714), .B(n715), .Z(n710));
AN2 U718 ( .A(n716), .B(n717), .Z(n714));
AN2 U719 ( .A(n718), .B(n719), .Z(n706));
OR2 U720 ( .A(n720), .B(n712), .Z(n719));
OR2 U721 ( .A(n721), .B(n722), .Z(n712));
AN2 U722 ( .A(n723), .B(n724), .Z(n722));
AN2 U723 ( .A(n725), .B(n726), .Z(n721));
OR2 U724 ( .A(n724), .B(n727), .Z(n726));
AN2 U725 ( .A(n727), .B(n723), .Z(n720));
OR2 U726 ( .A(n728), .B(n729), .Z(po6));
AN2 U727 ( .A(pi13), .B(n730), .Z(n729));
OR2 U728 ( .A(n731), .B(n732), .Z(n730));
OR2 U729 ( .A(n733), .B(n734), .Z(n732));
OR2 U730 ( .A(n735), .B(n736), .Z(n734));
AN2 U731 ( .A(n737), .B(n738), .Z(n736));
OR2 U732 ( .A(n739), .B(n740), .Z(n737));
OR2 U733 ( .A(n741), .B(n742), .Z(n740));
AN2 U734 ( .A(n743), .B(n744), .Z(n742));
OR2 U735 ( .A(n745), .B(n746), .Z(n743));
AN2 U736 ( .A(pi03), .B(n747), .Z(n745));
AN2 U737 ( .A(n748), .B(n749), .Z(n741));
AN2 U738 ( .A(n750), .B(n751), .Z(n748));
AN2 U739 ( .A(pi11), .B(n752), .Z(n735));
OR2 U740 ( .A(n753), .B(n754), .Z(n752));
OR2 U741 ( .A(n755), .B(n756), .Z(n754));
AN2 U742 ( .A(n757), .B(n747), .Z(n756));
OR2 U743 ( .A(n758), .B(n759), .Z(n757));
IV2 U744 ( .A(n760), .Z(n755));
AN2 U745 ( .A(n761), .B(n762), .Z(n753));
OR2 U746 ( .A(n763), .B(po5), .Z(n762));
AN2 U747 ( .A(n764), .B(n765), .Z(n763));
AN2 U748 ( .A(n766), .B(n767), .Z(n733));
OR2 U749 ( .A(n768), .B(n769), .Z(n767));
AN2 U750 ( .A(n770), .B(n771), .Z(n768));
IV2 U751 ( .A(n772), .Z(n766));
OR2 U752 ( .A(n773), .B(n774), .Z(n731));
AN2 U753 ( .A(n775), .B(n776), .Z(n774));
AN2 U754 ( .A(n777), .B(n778), .Z(n775));
AN2 U755 ( .A(n779), .B(n780), .Z(n773));
AN2 U756 ( .A(n781), .B(n782), .Z(n779));
AN2 U757 ( .A(n783), .B(n781), .Z(n728));
AN2 U758 ( .A(n782), .B(n784), .Z(n783));
OR2 U759 ( .A(n785), .B(n786), .Z(po3));
OR2 U760 ( .A(n787), .B(n788), .Z(n786));
OR2 U761 ( .A(n789), .B(n790), .Z(n788));
OR2 U762 ( .A(n791), .B(n792), .Z(n790));
AN2 U763 ( .A(n793), .B(n782), .Z(n792));
AN2 U764 ( .A(n794), .B(n795), .Z(n791));
OR2 U765 ( .A(n796), .B(n797), .Z(n789));
IV2 U766 ( .A(n798), .Z(n797));
OR2 U767 ( .A(n799), .B(n778), .Z(n798));
AN2 U768 ( .A(n778), .B(n799), .Z(n796));
OR2 U769 ( .A(n800), .B(n801), .Z(n799));
IV2 U770 ( .A(n802), .Z(n778));
OR2 U771 ( .A(n803), .B(n804), .Z(n802));
AN2 U772 ( .A(n805), .B(n806), .Z(n803));
AN2 U773 ( .A(n807), .B(n808), .Z(n806));
AN2 U774 ( .A(n809), .B(n810), .Z(n808));
OR2 U775 ( .A(pi11), .B(n811), .Z(n810));
AN2 U776 ( .A(n812), .B(n813), .Z(n811));
AN2 U777 ( .A(n814), .B(n815), .Z(n813));
OR2 U778 ( .A(n782), .B(n816), .Z(n815));
OR2 U779 ( .A(n817), .B(n818), .Z(n814));
OR2 U780 ( .A(n819), .B(n820), .Z(n818));
AN2 U781 ( .A(n750), .B(n821), .Z(n820));
AN2 U782 ( .A(n749), .B(n747), .Z(n819));
IV2 U783 ( .A(n821), .Z(n749));
AN2 U784 ( .A(n822), .B(n823), .Z(n812));
OR2 U785 ( .A(n824), .B(n825), .Z(n823));
OR2 U786 ( .A(n826), .B(n827), .Z(n822));
AN2 U787 ( .A(pi10), .B(n828), .Z(n826));
OR2 U788 ( .A(n829), .B(n830), .Z(n828));
OR2 U789 ( .A(n831), .B(n738), .Z(n809));
AN2 U790 ( .A(n832), .B(n833), .Z(n831));
AN2 U791 ( .A(n834), .B(n760), .Z(n833));
OR2 U792 ( .A(n817), .B(n835), .Z(n760));
OR2 U793 ( .A(pi03), .B(n836), .Z(n835));
OR2 U794 ( .A(n817), .B(n837), .Z(n834));
OR2 U795 ( .A(n715), .B(n827), .Z(n837));
IV2 U796 ( .A(n836), .Z(n715));
AN2 U797 ( .A(n838), .B(n839), .Z(n832));
OR2 U798 ( .A(n765), .B(n840), .Z(n839));
OR2 U799 ( .A(n841), .B(n825), .Z(n840));
OR2 U800 ( .A(n816), .B(n842), .Z(n838));
OR2 U801 ( .A(n843), .B(n844), .Z(n842));
AN2 U802 ( .A(n845), .B(n846), .Z(n844));
OR2 U803 ( .A(n847), .B(n848), .Z(n845));
AN2 U804 ( .A(n758), .B(n747), .Z(n848));
IV2 U805 ( .A(n849), .Z(n758));
AN2 U806 ( .A(n750), .B(n849), .Z(n847));
AN2 U807 ( .A(n849), .B(n759), .Z(n843));
OR2 U808 ( .A(n850), .B(n851), .Z(n849));
AN2 U809 ( .A(n852), .B(n853), .Z(n850));
IV2 U810 ( .A(n854), .Z(n816));
AN2 U811 ( .A(n855), .B(n856), .Z(n807));
OR2 U812 ( .A(n857), .B(n858), .Z(n856));
OR2 U813 ( .A(n859), .B(n860), .Z(n858));
AN2 U814 ( .A(n861), .B(n739), .Z(n859));
OR2 U815 ( .A(n862), .B(n863), .Z(n739));
AN2 U816 ( .A(n759), .B(n795), .Z(n862));
OR2 U817 ( .A(n846), .B(n864), .Z(n861));
IV2 U818 ( .A(n865), .Z(n864));
AN2 U819 ( .A(n795), .B(n863), .Z(n865));
IV2 U820 ( .A(n759), .Z(n846));
OR2 U821 ( .A(n866), .B(n867), .Z(n759));
AN2 U822 ( .A(n868), .B(po5), .Z(n867));
AN2 U823 ( .A(n750), .B(n869), .Z(n866));
OR2 U824 ( .A(n825), .B(n870), .Z(n855));
OR2 U825 ( .A(n871), .B(n872), .Z(n870));
AN2 U826 ( .A(n764), .B(n873), .Z(n872));
IV2 U827 ( .A(po5), .Z(n873));
AN2 U828 ( .A(n841), .B(po4), .Z(n871));
OR2 U829 ( .A(n874), .B(po5), .Z(po4));
IV2 U830 ( .A(n764), .Z(n841));
OR2 U831 ( .A(n875), .B(n724), .Z(n764));
AN2 U832 ( .A(n876), .B(n877), .Z(n875));
AN2 U833 ( .A(n878), .B(n879), .Z(n805));
AN2 U834 ( .A(n880), .B(n881), .Z(n879));
OR2 U835 ( .A(n782), .B(n882), .Z(n881));
OR2 U836 ( .A(n781), .B(n883), .Z(n882));
IV2 U837 ( .A(n884), .Z(n781));
OR2 U838 ( .A(n795), .B(n885), .Z(n880));
AN2 U839 ( .A(n886), .B(n887), .Z(n878));
OR2 U840 ( .A(pi03), .B(n888), .Z(n887));
AN2 U841 ( .A(n889), .B(n890), .Z(n888));
IV2 U842 ( .A(n891), .Z(n890));
AN2 U843 ( .A(n830), .B(n892), .Z(n891));
OR2 U844 ( .A(n893), .B(n894), .Z(n830));
IV2 U845 ( .A(n895), .Z(n894));
OR2 U846 ( .A(n746), .B(n750), .Z(n895));
AN2 U847 ( .A(n750), .B(n746), .Z(n893));
OR2 U848 ( .A(n896), .B(n897), .Z(n746));
AN2 U849 ( .A(pi02), .B(n898), .Z(n896));
IV2 U850 ( .A(n747), .Z(n750));
OR2 U851 ( .A(n899), .B(n900), .Z(n747));
AN2 U852 ( .A(n901), .B(n771), .Z(n900));
OR2 U853 ( .A(pi03), .B(n795), .Z(n771));
AN2 U854 ( .A(n902), .B(n903), .Z(n899));
OR2 U855 ( .A(n904), .B(n905), .Z(n903));
OR2 U856 ( .A(n906), .B(n907), .Z(n905));
AN2 U857 ( .A(n782), .B(n892), .Z(n907));
AN2 U858 ( .A(n769), .B(n751), .Z(n906));
AN2 U859 ( .A(po5), .B(n908), .Z(n904));
OR2 U860 ( .A(n909), .B(n772), .Z(n889));
AN2 U861 ( .A(n910), .B(n911), .Z(n909));
OR2 U862 ( .A(n912), .B(n795), .Z(n911));
OR2 U863 ( .A(n782), .B(n770), .Z(n910));
OR2 U864 ( .A(n827), .B(n913), .Z(n886));
OR2 U865 ( .A(n914), .B(n772), .Z(n913));
OR2 U866 ( .A(n915), .B(n916), .Z(n914));
AN2 U867 ( .A(n912), .B(n795), .Z(n916));
IV2 U868 ( .A(n770), .Z(n912));
AN2 U869 ( .A(n782), .B(n770), .Z(n915));
OR2 U870 ( .A(n917), .B(n918), .Z(n770));
AN2 U871 ( .A(n919), .B(n920), .Z(n917));
IV2 U872 ( .A(n795), .Z(n782));
OR2 U873 ( .A(n921), .B(n922), .Z(n787));
AN2 U874 ( .A(n923), .B(n824), .Z(n922));
AN2 U875 ( .A(n924), .B(n925), .Z(n923));
OR2 U876 ( .A(n926), .B(n927), .Z(n925));
AN2 U877 ( .A(pi11), .B(pi03), .Z(n926));
AN2 U878 ( .A(pi07), .B(n928), .Z(n921));
OR2 U879 ( .A(n929), .B(n930), .Z(n928));
AN2 U880 ( .A(n931), .B(n804), .Z(n929));
OR2 U881 ( .A(n932), .B(n933), .Z(n931));
AN2 U882 ( .A(n854), .B(n795), .Z(n933));
AN2 U883 ( .A(n934), .B(n827), .Z(n932));
OR2 U884 ( .A(n935), .B(n936), .Z(n785));
OR2 U885 ( .A(n937), .B(n938), .Z(n936));
AN2 U886 ( .A(n939), .B(n940), .Z(n938));
OR2 U887 ( .A(n941), .B(n942), .Z(n940));
OR2 U888 ( .A(n769), .B(n943), .Z(n942));
AN2 U889 ( .A(n874), .B(n944), .Z(n943));
AN2 U890 ( .A(n795), .B(pi03), .Z(n769));
OR2 U891 ( .A(n945), .B(n946), .Z(n795));
OR2 U892 ( .A(n947), .B(n948), .Z(n946));
AN2 U893 ( .A(n949), .B(n824), .Z(n948));
AN2 U894 ( .A(n950), .B(n765), .Z(n947));
IV2 U895 ( .A(n874), .Z(n765));
OR2 U896 ( .A(n951), .B(n952), .Z(n945));
OR2 U897 ( .A(n953), .B(n954), .Z(n952));
AN2 U898 ( .A(n955), .B(n827), .Z(n954));
OR2 U899 ( .A(n956), .B(n957), .Z(n955));
AN2 U900 ( .A(n958), .B(n784), .Z(n956));
AN2 U901 ( .A(pi07), .B(n959), .Z(n958));
AN2 U902 ( .A(po5), .B(n960), .Z(n953));
OR2 U903 ( .A(n961), .B(n962), .Z(n960));
AN2 U904 ( .A(n892), .B(n963), .Z(n962));
AN2 U905 ( .A(n964), .B(n965), .Z(n961));
AN2 U906 ( .A(pi13), .B(n966), .Z(n951));
OR2 U907 ( .A(n967), .B(n968), .Z(n966));
OR2 U908 ( .A(n969), .B(n970), .Z(n968));
AN2 U909 ( .A(n971), .B(pi02), .Z(n970));
AN2 U910 ( .A(n972), .B(n973), .Z(n969));
AN2 U911 ( .A(n974), .B(n975), .Z(n972));
OR2 U912 ( .A(n874), .B(n959), .Z(n975));
AN2 U913 ( .A(n827), .B(n824), .Z(n874));
IV2 U914 ( .A(pi03), .Z(n827));
OR2 U915 ( .A(n964), .B(n976), .Z(n974));
AN2 U916 ( .A(pi03), .B(n824), .Z(n976));
IV2 U917 ( .A(pi07), .Z(n824));
IV2 U918 ( .A(n959), .Z(n964));
OR2 U919 ( .A(n977), .B(n978), .Z(n959));
AN2 U920 ( .A(n979), .B(pi02), .Z(n978));
AN2 U921 ( .A(n980), .B(n717), .Z(n977));
OR2 U922 ( .A(n979), .B(pi02), .Z(n980));
AN2 U923 ( .A(n981), .B(po5), .Z(n967));
AN2 U924 ( .A(po5), .B(n982), .Z(n941));
AN2 U925 ( .A(pi03), .B(pi07), .Z(po5));
AN2 U926 ( .A(n983), .B(pi03), .Z(n935));
OR2 U927 ( .A(n984), .B(n985), .Z(po2));
OR2 U928 ( .A(n986), .B(n987), .Z(n985));
OR2 U929 ( .A(n988), .B(n989), .Z(n987));
OR2 U930 ( .A(n990), .B(n991), .Z(n989));
AN2 U931 ( .A(n793), .B(n992), .Z(n991));
AN2 U932 ( .A(n794), .B(n993), .Z(n990));
OR2 U933 ( .A(n994), .B(n995), .Z(n988));
AN2 U934 ( .A(n777), .B(n801), .Z(n995));
IV2 U935 ( .A(n800), .Z(n777));
AN2 U936 ( .A(n776), .B(n800), .Z(n994));
OR2 U937 ( .A(n996), .B(n804), .Z(n800));
AN2 U938 ( .A(n997), .B(n998), .Z(n996));
AN2 U939 ( .A(n999), .B(n1000), .Z(n998));
AN2 U940 ( .A(n1001), .B(n1002), .Z(n1000));
OR2 U941 ( .A(n1003), .B(n817), .Z(n1002));
AN2 U942 ( .A(n1004), .B(n836), .Z(n1003));
OR2 U943 ( .A(pi00), .B(n1005), .Z(n836));
OR2 U944 ( .A(pi02), .B(pi01), .Z(n1005));
AN2 U945 ( .A(n1006), .B(n1007), .Z(n1004));
OR2 U946 ( .A(pi11), .B(n1008), .Z(n1007));
AN2 U947 ( .A(n1009), .B(n821), .Z(n1008));
OR2 U948 ( .A(n898), .B(n1010), .Z(n821));
OR2 U949 ( .A(n1011), .B(n851), .Z(n1009));
AN2 U950 ( .A(n1012), .B(n1013), .Z(n1011));
OR2 U951 ( .A(n738), .B(n1014), .Z(n1006));
OR2 U952 ( .A(n1015), .B(n1016), .Z(n1014));
AN2 U953 ( .A(n713), .B(n1017), .Z(n1015));
OR2 U954 ( .A(n1018), .B(n1019), .Z(n1001));
OR2 U955 ( .A(n744), .B(n1020), .Z(n1019));
OR2 U956 ( .A(n1021), .B(n1022), .Z(n1018));
AN2 U957 ( .A(n717), .B(n1023), .Z(n1022));
AN2 U958 ( .A(n863), .B(n1024), .Z(n1021));
OR2 U959 ( .A(n1025), .B(n1026), .Z(n1024));
OR2 U960 ( .A(n992), .B(n852), .Z(n1026));
IV2 U961 ( .A(n1027), .Z(n1025));
OR2 U962 ( .A(n1028), .B(n1027), .Z(n863));
OR2 U963 ( .A(n1029), .B(n1030), .Z(n1027));
AN2 U964 ( .A(n1031), .B(n1032), .Z(n1029));
AN2 U965 ( .A(n1033), .B(n993), .Z(n1028));
AN2 U966 ( .A(n885), .B(n1034), .Z(n999));
OR2 U967 ( .A(n825), .B(n1035), .Z(n1034));
OR2 U968 ( .A(n1036), .B(n1037), .Z(n1035));
AN2 U969 ( .A(n1038), .B(n1039), .Z(n1037));
IV2 U970 ( .A(n724), .Z(n1039));
OR2 U971 ( .A(n877), .B(n738), .Z(n1038));
IV2 U972 ( .A(n876), .Z(n1036));
OR2 U973 ( .A(n1040), .B(n884), .Z(n885));
OR2 U974 ( .A(n1041), .B(n1042), .Z(n884));
OR2 U975 ( .A(n993), .B(n1032), .Z(n1042));
AN2 U976 ( .A(n1043), .B(n1044), .Z(n997));
AN2 U977 ( .A(n1045), .B(n1046), .Z(n1044));
OR2 U978 ( .A(pi02), .B(n1047), .Z(n1046));
AN2 U979 ( .A(n1048), .B(n1049), .Z(n1047));
OR2 U980 ( .A(n876), .B(n1050), .Z(n1049));
OR2 U981 ( .A(n717), .B(n825), .Z(n1050));
AN2 U982 ( .A(n1051), .B(n1052), .Z(n1048));
OR2 U983 ( .A(n1053), .B(n1054), .Z(n1052));
OR2 U984 ( .A(n1055), .B(n772), .Z(n1051));
AN2 U985 ( .A(n1056), .B(n1057), .Z(n1055));
OR2 U986 ( .A(n1058), .B(n993), .Z(n1057));
OR2 U987 ( .A(n992), .B(n919), .Z(n1056));
OR2 U988 ( .A(n1059), .B(n1016), .Z(n1045));
AN2 U989 ( .A(n1060), .B(n1061), .Z(n1059));
AN2 U990 ( .A(n1062), .B(n1063), .Z(n1061));
OR2 U991 ( .A(n876), .B(n1064), .Z(n1062));
OR2 U992 ( .A(pi06), .B(n825), .Z(n1064));
OR2 U993 ( .A(n1065), .B(n725), .Z(n876));
AN2 U994 ( .A(n718), .B(n1066), .Z(n1065));
AN2 U995 ( .A(n1067), .B(n1068), .Z(n1060));
OR2 U996 ( .A(n772), .B(n1069), .Z(n1068));
OR2 U997 ( .A(n1070), .B(n1071), .Z(n1069));
AN2 U998 ( .A(n1058), .B(n993), .Z(n1071));
IV2 U999 ( .A(n919), .Z(n1058));
AN2 U1000 ( .A(n992), .B(n919), .Z(n1070));
OR2 U1001 ( .A(n1072), .B(n1073), .Z(n919));
AN2 U1002 ( .A(n1074), .B(n1075), .Z(n1072));
OR2 U1003 ( .A(n1054), .B(n1076), .Z(n1067));
IV2 U1004 ( .A(n1053), .Z(n1076));
AN2 U1005 ( .A(n1077), .B(n1078), .Z(n1053));
OR2 U1006 ( .A(n897), .B(n851), .Z(n1078));
IV2 U1007 ( .A(n1079), .Z(n1077));
AN2 U1008 ( .A(n851), .B(n897), .Z(n1079));
OR2 U1009 ( .A(n1080), .B(n1081), .Z(n897));
AN2 U1010 ( .A(pi01), .B(n1082), .Z(n1080));
AN2 U1011 ( .A(n1083), .B(n1084), .Z(n1043));
OR2 U1012 ( .A(pi10), .B(n1085), .Z(n1084));
OR2 U1013 ( .A(n1086), .B(n1087), .Z(n1085));
AN2 U1014 ( .A(n1088), .B(n1089), .Z(n1087));
AN2 U1015 ( .A(n852), .B(n898), .Z(n1088));
IV2 U1016 ( .A(n1033), .Z(n852));
AN2 U1017 ( .A(n1090), .B(n853), .Z(n1086));
IV2 U1018 ( .A(n1089), .Z(n853));
AN2 U1019 ( .A(n1091), .B(n1082), .Z(n1089));
OR2 U1020 ( .A(n1031), .B(n1092), .Z(n1091));
OR2 U1021 ( .A(n851), .B(n1033), .Z(n1090));
OR2 U1022 ( .A(n1093), .B(n1094), .Z(n1033));
AN2 U1023 ( .A(n868), .B(n724), .Z(n1094));
AN2 U1024 ( .A(n851), .B(n869), .Z(n1093));
IV2 U1025 ( .A(n898), .Z(n851));
OR2 U1026 ( .A(n1095), .B(n1096), .Z(n898));
AN2 U1027 ( .A(n901), .B(n920), .Z(n1096));
OR2 U1028 ( .A(pi02), .B(n993), .Z(n920));
AN2 U1029 ( .A(n902), .B(n1097), .Z(n1095));
OR2 U1030 ( .A(n1098), .B(n1099), .Z(n1097));
OR2 U1031 ( .A(n1100), .B(n1101), .Z(n1099));
AN2 U1032 ( .A(n992), .B(n892), .Z(n1101));
AN2 U1033 ( .A(n918), .B(n751), .Z(n1100));
AN2 U1034 ( .A(n908), .B(n724), .Z(n1098));
OR2 U1035 ( .A(n1102), .B(n992), .Z(n1083));
IV2 U1036 ( .A(n993), .Z(n992));
AN2 U1037 ( .A(n1103), .B(n1104), .Z(n1102));
OR2 U1038 ( .A(n883), .B(n1105), .Z(n1104));
IV2 U1039 ( .A(n1106), .Z(n883));
IV2 U1040 ( .A(n801), .Z(n776));
OR2 U1041 ( .A(n1107), .B(n1108), .Z(n801));
OR2 U1042 ( .A(pi12), .B(n1109), .Z(n1108));
OR2 U1043 ( .A(n1110), .B(n1111), .Z(n986));
AN2 U1044 ( .A(n1112), .B(n717), .Z(n1111));
AN2 U1045 ( .A(n924), .B(n1113), .Z(n1112));
OR2 U1046 ( .A(n1114), .B(n927), .Z(n1113));
AN2 U1047 ( .A(pi11), .B(pi02), .Z(n1114));
AN2 U1048 ( .A(pi06), .B(n1115), .Z(n1110));
OR2 U1049 ( .A(n1116), .B(n930), .Z(n1115));
AN2 U1050 ( .A(n1117), .B(n804), .Z(n1116));
OR2 U1051 ( .A(n1118), .B(n1119), .Z(n1117));
AN2 U1052 ( .A(n854), .B(n993), .Z(n1119));
AN2 U1053 ( .A(n934), .B(n1016), .Z(n1118));
OR2 U1054 ( .A(n1120), .B(n1121), .Z(n984));
OR2 U1055 ( .A(n937), .B(n1122), .Z(n1121));
AN2 U1056 ( .A(n939), .B(n1123), .Z(n1122));
OR2 U1057 ( .A(n1124), .B(n1125), .Z(n1123));
OR2 U1058 ( .A(n918), .B(n1126), .Z(n1125));
AN2 U1059 ( .A(n724), .B(n982), .Z(n1126));
AN2 U1060 ( .A(n993), .B(pi02), .Z(n918));
OR2 U1061 ( .A(n1127), .B(n1128), .Z(n993));
OR2 U1062 ( .A(n1129), .B(n1130), .Z(n1128));
AN2 U1063 ( .A(n949), .B(n717), .Z(n1130));
AN2 U1064 ( .A(n950), .B(n877), .Z(n1129));
IV2 U1065 ( .A(n727), .Z(n877));
OR2 U1066 ( .A(n1131), .B(n1132), .Z(n1127));
OR2 U1067 ( .A(n1133), .B(n1134), .Z(n1132));
AN2 U1068 ( .A(n1135), .B(n1016), .Z(n1134));
OR2 U1069 ( .A(n1136), .B(n957), .Z(n1135));
AN2 U1070 ( .A(n1137), .B(n979), .Z(n1136));
AN2 U1071 ( .A(n784), .B(pi06), .Z(n1137));
AN2 U1072 ( .A(n724), .B(n1138), .Z(n1133));
OR2 U1073 ( .A(n1139), .B(n1140), .Z(n1138));
AN2 U1074 ( .A(n965), .B(n1141), .Z(n1139));
AN2 U1075 ( .A(pi02), .B(pi06), .Z(n724));
AN2 U1076 ( .A(pi13), .B(n1142), .Z(n1131));
OR2 U1077 ( .A(n1143), .B(n1144), .Z(n1142));
AN2 U1078 ( .A(n971), .B(pi01), .Z(n1144));
AN2 U1079 ( .A(n1145), .B(n973), .Z(n1143));
AN2 U1080 ( .A(n1146), .B(n1147), .Z(n1145));
OR2 U1081 ( .A(n727), .B(n979), .Z(n1147));
IV2 U1082 ( .A(n1141), .Z(n979));
OR2 U1083 ( .A(n1148), .B(n1141), .Z(n1146));
OR2 U1084 ( .A(n1149), .B(n1150), .Z(n1141));
AN2 U1085 ( .A(n1151), .B(n1017), .Z(n1150));
AN2 U1086 ( .A(pi05), .B(n1152), .Z(n1149));
OR2 U1087 ( .A(n1151), .B(n1017), .Z(n1152));
AN2 U1088 ( .A(pi02), .B(n717), .Z(n1148));
AN2 U1089 ( .A(n944), .B(n727), .Z(n1124));
AN2 U1090 ( .A(n1016), .B(n717), .Z(n727));
IV2 U1091 ( .A(pi06), .Z(n717));
IV2 U1092 ( .A(pi02), .Z(n1016));
AN2 U1093 ( .A(n983), .B(pi02), .Z(n1120));
OR2 U1094 ( .A(n1153), .B(n1154), .Z(po1));
OR2 U1095 ( .A(n1155), .B(n1156), .Z(n1154));
OR2 U1096 ( .A(n1157), .B(n1158), .Z(n1156));
OR2 U1097 ( .A(n1159), .B(n1160), .Z(n1158));
AN2 U1098 ( .A(n793), .B(n1105), .Z(n1160));
AN2 U1099 ( .A(n794), .B(n1032), .Z(n1159));
OR2 U1100 ( .A(n1161), .B(n1162), .Z(n1157));
AN2 U1101 ( .A(n1163), .B(n1107), .Z(n1162));
IV2 U1102 ( .A(n1164), .Z(n1161));
OR2 U1103 ( .A(n1107), .B(n1163), .Z(n1164));
AN2 U1104 ( .A(n1165), .B(n1166), .Z(n1163));
OR2 U1105 ( .A(n1167), .B(n804), .Z(n1107));
AN2 U1106 ( .A(n1168), .B(n1169), .Z(n1167));
AN2 U1107 ( .A(n1170), .B(n1171), .Z(n1169));
OR2 U1108 ( .A(n817), .B(n1172), .Z(n1171));
OR2 U1109 ( .A(pi11), .B(n1173), .Z(n1172));
AN2 U1110 ( .A(n1010), .B(n1174), .Z(n1173));
OR2 U1111 ( .A(n1012), .B(n1013), .Z(n1174));
OR2 U1112 ( .A(n1175), .B(n1082), .Z(n1010));
AN2 U1113 ( .A(n1176), .B(n1177), .Z(n1170));
OR2 U1114 ( .A(pi10), .B(n1178), .Z(n1177));
OR2 U1115 ( .A(n1179), .B(n1180), .Z(n1178));
AN2 U1116 ( .A(n1181), .B(n1031), .Z(n1180));
IV2 U1117 ( .A(n1182), .Z(n1179));
OR2 U1118 ( .A(n1181), .B(n1031), .Z(n1182));
OR2 U1119 ( .A(n1183), .B(n1184), .Z(n1181));
AN2 U1120 ( .A(n1185), .B(n1082), .Z(n1184));
AN2 U1121 ( .A(n1012), .B(n1092), .Z(n1183));
OR2 U1122 ( .A(n825), .B(n1186), .Z(n1176));
OR2 U1123 ( .A(n1187), .B(n1188), .Z(n1186));
AN2 U1124 ( .A(n1189), .B(n1190), .Z(n1187));
IV2 U1125 ( .A(n725), .Z(n1190));
OR2 U1126 ( .A(n1066), .B(n738), .Z(n1189));
AN2 U1127 ( .A(n1191), .B(n1192), .Z(n1168));
AN2 U1128 ( .A(n1193), .B(n1194), .Z(n1192));
OR2 U1129 ( .A(n1195), .B(n1017), .Z(n1194));
AN2 U1130 ( .A(n1196), .B(n1197), .Z(n1195));
AN2 U1131 ( .A(n1198), .B(n1199), .Z(n1197));
OR2 U1132 ( .A(pi05), .B(n1200), .Z(n1199));
AN2 U1133 ( .A(n1201), .B(n1063), .Z(n1198));
OR2 U1134 ( .A(n1202), .B(n772), .Z(n1201));
AN2 U1135 ( .A(n1203), .B(n1204), .Z(n1202));
OR2 U1136 ( .A(n1074), .B(n1032), .Z(n1204));
OR2 U1137 ( .A(n1105), .B(n1205), .Z(n1203));
AN2 U1138 ( .A(n1206), .B(n1207), .Z(n1196));
OR2 U1139 ( .A(n1208), .B(n1054), .Z(n1207));
AN2 U1140 ( .A(n1209), .B(n1210), .Z(n1208));
OR2 U1141 ( .A(n1081), .B(n1082), .Z(n1210));
OR2 U1142 ( .A(n1012), .B(n1211), .Z(n1209));
IV2 U1143 ( .A(n1081), .Z(n1211));
OR2 U1144 ( .A(n817), .B(n1212), .Z(n1206));
OR2 U1145 ( .A(n713), .B(n738), .Z(n1212));
OR2 U1146 ( .A(pi01), .B(n1213), .Z(n1193));
AN2 U1147 ( .A(n1214), .B(n1215), .Z(n1213));
AN2 U1148 ( .A(n1216), .B(n1217), .Z(n1215));
OR2 U1149 ( .A(n1054), .B(n1218), .Z(n1216));
OR2 U1150 ( .A(n1012), .B(n1081), .Z(n1218));
AN2 U1151 ( .A(pi00), .B(n1175), .Z(n1081));
OR2 U1152 ( .A(pi08), .B(n1020), .Z(n1054));
AN2 U1153 ( .A(n1219), .B(n1220), .Z(n1214));
OR2 U1154 ( .A(n772), .B(n1221), .Z(n1220));
OR2 U1155 ( .A(n1222), .B(n1223), .Z(n1221));
AN2 U1156 ( .A(n1074), .B(n1032), .Z(n1223));
AN2 U1157 ( .A(n1105), .B(n1205), .Z(n1222));
OR2 U1158 ( .A(n1224), .B(n738), .Z(n772));
AN2 U1159 ( .A(n1225), .B(n829), .Z(n1224));
OR2 U1160 ( .A(n751), .B(n1023), .Z(n1225));
OR2 U1161 ( .A(n716), .B(n1200), .Z(n1219));
OR2 U1162 ( .A(n718), .B(n825), .Z(n1200));
IV2 U1163 ( .A(n761), .Z(n825));
AN2 U1164 ( .A(n1226), .B(n1227), .Z(n1191));
OR2 U1165 ( .A(n1228), .B(n1229), .Z(n1227));
OR2 U1166 ( .A(n1020), .B(n1230), .Z(n1229));
OR2 U1167 ( .A(n1231), .B(n1232), .Z(n1230));
AN2 U1168 ( .A(n1233), .B(n1234), .Z(n1232));
AN2 U1169 ( .A(n1235), .B(n1031), .Z(n1233));
OR2 U1170 ( .A(n1030), .B(n1032), .Z(n1235));
AN2 U1171 ( .A(n1092), .B(n1041), .Z(n1030));
IV2 U1172 ( .A(n1236), .Z(n1231));
OR2 U1173 ( .A(n1234), .B(n1031), .Z(n1236));
OR2 U1174 ( .A(n1237), .B(n1238), .Z(n1031));
AN2 U1175 ( .A(n868), .B(n725), .Z(n1238));
AN2 U1176 ( .A(n1012), .B(n869), .Z(n1237));
IV2 U1177 ( .A(n1082), .Z(n1012));
OR2 U1178 ( .A(n1239), .B(n1240), .Z(n1082));
AN2 U1179 ( .A(n901), .B(n1075), .Z(n1240));
OR2 U1180 ( .A(pi01), .B(n1032), .Z(n1075));
AN2 U1181 ( .A(n902), .B(n1241), .Z(n1239));
OR2 U1182 ( .A(n1242), .B(n1243), .Z(n1241));
OR2 U1183 ( .A(n1244), .B(n1245), .Z(n1243));
AN2 U1184 ( .A(n1105), .B(n892), .Z(n1245));
AN2 U1185 ( .A(n1073), .B(n751), .Z(n1244));
AN2 U1186 ( .A(n908), .B(n725), .Z(n1242));
OR2 U1187 ( .A(n1185), .B(n1246), .Z(n1234));
OR2 U1188 ( .A(n1247), .B(n1105), .Z(n1246));
IV2 U1189 ( .A(n1248), .Z(n1020));
OR2 U1190 ( .A(n1249), .B(n744), .Z(n1228));
AN2 U1191 ( .A(n716), .B(n1023), .Z(n1249));
AN2 U1192 ( .A(n1250), .B(n1251), .Z(n1226));
OR2 U1193 ( .A(n1105), .B(n1103), .Z(n1251));
IV2 U1194 ( .A(n1252), .Z(n1103));
OR2 U1195 ( .A(n1253), .B(n1254), .Z(n1252));
AN2 U1196 ( .A(n1106), .B(n1041), .Z(n1254));
OR2 U1197 ( .A(n1255), .B(n780), .Z(n1106));
AN2 U1198 ( .A(n973), .B(n738), .Z(n1255));
AN2 U1199 ( .A(n854), .B(n738), .Z(n1253));
IV2 U1200 ( .A(n1032), .Z(n1105));
OR2 U1201 ( .A(n1032), .B(n1256), .Z(n1250));
OR2 U1202 ( .A(n1040), .B(n1041), .Z(n1256));
IV2 U1203 ( .A(n1257), .Z(n1040));
OR2 U1204 ( .A(n1258), .B(n1259), .Z(n1155));
AN2 U1205 ( .A(n1260), .B(n716), .Z(n1259));
AN2 U1206 ( .A(n924), .B(n1261), .Z(n1260));
OR2 U1207 ( .A(n1262), .B(n927), .Z(n1261));
AN2 U1208 ( .A(pi11), .B(pi01), .Z(n1262));
AN2 U1209 ( .A(pi05), .B(n1263), .Z(n1258));
OR2 U1210 ( .A(n1264), .B(n930), .Z(n1263));
AN2 U1211 ( .A(n1265), .B(n804), .Z(n1264));
OR2 U1212 ( .A(n1266), .B(n1267), .Z(n1265));
AN2 U1213 ( .A(n854), .B(n1032), .Z(n1267));
AN2 U1214 ( .A(n934), .B(n1017), .Z(n1266));
AN2 U1215 ( .A(pi11), .B(n761), .Z(n934));
OR2 U1216 ( .A(n1268), .B(n1269), .Z(n1153));
OR2 U1217 ( .A(n937), .B(n1270), .Z(n1269));
AN2 U1218 ( .A(n939), .B(n1271), .Z(n1270));
OR2 U1219 ( .A(n1272), .B(n1273), .Z(n1271));
OR2 U1220 ( .A(n1073), .B(n1274), .Z(n1273));
AN2 U1221 ( .A(n725), .B(n982), .Z(n1274));
AN2 U1222 ( .A(n1032), .B(pi01), .Z(n1073));
OR2 U1223 ( .A(n1275), .B(n1276), .Z(n1032));
OR2 U1224 ( .A(n1277), .B(n1278), .Z(n1276));
AN2 U1225 ( .A(n949), .B(n716), .Z(n1278));
AN2 U1226 ( .A(n950), .B(n1066), .Z(n1277));
IV2 U1227 ( .A(n723), .Z(n1066));
OR2 U1228 ( .A(n1279), .B(n1280), .Z(n1275));
OR2 U1229 ( .A(n1281), .B(n1282), .Z(n1280));
AN2 U1230 ( .A(n1283), .B(n1017), .Z(n1282));
OR2 U1231 ( .A(n1284), .B(n957), .Z(n1283));
AN2 U1232 ( .A(n1285), .B(n784), .Z(n1284));
AN2 U1233 ( .A(pi05), .B(n1286), .Z(n1285));
AN2 U1234 ( .A(n725), .B(n1287), .Z(n1281));
OR2 U1235 ( .A(n1288), .B(n1140), .Z(n1287));
AN2 U1236 ( .A(n965), .B(n1151), .Z(n1288));
AN2 U1237 ( .A(n744), .B(n902), .Z(n965));
AN2 U1238 ( .A(pi01), .B(pi05), .Z(n725));
AN2 U1239 ( .A(pi13), .B(n1289), .Z(n1279));
OR2 U1240 ( .A(n1290), .B(n1291), .Z(n1289));
AN2 U1241 ( .A(n971), .B(pi00), .Z(n1291));
AN2 U1242 ( .A(n892), .B(n1292), .Z(n971));
AN2 U1243 ( .A(pi10), .B(pi11), .Z(n1292));
AN2 U1244 ( .A(n1293), .B(n973), .Z(n1290));
AN2 U1245 ( .A(n1294), .B(n1295), .Z(n1293));
OR2 U1246 ( .A(n723), .B(n1286), .Z(n1295));
IV2 U1247 ( .A(n1151), .Z(n1286));
OR2 U1248 ( .A(n1151), .B(n1296), .Z(n1294));
AN2 U1249 ( .A(pi01), .B(n716), .Z(n1296));
AN2 U1250 ( .A(n944), .B(n723), .Z(n1272));
AN2 U1251 ( .A(n1017), .B(n716), .Z(n723));
IV2 U1252 ( .A(pi05), .Z(n716));
IV2 U1253 ( .A(pi01), .Z(n1017));
AN2 U1254 ( .A(n983), .B(pi01), .Z(n1268));
AN2 U1255 ( .A(pi11), .B(n1297), .Z(n983));
OR2 U1256 ( .A(n1298), .B(n1299), .Z(po0));
OR2 U1257 ( .A(n1300), .B(n1301), .Z(n1299));
OR2 U1258 ( .A(n1302), .B(n1303), .Z(n1301));
OR2 U1259 ( .A(n1304), .B(n1305), .Z(n1303));
AN2 U1260 ( .A(n793), .B(n1247), .Z(n1305));
AN2 U1261 ( .A(n924), .B(n1306), .Z(n793));
IV2 U1262 ( .A(n1307), .Z(n1306));
OR2 U1263 ( .A(n854), .B(n1308), .Z(n1307));
AN2 U1264 ( .A(pi08), .B(n1063), .Z(n1308));
IV2 U1265 ( .A(n1309), .Z(n1063));
AN2 U1266 ( .A(n794), .B(n1041), .Z(n1304));
AN2 U1267 ( .A(n1310), .B(n924), .Z(n794));
OR2 U1268 ( .A(pi11), .B(n854), .Z(n1310));
AN2 U1269 ( .A(pi11), .B(n1311), .Z(n1302));
OR2 U1270 ( .A(n1312), .B(n1313), .Z(n1311));
OR2 U1271 ( .A(n1314), .B(n1315), .Z(n1313));
AN2 U1272 ( .A(n924), .B(n1316), .Z(n1315));
AN2 U1273 ( .A(n1317), .B(n761), .Z(n1314));
AN2 U1274 ( .A(n1023), .B(n908), .Z(n761));
AN2 U1275 ( .A(n1151), .B(n804), .Z(n1317));
AN2 U1276 ( .A(n1297), .B(pi00), .Z(n1312));
AN2 U1277 ( .A(n804), .B(n1318), .Z(n1297));
OR2 U1278 ( .A(pi10), .B(n892), .Z(n1318));
OR2 U1279 ( .A(n1319), .B(n1320), .Z(n1300));
AN2 U1280 ( .A(n1321), .B(n709), .Z(n1320));
AN2 U1281 ( .A(n927), .B(n924), .Z(n1321));
AN2 U1282 ( .A(pi04), .B(n1322), .Z(n1319));
OR2 U1283 ( .A(n1323), .B(n930), .Z(n1322));
AN2 U1284 ( .A(n939), .B(n1324), .Z(n930));
AN2 U1285 ( .A(n744), .B(pi11), .Z(n1324));
AN2 U1286 ( .A(n957), .B(n1041), .Z(n1323));
OR2 U1287 ( .A(n1325), .B(n1326), .Z(n1298));
OR2 U1288 ( .A(n937), .B(n1327), .Z(n1326));
AN2 U1289 ( .A(pi13), .B(n1328), .Z(n1327));
OR2 U1290 ( .A(n1329), .B(n1330), .Z(n1328));
AN2 U1291 ( .A(n1109), .B(n1166), .Z(n1330));
IV2 U1292 ( .A(pi12), .Z(n1166));
IV2 U1293 ( .A(n1165), .Z(n1109));
AN2 U1294 ( .A(pi12), .B(n1165), .Z(n1329));
OR2 U1295 ( .A(n1331), .B(n1332), .Z(n1165));
AN2 U1296 ( .A(pi13), .B(n1333), .Z(n1332));
OR2 U1297 ( .A(n1334), .B(n1335), .Z(n1333));
OR2 U1298 ( .A(n1336), .B(n1337), .Z(n1335));
AN2 U1299 ( .A(n1247), .B(n1257), .Z(n1337));
OR2 U1300 ( .A(n1338), .B(n780), .Z(n1257));
AN2 U1301 ( .A(n1023), .B(n751), .Z(n780));
AN2 U1302 ( .A(n944), .B(pi09), .Z(n1338));
AN2 U1303 ( .A(pi11), .B(n1339), .Z(n1336));
OR2 U1304 ( .A(n1340), .B(n1341), .Z(n1339));
OR2 U1305 ( .A(n1342), .B(n1343), .Z(n1341));
AN2 U1306 ( .A(n1344), .B(pi00), .Z(n1343));
AN2 U1307 ( .A(n1345), .B(n1247), .Z(n1344));
AN2 U1308 ( .A(pi10), .B(n1346), .Z(n1345));
AN2 U1309 ( .A(n1041), .B(n713), .Z(n1342));
IV2 U1310 ( .A(n1217), .Z(n1340));
OR2 U1311 ( .A(pi00), .B(n817), .Z(n1217));
OR2 U1312 ( .A(n1023), .B(n1346), .Z(n817));
OR2 U1313 ( .A(n1347), .B(n1348), .Z(n1334));
OR2 U1314 ( .A(n1349), .B(n1350), .Z(n1348));
AN2 U1315 ( .A(n1316), .B(n1023), .Z(n1350));
AN2 U1316 ( .A(n854), .B(n1351), .Z(n1349));
OR2 U1317 ( .A(n1352), .B(n1353), .Z(n1351));
AN2 U1318 ( .A(pi00), .B(n738), .Z(n1353));
AN2 U1319 ( .A(pi09), .B(n1041), .Z(n1352));
AN2 U1320 ( .A(n1248), .B(n1354), .Z(n1347));
OR2 U1321 ( .A(n1355), .B(n1356), .Z(n1354));
OR2 U1322 ( .A(n1357), .B(n1358), .Z(n1356));
AN2 U1323 ( .A(n1185), .B(n1041), .Z(n1358));
IV2 U1324 ( .A(n1092), .Z(n1185));
AN2 U1325 ( .A(n1247), .B(n1092), .Z(n1357));
OR2 U1326 ( .A(n1359), .B(n1360), .Z(n1092));
AN2 U1327 ( .A(n868), .B(n718), .Z(n1360));
AN2 U1328 ( .A(n1023), .B(n901), .Z(n868));
AN2 U1329 ( .A(n973), .B(pi11), .Z(n901));
AN2 U1330 ( .A(n869), .B(n1013), .Z(n1359));
AN2 U1331 ( .A(n1361), .B(n927), .Z(n869));
AN2 U1332 ( .A(n963), .B(pi08), .Z(n927));
IV2 U1333 ( .A(n1041), .Z(n1247));
AN2 U1334 ( .A(n1175), .B(n713), .Z(n1355));
IV2 U1335 ( .A(n1013), .Z(n1175));
AN2 U1336 ( .A(n1361), .B(n738), .Z(n1248));
AN2 U1337 ( .A(n1362), .B(n751), .Z(n1331));
AN2 U1338 ( .A(n902), .B(n1013), .Z(n1362));
OR2 U1339 ( .A(n1363), .B(n1364), .Z(n1013));
IV2 U1340 ( .A(n902), .Z(n1364));
AN2 U1341 ( .A(n1365), .B(n1366), .Z(n1363));
OR2 U1342 ( .A(n1188), .B(n857), .Z(n1366));
IV2 U1343 ( .A(n908), .Z(n857));
IV2 U1344 ( .A(n718), .Z(n1188));
AN2 U1345 ( .A(n1367), .B(n1368), .Z(n1365));
OR2 U1346 ( .A(n1346), .B(n1205), .Z(n1368));
IV2 U1347 ( .A(n1074), .Z(n1205));
IV2 U1348 ( .A(n751), .Z(n1346));
OR2 U1349 ( .A(n829), .B(n1041), .Z(n1367));
IV2 U1350 ( .A(n892), .Z(n829));
AN2 U1351 ( .A(n1309), .B(n1369), .Z(n937));
AN2 U1352 ( .A(pi13), .B(n751), .Z(n1369));
AN2 U1353 ( .A(n939), .B(n1370), .Z(n1325));
OR2 U1354 ( .A(n1371), .B(n1372), .Z(n1370));
OR2 U1355 ( .A(n1074), .B(n1373), .Z(n1372));
AN2 U1356 ( .A(n1374), .B(n944), .Z(n1373));
AN2 U1357 ( .A(n713), .B(n709), .Z(n1374));
AN2 U1358 ( .A(n1041), .B(pi00), .Z(n1074));
OR2 U1359 ( .A(n1375), .B(n1376), .Z(n1041));
OR2 U1360 ( .A(n1377), .B(n1378), .Z(n1376));
OR2 U1361 ( .A(n1379), .B(n1380), .Z(n1378));
AN2 U1362 ( .A(n949), .B(n709), .Z(n1380));
OR2 U1363 ( .A(n1381), .B(n1382), .Z(n949));
OR2 U1364 ( .A(n1383), .B(n1384), .Z(n1382));
AN2 U1365 ( .A(n751), .B(n963), .Z(n1384));
AN2 U1366 ( .A(n1385), .B(n860), .Z(n1383));
IV2 U1367 ( .A(n963), .Z(n860));
AN2 U1368 ( .A(n1386), .B(n924), .Z(n1381));
AN2 U1369 ( .A(n804), .B(n1361), .Z(n924));
AN2 U1370 ( .A(pi08), .B(pi10), .Z(n1386));
AN2 U1371 ( .A(n718), .B(n1140), .Z(n1379));
OR2 U1372 ( .A(n1387), .B(n981), .Z(n1140));
AN2 U1373 ( .A(pi11), .B(n1388), .Z(n981));
AN2 U1374 ( .A(n1023), .B(n1389), .Z(n1388));
OR2 U1375 ( .A(n751), .B(n892), .Z(n1389));
AN2 U1376 ( .A(n744), .B(n1361), .Z(n892));
AN2 U1377 ( .A(pi09), .B(pi08), .Z(n751));
AN2 U1378 ( .A(n944), .B(n1361), .Z(n1387));
AN2 U1379 ( .A(n744), .B(n963), .Z(n944));
AN2 U1380 ( .A(n784), .B(n1151), .Z(n1377));
AN2 U1381 ( .A(n713), .B(pi04), .Z(n1151));
AN2 U1382 ( .A(n973), .B(n902), .Z(n784));
AN2 U1383 ( .A(n963), .B(pi13), .Z(n902));
AN2 U1384 ( .A(n738), .B(pi10), .Z(n963));
OR2 U1385 ( .A(n1390), .B(n1391), .Z(n1375));
OR2 U1386 ( .A(n1392), .B(n1393), .Z(n1391));
AN2 U1387 ( .A(n950), .B(n1394), .Z(n1393));
OR2 U1388 ( .A(pi00), .B(pi04), .Z(n1394));
AN2 U1389 ( .A(n1395), .B(n908), .Z(n950));
AN2 U1390 ( .A(n1361), .B(pi08), .Z(n908));
IV2 U1391 ( .A(pi09), .Z(n1361));
OR2 U1392 ( .A(pi13), .B(n1309), .Z(n1395));
AN2 U1393 ( .A(n1023), .B(n738), .Z(n1309));
IV2 U1394 ( .A(pi11), .Z(n738));
AN2 U1395 ( .A(n1385), .B(n1316), .Z(n1392));
AN2 U1396 ( .A(n709), .B(pi00), .Z(n1316));
IV2 U1397 ( .A(pi04), .Z(n709));
AN2 U1398 ( .A(n973), .B(pi13), .Z(n1385));
AN2 U1399 ( .A(n744), .B(pi09), .Z(n973));
AN2 U1400 ( .A(n957), .B(n713), .Z(n1390));
IV2 U1401 ( .A(pi00), .Z(n713));
AN2 U1402 ( .A(n804), .B(n854), .Z(n957));
AN2 U1403 ( .A(n744), .B(n1023), .Z(n854));
IV2 U1404 ( .A(pi10), .Z(n1023));
AN2 U1405 ( .A(n718), .B(n982), .Z(n1371));
OR2 U1406 ( .A(n1396), .B(pi11), .Z(n982));
AN2 U1407 ( .A(pi10), .B(n744), .Z(n1396));
IV2 U1408 ( .A(pi08), .Z(n744));
AN2 U1409 ( .A(pi00), .B(pi04), .Z(n718));
AN2 U1410 ( .A(n804), .B(pi09), .Z(n939));
IV2 U1411 ( .A(pi13), .Z(n804));
endmodule
module IV2(A, Z);
input A;
output Z;
assign Z = ~A;
endmodule
module AN2(A, B, Z);
input A, B;
output Z;
assign Z = A & B;
endmodule
module OR2(A, B, Z);
input A, B;
output Z;
assign Z = A | B;
endmodule

41
examples/smtbmc/glift/alu4.ys Normal file
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read_verilog alu4.v
techmap
flatten
select alu4_lev2
glift -create-instrumented-model
techmap
opt
rename alu4_lev2 uut
cd ..
delete [AIONX][NVXR]2
read_verilog alu4.v
techmap
flatten
select alu4_lev2
glift -create-precise-model
techmap
opt
rename alu4_lev2 spec
cd ..
delete [AIONX][NVXR]2
design -push-copy
miter -equiv spec uut miter
flatten
delete uut spec
techmap
opt
stat miter
qbfsat -O2 -write-solution alu4.soln -solver yices -timeout 3600 -nocleanup -assume-outputs -assume-negative-polarity miter
design -pop
stat
copy uut solved
qbfsat -specialize-from-file alu4.soln solved
opt solved
miter -equiv spec solved satmiter
flatten
sat -prove trigger 0 satmiter
delete satmiter
stat
shell

40
examples/smtbmc/glift/mux2.ys Normal file
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@ -0,0 +1,40 @@
logger -expect log "SAT proof finished - no model found: SUCCESS!" 1
logger -expect log "Number of cells:.*[\t ]12" 1
logger -expect log "Number of cells:.*[\t ]20" 1
logger -expect log "Problem is satisfiable with \\gate.__glift_weight = 11." 1
logger -expect log "Problem is NOT satisfiable with \\gate.__glift_weight <= 10." 1
logger -expect log "Wire \\gate.__glift_weight is minimized at 11." 1
logger -expect log "Specializing .* from file with .* = 1." 2
logger -expect log "Specializing .* from file with .* = 0." 4
read_verilog <<EOT
module mux2(a, b, s, y);
input a, b, s;
output y;
wire s_n = ~s;
wire t0 = s & a;
wire t1 = s_n & b;
assign y = t0 | t1;
endmodule
EOT
techmap
copy mux2 spec
copy mux2 uut
copy mux2 solved
delete mux2
glift -create-precise-model spec
glift -create-instrumented-model uut
glift -create-instrumented-model -no-cost-model solved
design -push-copy
miter -equiv spec uut qbfmiter
flatten
delete spec uut solved
qbfsat -assume-outputs -assume-negative-polarity -write-solution mux2.soln qbfmiter
design -pop
qbfsat -specialize-from-file mux2.soln solved
opt
miter -equiv spec solved proofmiter
flatten proofmiter
sat -prove trigger 0 proofmiter
delete proofmiter
stat solved spec

83
examples/smtbmc/glift/t481.v Executable file
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module t481_lev2(pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09,
pi10, pi11, pi12, pi13, pi14, pi15, po0);
input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09,
pi10, pi11, pi12, pi13, pi14, pi15;
output po0;
wire n46, n47, n48, n49, n50, n51, n52, n53, n54, n55,
n56, n57, n58, n59, n60, n61, n62, n63, n64, n65,
n66, n67, n68, n69, n70, n71, n72, n73, n74, n75,
n76, n77, n78, n79, n80, n81, n82, n83, n84, n85,
n86, n87, n88, n89, n90;
OR2 U47 ( .A(n46), .B(n47), .Z(po0));
OR2 U48 ( .A(n48), .B(n49), .Z(n47));
AN2 U49 ( .A(n50), .B(n51), .Z(n49));
OR2 U50 ( .A(n52), .B(n53), .Z(n51));
AN2 U51 ( .A(n54), .B(n55), .Z(n53));
AN2 U52 ( .A(n56), .B(n57), .Z(n54));
AN2 U53 ( .A(n58), .B(n59), .Z(n52));
AN2 U54 ( .A(n60), .B(n61), .Z(n48));
IV2 U55 ( .A(n50), .Z(n61));
AN2 U56 ( .A(n62), .B(pi15), .Z(n50));
IV2 U57 ( .A(pi14), .Z(n62));
OR2 U58 ( .A(n63), .B(n64), .Z(n60));
AN2 U59 ( .A(n65), .B(n55), .Z(n64));
IV2 U60 ( .A(n59), .Z(n55));
AN2 U61 ( .A(n57), .B(n58), .Z(n65));
IV2 U62 ( .A(n56), .Z(n58));
AN2 U63 ( .A(n56), .B(n59), .Z(n63));
AN2 U64 ( .A(n66), .B(pi00), .Z(n56));
IV2 U65 ( .A(pi01), .Z(n66));
AN2 U66 ( .A(n67), .B(n59), .Z(n46));
OR2 U67 ( .A(n68), .B(n69), .Z(n59));
OR2 U68 ( .A(n70), .B(n71), .Z(n69));
AN2 U69 ( .A(n72), .B(n73), .Z(n71));
IV2 U70 ( .A(n74), .Z(n70));
OR2 U71 ( .A(n73), .B(n72), .Z(n74));
AN2 U72 ( .A(n75), .B(pi12), .Z(n72));
IV2 U73 ( .A(pi13), .Z(n75));
OR2 U74 ( .A(pi10), .B(n76), .Z(n73));
IV2 U75 ( .A(pi11), .Z(n76));
AN2 U76 ( .A(n77), .B(n78), .Z(n68));
OR2 U77 ( .A(n79), .B(n80), .Z(n78));
IV2 U78 ( .A(n81), .Z(n77));
AN2 U79 ( .A(n80), .B(n79), .Z(n81));
AN2 U80 ( .A(n82), .B(pi08), .Z(n79));
IV2 U81 ( .A(pi09), .Z(n82));
OR2 U82 ( .A(pi06), .B(n83), .Z(n80));
IV2 U83 ( .A(pi07), .Z(n83));
IV2 U84 ( .A(n57), .Z(n67));
OR2 U85 ( .A(n84), .B(n85), .Z(n57));
AN2 U86 ( .A(n86), .B(n87), .Z(n85));
IV2 U87 ( .A(n88), .Z(n84));
OR2 U88 ( .A(n87), .B(n86), .Z(n88));
AN2 U89 ( .A(n89), .B(pi04), .Z(n86));
IV2 U90 ( .A(pi05), .Z(n89));
OR2 U91 ( .A(pi02), .B(n90), .Z(n87));
IV2 U92 ( .A(pi03), .Z(n90));
endmodule
module IV2(A, Z);
input A;
output Z;
assign Z = ~A;
endmodule
module AN2(A, B, Z);
input A, B;
output Z;
assign Z = A & B;
endmodule
module OR2(A, B, Z);
input A, B;
output Z;
assign Z = A | B;
endmodule

41
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read_verilog t481.v
techmap
flatten
select t481_lev2
glift -create-instrumented-model
techmap
opt
rename t481_lev2 uut
cd ..
delete [AIONX][NVXR]2
read_verilog t481.v
techmap
flatten
select t481_lev2
glift -create-precise-model
techmap
opt
rename t481_lev2 spec
cd ..
delete [AIONX][NVXR]2
design -push-copy
miter -equiv spec uut miter
flatten
delete uut spec
techmap
opt
stat miter
qbfsat -O2 -write-solution t481.soln -solver yices -timeout 3600 -nocleanup -assume-outputs -assume-negative-polarity miter
design -pop
stat
copy uut solved
qbfsat -specialize-from-file t481.soln solved
opt solved
miter -equiv spec solved satmiter
flatten
sat -prove trigger 0 satmiter
delete satmiter
stat
shell

345
examples/smtbmc/glift/too_large.v Executable file
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module too_large_lev2(pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09,
pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19,
pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29,
pi30, pi31, pi32, pi33, pi34, pi35, pi36, pi37, po0, po1,
po2);
input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09,
pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19,
pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29,
pi30, pi31, pi32, pi33, pi34, pi35, pi36, pi37;
output po0, po1, po2;
wire n280, n281, n282, n283, n284, n285, n286, n287, n288, n289,
n290, n291, n292, n293, n294, n295, n296, n297, n298, n299,
n300, n301, n302, n303, n304, n305, n306, n307, n308, n309,
n310, n311, n312, n313, n314, n315, n316, n317, n318, n319,
n320, n321, n322, n323, n324, n325, n326, n327, n328, n329,
n330, n331, n332, n333, n334, n335, n336, n337, n338, n339,
n340, n341, n342, n343, n344, n345, n346, n347, n348, n349,
n350, n351, n352, n353, n354, n355, n356, n357, n358, n359,
n360, n361, n362, n363, n364, n365, n366, n367, n368, n369,
n370, n371, n372, n373, n374, n375, n376, n377, n378, n379,
n380, n381, n382, n383, n384, n385, n386, n387, n388, n389,
n390, n391, n392, n393, n394, n395, n396, n397, n398, n399,
n400, n401, n402, n403, n404, n405, n406, n407, n408, n409,
n410, n411, n412, n413, n414, n415, n416, n417, n418, n419,
n420, n421, n422, n423, n424, n425, n426, n427, n428, n429,
n430, n431, n432, n433, n434, n435, n436, n437, n438, n439,
n440, n441, n442, n443, n444, n445, n446, n447, n448, n449,
n450, n451, n452, n453, n454, n455, n456, n457, n458, n459,
n460, n461, n462, n463, n464, n465, n466, n467, n468, n469,
n470, n471, n472, n473, n474, n475, n476, n477, n478, n479,
n480, n481, n482, n483, n484, n485, n486, n487, n488, n489,
n490, n491, n492, n493, n494, n495, n496, n497, n498, n499,
n500, n501, n502, n503, n504, n505, n506, n507, n508, n509,
n510, n511, n512, n513, n514, n515, n516, n517, n518, n519,
n520, n521, n522, n523, n524, n525, n526, n527, n528, n529,
n530, n531, n532, n533, n534, n535, n536, n537, n538, n539,
n540, n541, n542, n543, n544, n545, n546, n547, n548, n549,
n550, n551, n552, n553, n554, n555, n556;
AN2 U283 ( .A(n280), .B(n281), .Z(po2));
OR2 U284 ( .A(n282), .B(n283), .Z(n280));
OR2 U285 ( .A(n284), .B(n285), .Z(n283));
AN2 U286 ( .A(n286), .B(n287), .Z(n285));
OR2 U287 ( .A(n288), .B(n289), .Z(n287));
OR2 U288 ( .A(n290), .B(n291), .Z(n289));
AN2 U289 ( .A(pi29), .B(n292), .Z(n291));
AN2 U290 ( .A(n293), .B(pi35), .Z(n290));
AN2 U291 ( .A(n294), .B(n295), .Z(n293));
OR2 U292 ( .A(pi29), .B(n296), .Z(n294));
AN2 U293 ( .A(n297), .B(pi18), .Z(n284));
AN2 U294 ( .A(n298), .B(n299), .Z(n297));
IV2 U295 ( .A(n300), .Z(n299));
OR2 U296 ( .A(n301), .B(n302), .Z(n298));
AN2 U297 ( .A(n303), .B(n304), .Z(n302));
OR2 U298 ( .A(n305), .B(n306), .Z(n304));
AN2 U299 ( .A(n307), .B(n308), .Z(n306));
AN2 U300 ( .A(n309), .B(n310), .Z(n305));
OR2 U301 ( .A(n311), .B(n312), .Z(n310));
AN2 U302 ( .A(n308), .B(n313), .Z(n312));
OR2 U303 ( .A(n314), .B(n315), .Z(n308));
AN2 U304 ( .A(n316), .B(n317), .Z(n311));
AN2 U305 ( .A(n318), .B(n319), .Z(n317));
AN2 U306 ( .A(pi15), .B(n315), .Z(n316));
OR2 U307 ( .A(n320), .B(n321), .Z(n315));
AN2 U308 ( .A(n322), .B(n323), .Z(n309));
OR2 U309 ( .A(n324), .B(n325), .Z(n322));
AN2 U310 ( .A(n326), .B(n327), .Z(n301));
OR2 U311 ( .A(n328), .B(n307), .Z(n327));
AN2 U312 ( .A(n329), .B(n323), .Z(n328));
OR2 U313 ( .A(n330), .B(n331), .Z(n329));
AN2 U314 ( .A(n332), .B(n313), .Z(n331));
OR2 U315 ( .A(n333), .B(n325), .Z(n332));
AN2 U316 ( .A(n324), .B(n334), .Z(n333));
IV2 U317 ( .A(n335), .Z(n334));
AN2 U318 ( .A(n336), .B(pi08), .Z(n335));
OR2 U319 ( .A(n320), .B(n314), .Z(n336));
AN2 U320 ( .A(n337), .B(n338), .Z(n314));
OR2 U321 ( .A(pi20), .B(n339), .Z(n337));
AN2 U322 ( .A(n340), .B(n341), .Z(n330));
AN2 U323 ( .A(n342), .B(n319), .Z(n341));
OR2 U324 ( .A(n343), .B(n325), .Z(n342));
AN2 U325 ( .A(n324), .B(n344), .Z(n343));
IV2 U326 ( .A(n345), .Z(n344));
AN2 U327 ( .A(n346), .B(n295), .Z(n324));
AN2 U328 ( .A(pi15), .B(n318), .Z(n340));
OR2 U329 ( .A(n347), .B(n348), .Z(n318));
AN2 U330 ( .A(n349), .B(n350), .Z(n347));
AN2 U331 ( .A(n351), .B(n352), .Z(n326));
OR2 U332 ( .A(n353), .B(n354), .Z(n282));
AN2 U333 ( .A(n355), .B(n356), .Z(n354));
AN2 U334 ( .A(n357), .B(n358), .Z(n355));
OR2 U335 ( .A(pi26), .B(pi27), .Z(n357));
AN2 U336 ( .A(n359), .B(n360), .Z(n353));
OR2 U337 ( .A(n361), .B(n362), .Z(n360));
AN2 U338 ( .A(n288), .B(n363), .Z(n362));
OR2 U339 ( .A(n364), .B(n365), .Z(n288));
AN2 U340 ( .A(n292), .B(n296), .Z(n364));
OR2 U341 ( .A(n366), .B(n367), .Z(n296));
IV2 U342 ( .A(n368), .Z(n367));
AN2 U343 ( .A(n369), .B(n370), .Z(n368));
OR2 U344 ( .A(pi33), .B(pi22), .Z(n366));
AN2 U345 ( .A(pi29), .B(n371), .Z(n361));
OR2 U346 ( .A(n372), .B(n373), .Z(n371));
AN2 U347 ( .A(n374), .B(n292), .Z(n372));
IV2 U348 ( .A(n356), .Z(n359));
AN2 U349 ( .A(n295), .B(pi35), .Z(n356));
IV2 U350 ( .A(pi28), .Z(n295));
OR2 U351 ( .A(n375), .B(n376), .Z(po1));
OR2 U352 ( .A(n377), .B(n378), .Z(n376));
AN2 U353 ( .A(n379), .B(n380), .Z(n378));
AN2 U354 ( .A(n381), .B(n382), .Z(n380));
IV2 U355 ( .A(n365), .Z(n382));
AN2 U356 ( .A(n383), .B(pi05), .Z(n379));
AN2 U357 ( .A(n384), .B(n385), .Z(n377));
OR2 U358 ( .A(n386), .B(n387), .Z(n385));
AN2 U359 ( .A(n388), .B(n369), .Z(n387));
OR2 U360 ( .A(n389), .B(n390), .Z(n388));
AN2 U361 ( .A(n391), .B(n370), .Z(n390));
OR2 U362 ( .A(n392), .B(n393), .Z(n391));
OR2 U363 ( .A(n394), .B(n395), .Z(n393));
AN2 U364 ( .A(n396), .B(pi35), .Z(n395));
AN2 U365 ( .A(n397), .B(n358), .Z(n396));
AN2 U366 ( .A(n398), .B(n399), .Z(n394));
IV2 U367 ( .A(n400), .Z(n399));
AN2 U368 ( .A(n286), .B(pi08), .Z(n398));
AN2 U369 ( .A(n401), .B(n402), .Z(n392));
OR2 U370 ( .A(n403), .B(n286), .Z(n402));
AN2 U371 ( .A(n400), .B(n363), .Z(n403));
OR2 U372 ( .A(n404), .B(n300), .Z(n401));
AN2 U373 ( .A(pi37), .B(pi13), .Z(n404));
AN2 U374 ( .A(n405), .B(n406), .Z(n389));
AN2 U375 ( .A(n407), .B(n352), .Z(n406));
AN2 U376 ( .A(pi05), .B(n408), .Z(n405));
OR2 U377 ( .A(n409), .B(n410), .Z(n408));
AN2 U378 ( .A(n411), .B(n351), .Z(n410));
AN2 U379 ( .A(n412), .B(n413), .Z(n409));
OR2 U380 ( .A(n414), .B(n415), .Z(n412));
AN2 U381 ( .A(n416), .B(n351), .Z(n415));
OR2 U382 ( .A(n417), .B(n418), .Z(n416));
AN2 U383 ( .A(n286), .B(n319), .Z(n417));
AN2 U384 ( .A(n419), .B(n420), .Z(n414));
AN2 U385 ( .A(pi02), .B(n421), .Z(n419));
AN2 U386 ( .A(n422), .B(n423), .Z(n386));
AN2 U387 ( .A(n424), .B(n425), .Z(n423));
OR2 U388 ( .A(n426), .B(n427), .Z(n425));
AN2 U389 ( .A(n428), .B(n429), .Z(n427));
AN2 U390 ( .A(n430), .B(n407), .Z(n426));
IV2 U391 ( .A(n431), .Z(n407));
AN2 U392 ( .A(n432), .B(pi21), .Z(n431));
OR2 U393 ( .A(pi01), .B(pi20), .Z(n432));
OR2 U394 ( .A(n433), .B(n434), .Z(n430));
AN2 U395 ( .A(n429), .B(n339), .Z(n433));
OR2 U396 ( .A(n435), .B(n411), .Z(n424));
AN2 U397 ( .A(n436), .B(n437), .Z(n411));
AN2 U398 ( .A(n438), .B(n286), .Z(n437));
IV2 U399 ( .A(n439), .Z(n436));
OR2 U400 ( .A(pi26), .B(pi06), .Z(n439));
AN2 U401 ( .A(pi05), .B(n303), .Z(n422));
AN2 U402 ( .A(n440), .B(n441), .Z(n375));
OR2 U403 ( .A(n442), .B(n443), .Z(n441));
AN2 U404 ( .A(pi35), .B(n397), .Z(n443));
OR2 U405 ( .A(pi27), .B(pi28), .Z(n397));
AN2 U406 ( .A(n300), .B(n400), .Z(n442));
OR2 U407 ( .A(pi26), .B(n413), .Z(n400));
OR2 U408 ( .A(n444), .B(n445), .Z(po0));
OR2 U409 ( .A(n446), .B(n447), .Z(n445));
AN2 U410 ( .A(n448), .B(pi04), .Z(n447));
AN2 U411 ( .A(n383), .B(n381), .Z(n448));
OR2 U412 ( .A(n449), .B(n450), .Z(n381));
AN2 U413 ( .A(n420), .B(n451), .Z(n450));
AN2 U414 ( .A(n452), .B(n453), .Z(n449));
OR2 U415 ( .A(n454), .B(n374), .Z(n452));
AN2 U416 ( .A(n373), .B(n455), .Z(n454));
AN2 U417 ( .A(n456), .B(n457), .Z(n383));
AN2 U418 ( .A(n413), .B(n281), .Z(n457));
AN2 U419 ( .A(n384), .B(n458), .Z(n446));
OR2 U420 ( .A(n459), .B(n460), .Z(n458));
OR2 U421 ( .A(n461), .B(n462), .Z(n460));
AN2 U422 ( .A(n463), .B(n369), .Z(n462));
OR2 U423 ( .A(n464), .B(n465), .Z(n463));
AN2 U424 ( .A(n466), .B(n467), .Z(n465));
OR2 U425 ( .A(n468), .B(n469), .Z(n467));
OR2 U426 ( .A(n470), .B(n471), .Z(n469));
AN2 U427 ( .A(n365), .B(n350), .Z(n471));
AN2 U428 ( .A(n472), .B(pi37), .Z(n470));
AN2 U429 ( .A(pi13), .B(n473), .Z(n472));
OR2 U430 ( .A(n474), .B(n475), .Z(n473));
AN2 U431 ( .A(n370), .B(n338), .Z(n475));
AN2 U432 ( .A(pi16), .B(n476), .Z(n474));
OR2 U433 ( .A(n477), .B(n428), .Z(n476));
AN2 U434 ( .A(n478), .B(n350), .Z(n477));
AN2 U435 ( .A(n300), .B(n479), .Z(n468));
OR2 U436 ( .A(n480), .B(n286), .Z(n466));
AN2 U437 ( .A(n481), .B(n363), .Z(n480));
AN2 U438 ( .A(n482), .B(n483), .Z(n464));
AN2 U439 ( .A(n370), .B(n358), .Z(n482));
AN2 U440 ( .A(n484), .B(n485), .Z(n461));
AN2 U441 ( .A(n286), .B(n486), .Z(n484));
OR2 U442 ( .A(n487), .B(n488), .Z(n486));
AN2 U443 ( .A(n489), .B(n370), .Z(n488));
OR2 U444 ( .A(n490), .B(n345), .Z(n489));
AN2 U445 ( .A(n320), .B(pi08), .Z(n345));
AN2 U446 ( .A(pi06), .B(n369), .Z(n490));
AN2 U447 ( .A(n491), .B(n429), .Z(n487));
AN2 U448 ( .A(pi08), .B(n492), .Z(n491));
AN2 U449 ( .A(pi04), .B(n493), .Z(n459));
OR2 U450 ( .A(n494), .B(n495), .Z(n493));
AN2 U451 ( .A(n303), .B(n496), .Z(n495));
OR2 U452 ( .A(n497), .B(n498), .Z(n496));
AN2 U453 ( .A(n499), .B(n500), .Z(n498));
OR2 U454 ( .A(n501), .B(n307), .Z(n500));
AN2 U455 ( .A(n374), .B(n502), .Z(n307));
AN2 U456 ( .A(n413), .B(n453), .Z(n502));
AN2 U457 ( .A(n503), .B(n313), .Z(n501));
OR2 U458 ( .A(n504), .B(n505), .Z(n503));
AN2 U459 ( .A(n325), .B(n323), .Z(n504));
AN2 U460 ( .A(n413), .B(n506), .Z(n325));
AN2 U461 ( .A(n434), .B(n370), .Z(n499));
OR2 U462 ( .A(n507), .B(n320), .Z(n434));
AN2 U463 ( .A(n321), .B(n508), .Z(n507));
IV2 U464 ( .A(pi07), .Z(n321));
AN2 U465 ( .A(n509), .B(n429), .Z(n497));
AN2 U466 ( .A(n508), .B(n338), .Z(n429));
IV2 U467 ( .A(pi15), .Z(n338));
AN2 U468 ( .A(n510), .B(n492), .Z(n509));
OR2 U469 ( .A(n511), .B(n428), .Z(n492));
AN2 U470 ( .A(n479), .B(pi20), .Z(n428));
AN2 U471 ( .A(n339), .B(n350), .Z(n511));
OR2 U472 ( .A(n478), .B(n348), .Z(n339));
IV2 U473 ( .A(pi16), .Z(n348));
IV2 U474 ( .A(n349), .Z(n478));
AN2 U475 ( .A(n512), .B(n513), .Z(n349));
OR2 U476 ( .A(pi25), .B(pi17), .Z(n513));
OR2 U477 ( .A(n514), .B(pi24), .Z(n512));
IV2 U478 ( .A(pi09), .Z(n514));
OR2 U479 ( .A(n515), .B(n435), .Z(n510));
AN2 U480 ( .A(n516), .B(n413), .Z(n435));
OR2 U481 ( .A(n517), .B(n418), .Z(n516));
AN2 U482 ( .A(n363), .B(n453), .Z(n418));
OR2 U483 ( .A(n373), .B(n374), .Z(n363));
AN2 U484 ( .A(n323), .B(pi02), .Z(n373));
AN2 U485 ( .A(n505), .B(n438), .Z(n515));
OR2 U486 ( .A(n453), .B(n319), .Z(n438));
IV2 U487 ( .A(n518), .Z(n303));
OR2 U488 ( .A(n519), .B(n520), .Z(n518));
OR2 U489 ( .A(pi08), .B(n521), .Z(n520));
OR2 U490 ( .A(pi10), .B(n522), .Z(n519));
OR2 U491 ( .A(pi12), .B(pi11), .Z(n522));
AN2 U492 ( .A(n523), .B(n524), .Z(n494));
OR2 U493 ( .A(n525), .B(n526), .Z(n524));
AN2 U494 ( .A(n527), .B(n528), .Z(n526));
OR2 U495 ( .A(n529), .B(n530), .Z(n528));
AN2 U496 ( .A(n531), .B(n351), .Z(n530));
AN2 U497 ( .A(n358), .B(n453), .Z(n531));
OR2 U498 ( .A(n532), .B(n374), .Z(n358));
AN2 U499 ( .A(n506), .B(n323), .Z(n532));
AN2 U500 ( .A(n517), .B(n533), .Z(n529));
AN2 U501 ( .A(n421), .B(n534), .Z(n533));
IV2 U502 ( .A(pi14), .Z(n421));
AN2 U503 ( .A(n420), .B(n506), .Z(n517));
OR2 U504 ( .A(pi02), .B(n346), .Z(n506));
AN2 U505 ( .A(n323), .B(n319), .Z(n420));
AN2 U506 ( .A(n369), .B(n413), .Z(n527));
OR2 U507 ( .A(n320), .B(n508), .Z(n369));
AN2 U508 ( .A(n535), .B(n536), .Z(n525));
AN2 U509 ( .A(n313), .B(n351), .Z(n536));
IV2 U510 ( .A(n521), .Z(n351));
AN2 U511 ( .A(pi00), .B(pi14), .Z(n521));
OR2 U512 ( .A(n537), .B(n453), .Z(n313));
IV2 U513 ( .A(pi13), .Z(n453));
AN2 U514 ( .A(n319), .B(n534), .Z(n537));
IV2 U515 ( .A(pi37), .Z(n534));
IV2 U516 ( .A(pi03), .Z(n319));
AN2 U517 ( .A(n505), .B(n538), .Z(n535));
OR2 U518 ( .A(n539), .B(n320), .Z(n538));
IV2 U519 ( .A(pi19), .Z(n320));
AN2 U520 ( .A(n540), .B(n508), .Z(n539));
IV2 U521 ( .A(pi23), .Z(n508));
IV2 U522 ( .A(pi08), .Z(n540));
AN2 U523 ( .A(n541), .B(n286), .Z(n505));
AN2 U524 ( .A(n346), .B(n323), .Z(n286));
IV2 U525 ( .A(pi27), .Z(n541));
AN2 U526 ( .A(n370), .B(n352), .Z(n523));
IV2 U527 ( .A(pi36), .Z(n352));
OR2 U528 ( .A(n350), .B(n479), .Z(n370));
IV2 U529 ( .A(pi21), .Z(n479));
IV2 U530 ( .A(pi20), .Z(n350));
IV2 U531 ( .A(n542), .Z(n384));
OR2 U532 ( .A(n543), .B(n544), .Z(n542));
OR2 U533 ( .A(pi29), .B(pi22), .Z(n544));
OR2 U534 ( .A(pi34), .B(pi33), .Z(n543));
AN2 U535 ( .A(n440), .B(n545), .Z(n444));
OR2 U536 ( .A(n546), .B(n483), .Z(n545));
OR2 U537 ( .A(n547), .B(n548), .Z(n483));
AN2 U538 ( .A(pi28), .B(pi35), .Z(n548));
AN2 U539 ( .A(pi26), .B(n485), .Z(n547));
IV2 U540 ( .A(n481), .Z(n485));
AN2 U541 ( .A(n549), .B(n481), .Z(n546));
OR2 U542 ( .A(pi27), .B(n413), .Z(n481));
IV2 U543 ( .A(pi35), .Z(n413));
OR2 U544 ( .A(n365), .B(n300), .Z(n549));
AN2 U545 ( .A(pi01), .B(pi31), .Z(n300));
AN2 U546 ( .A(pi01), .B(pi21), .Z(n365));
AN2 U547 ( .A(n456), .B(n550), .Z(n440));
AN2 U548 ( .A(n281), .B(n551), .Z(n550));
OR2 U549 ( .A(n374), .B(n552), .Z(n551));
AN2 U550 ( .A(n323), .B(n451), .Z(n552));
OR2 U551 ( .A(n553), .B(n554), .Z(n451));
AN2 U552 ( .A(n555), .B(n346), .Z(n554));
IV2 U553 ( .A(pi32), .Z(n346));
AN2 U554 ( .A(pi02), .B(n455), .Z(n553));
IV2 U555 ( .A(pi29), .Z(n455));
IV2 U556 ( .A(pi30), .Z(n323));
AN2 U557 ( .A(n555), .B(pi03), .Z(n374));
IV2 U558 ( .A(pi02), .Z(n555));
IV2 U559 ( .A(pi34), .Z(n281));
IV2 U560 ( .A(n292), .Z(n456));
OR2 U561 ( .A(pi00), .B(n556), .Z(n292));
OR2 U562 ( .A(pi37), .B(pi36), .Z(n556));
endmodule
module IV2(A, Z);
input A;
output Z;
assign Z = ~A;
endmodule
module AN2(A, B, Z);
input A, B;
output Z;
assign Z = A & B;
endmodule
module OR2(A, B, Z);
input A, B;
output Z;
assign Z = A | B;
endmodule

41
examples/smtbmc/glift/too_large.ys Normal file
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read_verilog too_large.v
techmap
flatten
select too_large_lev2
glift -create-instrumented-model
techmap
opt
rename too_large_lev2 uut
cd ..
delete [AIONX][NVXR]2
read_verilog too_large.v
techmap
flatten
select too_large_lev2
glift -create-precise-model
techmap
opt
rename too_large_lev2 spec
cd ..
delete [AIONX][NVXR]2
design -push-copy
miter -equiv spec uut miter
flatten
delete uut spec
techmap
opt
stat miter
qbfsat -O2 -write-solution too_large.soln -solver yices -timeout 3600 -nocleanup -assume-outputs -assume-negative-polarity miter
design -pop
stat
copy uut solved
qbfsat -specialize-from-file too_large.soln solved
opt solved
miter -equiv spec solved satmiter
flatten
sat -prove trigger 0 satmiter
delete satmiter
stat
shell

220
examples/smtbmc/glift/ttt2.v Executable file
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module ttt2_lev2(pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09,
pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19,
pi20, pi21, pi22, pi23, po00, po01, po02, po03, po04, po05,
po06, po07, po08, po09, po10, po11, po12, po13, po14, po15,
po16, po17, po18, po19, po20);
input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09,
pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19,
pi20, pi21, pi22, pi23;
output po00, po01, po02, po03, po04, po05, po06, po07, po08, po09,
po10, po11, po12, po13, po14, po15, po16, po17, po18, po19,
po20;
wire n148, n149, n150, n151, n152, n153, n154, n155, n156, n157,
n158, n159, n160, n161, n162, n163, n164, n165, n166, n167,
n168, n169, n170, n171, n172, n173, n174, n175, n176, n177,
n178, n179, n180, n181, n182, n183, n184, n185, n186, n187,
n188, n189, n190, n191, n192, n193, n194, n195, n196, n197,
n198, n199, n200, n201, n202, n203, n204, n205, n206, n207,
n208, n209, n210, n211, n212, n213, n214, n215, n216, n217,
n218, n219, n220, n221, n222, n223, n224, n225, n226, n227,
n228, n229, n230, n231, n232, n233, n234, n235, n236, n237,
n238, n239, n240, n241, n242, n243, n244, n245, n246, n247,
n248, n249, n250, n251, n252, n253, n254, n255, n256, n257,
n258, n259, n260, n261, n262, n263, n264, n265, n266, n267,
n268, n269, n270, n271, n272, n273, n274, n275, n276, n277,
n278, n279, n280, n281, n282, n283, n284, n285, n286, n287,
n288, n289, n290, n291, n292, n293;
AN2 U168 ( .A(n148), .B(n149), .Z(po20));
OR2 U169 ( .A(n150), .B(n151), .Z(n148));
AN2 U170 ( .A(pi02), .B(n152), .Z(n151));
IV2 U171 ( .A(n153), .Z(n150));
OR2 U172 ( .A(n152), .B(pi02), .Z(n153));
IV2 U173 ( .A(pi23), .Z(n152));
AN2 U174 ( .A(n154), .B(n149), .Z(po19));
OR2 U175 ( .A(n155), .B(n156), .Z(n154));
AN2 U176 ( .A(pi01), .B(n157), .Z(n156));
AN2 U177 ( .A(pi22), .B(n158), .Z(n155));
IV2 U178 ( .A(pi01), .Z(n158));
AN2 U179 ( .A(n159), .B(n149), .Z(po18));
OR2 U180 ( .A(n160), .B(n161), .Z(po17));
AN2 U181 ( .A(pi20), .B(n162), .Z(n161));
OR2 U182 ( .A(n163), .B(n164), .Z(n162));
OR2 U183 ( .A(n165), .B(n166), .Z(n164));
AN2 U184 ( .A(n167), .B(pi18), .Z(n166));
AN2 U185 ( .A(n149), .B(n168), .Z(n167));
AN2 U186 ( .A(n169), .B(n170), .Z(n160));
AN2 U187 ( .A(n171), .B(n172), .Z(n169));
OR2 U188 ( .A(n165), .B(n173), .Z(po16));
OR2 U189 ( .A(n174), .B(n175), .Z(n173));
AN2 U190 ( .A(n176), .B(n168), .Z(n175));
AN2 U191 ( .A(n170), .B(n171), .Z(n176));
AN2 U192 ( .A(pi19), .B(n163), .Z(n174));
AN2 U193 ( .A(pi19), .B(n177), .Z(n165));
AN2 U194 ( .A(n178), .B(n149), .Z(n177));
OR2 U195 ( .A(n179), .B(n180), .Z(po15));
AN2 U196 ( .A(n181), .B(n178), .Z(n180));
AN2 U197 ( .A(n182), .B(n170), .Z(n181));
AN2 U198 ( .A(pi17), .B(n183), .Z(n182));
OR2 U199 ( .A(pi19), .B(n184), .Z(n183));
AN2 U200 ( .A(pi18), .B(n163), .Z(n179));
OR2 U201 ( .A(n185), .B(n186), .Z(n163));
AN2 U202 ( .A(n149), .B(n187), .Z(n185));
OR2 U203 ( .A(n188), .B(n189), .Z(po14));
AN2 U204 ( .A(pi17), .B(n186), .Z(n189));
OR2 U205 ( .A(n190), .B(n191), .Z(n186));
AN2 U206 ( .A(n192), .B(n149), .Z(n190));
OR2 U207 ( .A(pi14), .B(n193), .Z(n192));
AN2 U208 ( .A(n170), .B(n187), .Z(n188));
AN2 U209 ( .A(n194), .B(n195), .Z(n170));
AN2 U210 ( .A(n196), .B(n197), .Z(n195));
OR2 U211 ( .A(n198), .B(n199), .Z(po13));
AN2 U212 ( .A(pi16), .B(n200), .Z(n199));
OR2 U213 ( .A(n201), .B(n191), .Z(n200));
AN2 U214 ( .A(n202), .B(pi14), .Z(n198));
AN2 U215 ( .A(n203), .B(n149), .Z(n202));
OR2 U216 ( .A(n204), .B(n197), .Z(n203));
IV2 U217 ( .A(n193), .Z(n197));
AN2 U218 ( .A(n205), .B(n206), .Z(n204));
AN2 U219 ( .A(n207), .B(n208), .Z(n206));
AN2 U220 ( .A(pi15), .B(pi13), .Z(n205));
OR2 U221 ( .A(n201), .B(n209), .Z(po12));
OR2 U222 ( .A(n210), .B(n211), .Z(n209));
AN2 U223 ( .A(n212), .B(n213), .Z(n211));
AN2 U224 ( .A(pi14), .B(n194), .Z(n212));
AN2 U225 ( .A(pi15), .B(n191), .Z(n210));
AN2 U226 ( .A(pi15), .B(n214), .Z(n201));
AN2 U227 ( .A(n196), .B(n149), .Z(n214));
OR2 U228 ( .A(n215), .B(n216), .Z(po11));
AN2 U229 ( .A(n217), .B(n196), .Z(n216));
IV2 U230 ( .A(pi14), .Z(n196));
AN2 U231 ( .A(n194), .B(n193), .Z(n217));
OR2 U232 ( .A(pi15), .B(n208), .Z(n193));
IV2 U233 ( .A(pi16), .Z(n208));
AN2 U234 ( .A(pi13), .B(n218), .Z(n194));
AN2 U235 ( .A(pi14), .B(n191), .Z(n215));
OR2 U236 ( .A(n219), .B(n220), .Z(n191));
AN2 U237 ( .A(n149), .B(n221), .Z(n220));
OR2 U238 ( .A(n222), .B(n223), .Z(po10));
AN2 U239 ( .A(n219), .B(pi13), .Z(n223));
AN2 U240 ( .A(n224), .B(n157), .Z(n219));
IV2 U241 ( .A(pi22), .Z(n157));
OR2 U242 ( .A(n225), .B(n226), .Z(n224));
OR2 U243 ( .A(po06), .B(n227), .Z(n226));
AN2 U244 ( .A(n218), .B(n221), .Z(n222));
IV2 U245 ( .A(pi13), .Z(n221));
AN2 U246 ( .A(n207), .B(n149), .Z(n218));
OR2 U247 ( .A(n228), .B(pi22), .Z(n207));
AN2 U248 ( .A(n229), .B(pi09), .Z(n228));
AN2 U249 ( .A(n230), .B(n231), .Z(n229));
OR2 U250 ( .A(n232), .B(n233), .Z(po09));
AN2 U251 ( .A(pi12), .B(n234), .Z(n233));
OR2 U252 ( .A(n235), .B(po06), .Z(n234));
AN2 U253 ( .A(n227), .B(n236), .Z(n232));
OR2 U254 ( .A(n237), .B(n230), .Z(n236));
AN2 U255 ( .A(n238), .B(pi11), .Z(n237));
AN2 U256 ( .A(pi09), .B(n239), .Z(n238));
IV2 U257 ( .A(pi12), .Z(n239));
OR2 U258 ( .A(n235), .B(n240), .Z(po08));
OR2 U259 ( .A(n241), .B(n242), .Z(n240));
AN2 U260 ( .A(po06), .B(pi11), .Z(n242));
AN2 U261 ( .A(n243), .B(n244), .Z(n241));
AN2 U262 ( .A(n227), .B(pi09), .Z(n243));
AN2 U263 ( .A(n149), .B(pi10), .Z(n227));
AN2 U264 ( .A(pi11), .B(n245), .Z(n235));
AN2 U265 ( .A(n231), .B(n149), .Z(n245));
OR2 U266 ( .A(n246), .B(n247), .Z(po07));
AN2 U267 ( .A(po06), .B(pi10), .Z(n247));
AN2 U268 ( .A(n248), .B(n231), .Z(n246));
IV2 U269 ( .A(pi10), .Z(n231));
AN2 U270 ( .A(n225), .B(pi09), .Z(n248));
AN2 U271 ( .A(n249), .B(n149), .Z(n225));
IV2 U272 ( .A(n230), .Z(n249));
AN2 U273 ( .A(n244), .B(pi12), .Z(n230));
IV2 U274 ( .A(pi11), .Z(n244));
AN2 U275 ( .A(n250), .B(n149), .Z(po06));
IV2 U276 ( .A(pi00), .Z(n149));
IV2 U277 ( .A(pi09), .Z(n250));
AN2 U278 ( .A(n251), .B(n252), .Z(po05));
OR2 U279 ( .A(n253), .B(n254), .Z(n251));
OR2 U280 ( .A(n255), .B(n256), .Z(n254));
AN2 U281 ( .A(n257), .B(n187), .Z(n255));
AN2 U282 ( .A(pi08), .B(n258), .Z(n253));
OR2 U283 ( .A(n259), .B(n260), .Z(po04));
AN2 U284 ( .A(pi07), .B(n261), .Z(n260));
AN2 U285 ( .A(n262), .B(n257), .Z(n259));
AN2 U286 ( .A(n171), .B(n252), .Z(n262));
AN2 U287 ( .A(pi17), .B(pi18), .Z(n171));
OR2 U288 ( .A(n263), .B(n264), .Z(po03));
OR2 U289 ( .A(n265), .B(n266), .Z(n264));
AN2 U290 ( .A(pi06), .B(n261), .Z(n266));
AN2 U291 ( .A(n267), .B(n213), .Z(n265));
OR2 U292 ( .A(n172), .B(pi21), .Z(n267));
OR2 U293 ( .A(n268), .B(n269), .Z(n263));
OR2 U294 ( .A(n270), .B(n269), .Z(po02));
IV2 U295 ( .A(n271), .Z(n269));
OR2 U296 ( .A(n272), .B(n273), .Z(n271));
AN2 U297 ( .A(n274), .B(n275), .Z(n272));
OR2 U298 ( .A(n187), .B(n276), .Z(n275));
OR2 U299 ( .A(pi21), .B(n277), .Z(n274));
AN2 U300 ( .A(pi05), .B(n261), .Z(n270));
OR2 U301 ( .A(n278), .B(n279), .Z(po01));
OR2 U302 ( .A(n268), .B(n280), .Z(n279));
AN2 U303 ( .A(pi04), .B(n261), .Z(n280));
AN2 U304 ( .A(n252), .B(n258), .Z(n261));
IV2 U305 ( .A(n281), .Z(n268));
OR2 U306 ( .A(n282), .B(n283), .Z(n281));
OR2 U307 ( .A(n184), .B(n284), .Z(n283));
OR2 U308 ( .A(pi21), .B(pi17), .Z(n282));
AN2 U309 ( .A(n159), .B(n213), .Z(n278));
IV2 U310 ( .A(pi15), .Z(n213));
OR2 U311 ( .A(n285), .B(n286), .Z(n159));
AN2 U312 ( .A(pi21), .B(n287), .Z(n286));
OR2 U313 ( .A(n276), .B(n288), .Z(n287));
OR2 U314 ( .A(n273), .B(n187), .Z(n288));
OR2 U315 ( .A(pi23), .B(pi18), .Z(n276));
AN2 U316 ( .A(n172), .B(n277), .Z(n285));
AN2 U317 ( .A(pi23), .B(n289), .Z(n277));
AN2 U318 ( .A(n178), .B(n187), .Z(n289));
IV2 U319 ( .A(pi17), .Z(n187));
IV2 U320 ( .A(pi18), .Z(n178));
IV2 U321 ( .A(n273), .Z(n172));
OR2 U322 ( .A(pi20), .B(n168), .Z(n273));
AN2 U323 ( .A(n290), .B(n252), .Z(po00));
IV2 U324 ( .A(pi21), .Z(n252));
OR2 U325 ( .A(n256), .B(n291), .Z(n290));
OR2 U326 ( .A(n257), .B(n292), .Z(n291));
AN2 U327 ( .A(pi03), .B(n258), .Z(n292));
AN2 U328 ( .A(n284), .B(pi20), .Z(n258));
AN2 U329 ( .A(n184), .B(n168), .Z(n257));
IV2 U330 ( .A(pi19), .Z(n168));
IV2 U331 ( .A(pi20), .Z(n184));
AN2 U332 ( .A(n293), .B(pi17), .Z(n256));
IV2 U333 ( .A(n284), .Z(n293));
OR2 U334 ( .A(pi18), .B(pi19), .Z(n284));
endmodule
module IV2(A, Z);
input A;
output Z;
assign Z = ~A;
endmodule
module AN2(A, B, Z);
input A, B;
output Z;
assign Z = A & B;
endmodule
module OR2(A, B, Z);
input A, B;
output Z;
assign Z = A | B;
endmodule

41
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read_verilog ttt2.v
techmap
flatten
select ttt2_lev2
glift -create-instrumented-model
techmap
opt
rename ttt2_lev2 uut
cd ..
delete [AIONX][NVXR]2
read_verilog ttt2.v
techmap
flatten
select ttt2_lev2
glift -create-precise-model
techmap
opt
rename ttt2_lev2 spec
cd ..
delete [AIONX][NVXR]2
design -push-copy
miter -equiv spec uut miter
flatten
delete uut spec
techmap
opt
stat miter
qbfsat -O2 -write-solution ttt2.soln -solver yices -timeout 3600 -nocleanup -assume-outputs -assume-negative-polarity miter
design -pop
stat
copy uut solved
qbfsat -specialize-from-file ttt2.soln solved
opt solved
miter -equiv spec solved satmiter
flatten
sat -prove trigger 0 satmiter
delete satmiter
stat
shell

380
examples/smtbmc/glift/x1.v Executable file
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module x1_lev2(pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09,
pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19,
pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29,
pi30, pi31, pi32, pi33, pi34, pi35, pi36, pi37, pi38, pi39,
pi40, pi41, pi42, pi43, pi44, pi45, pi46, pi47, pi48, pi49,
pi50, po00, po01, po02, po03, po04, po05, po06, po07, po08,
po09, po10, po11, po12, po13, po14, po15, po16, po17, po18,
po19, po20, po21, po22, po23, po24, po25, po26, po27, po28,
po29, po30, po31, po32, po33, po34);
input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09,
pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19,
pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29,
pi30, pi31, pi32, pi33, pi34, pi35, pi36, pi37, pi38, pi39,
pi40, pi41, pi42, pi43, pi44, pi45, pi46, pi47, pi48, pi49,
pi50;
output po00, po01, po02, po03, po04, po05, po06, po07, po08, po09,
po10, po11, po12, po13, po14, po15, po16, po17, po18, po19,
po20, po21, po22, po23, po24, po25, po26, po27, po28, po29,
po30, po31, po32, po33, po34;
wire po05, po16, po18, po24, po25, po28, po29, n270, n271, n272,
n273, n274, n275, n276, n277, n278, n279, n280, n281, n282,
n283, n284, n285, n286, n287, n288, n289, n290, n291, n292,
n293, n294, n295, n296, n297, n298, n299, n300, n301, n302,
n303, n304, n305, n306, n307, n308, n309, n310, n311, n312,
n313, n314, n315, n316, n317, n318, n319, n320, n321, n322,
n323, n324, n325, n326, n327, n328, n329, n330, n331, n332,
n333, n334, n335, n336, n337, n338, n339, n340, n341, n342,
n343, n344, n345, n346, n347, n348, n349, n350, n351, n352,
n353, n354, n355, n356, n357, n358, n359, n360, n361, n362,
n363, n364, n365, n366, n367, n368, n369, n370, n371, n372,
n373, n374, n375, n376, n377, n378, n379, n380, n381, n382,
n383, n384, n385, n386, n387, n388, n389, n390, n391, n392,
n393, n394, n395, n396, n397, n398, n399, n400, n401, n402,
n403, n404, n405, n406, n407, n408, n409, n410, n411, n412,
n413, n414, n415, n416, n417, n418, n419, n420, n421, n422,
n423, n424, n425, n426, n427, n428, n429, n430, n431, n432,
n433, n434, n435, n436, n437, n438, n439, n440, n441, n442,
n443, n444, n445, n446, n447, n448, n449, n450, n451, n452,
n453, n454, n455, n456, n457, n458, n459, n460, n461, n462,
n463, n464, n465, n466, n467, n468, n469, n470, n471, n472,
n473, n474, n475, n476, n477, n478, n479, n480, n481, n482,
n483, n484, n485, n486, n487, n488, n489, n490, n491, n492,
n493, n494, n495, n496, n497, n498, n499, n500, n501, n502,
n503, n504, n505, n506, n507, n508, n509, n510, n511, n512,
n513, n514, n515, n516, n517, n518, n519, n520, n521, n522,
n523, n524, n525, n526, n527, n528, n529, n530, n531, n532,
n533;
assign po05 = pi32;
assign po16 = pi37;
assign po18 = pi38;
assign po24 = pi23;
assign po25 = pi24;
assign po28 = pi48;
assign po29 = pi49;
IV2 U294 ( .A(po32), .Z(po33));
OR2 U295 ( .A(n270), .B(n271), .Z(po32));
OR2 U296 ( .A(po25), .B(po05), .Z(n271));
AN2 U297 ( .A(n272), .B(n273), .Z(n270));
OR2 U298 ( .A(pi31), .B(po01), .Z(n273));
AN2 U299 ( .A(n274), .B(pi18), .Z(po31));
AN2 U300 ( .A(pi17), .B(n275), .Z(n274));
AN2 U301 ( .A(n276), .B(n272), .Z(po30));
OR2 U302 ( .A(n277), .B(n278), .Z(n276));
AN2 U303 ( .A(n279), .B(n280), .Z(n278));
OR2 U304 ( .A(n281), .B(pi31), .Z(n280));
AN2 U305 ( .A(pi35), .B(n282), .Z(n281));
AN2 U306 ( .A(n283), .B(n284), .Z(n277));
OR2 U307 ( .A(n285), .B(n286), .Z(n284));
AN2 U308 ( .A(pi31), .B(n287), .Z(n286));
IV2 U309 ( .A(pi05), .Z(n287));
AN2 U310 ( .A(n288), .B(pi35), .Z(n285));
AN2 U311 ( .A(pi21), .B(pi13), .Z(n288));
AN2 U312 ( .A(pi07), .B(n289), .Z(po27));
OR2 U313 ( .A(n290), .B(n291), .Z(po26));
OR2 U314 ( .A(n292), .B(n293), .Z(n291));
AN2 U315 ( .A(n294), .B(n295), .Z(n293));
AN2 U316 ( .A(n296), .B(n297), .Z(n295));
AN2 U317 ( .A(pi33), .B(n298), .Z(n294));
IV2 U318 ( .A(n299), .Z(n298));
AN2 U319 ( .A(pi19), .B(pi00), .Z(n299));
AN2 U320 ( .A(n300), .B(n301), .Z(n292));
AN2 U321 ( .A(n302), .B(n303), .Z(n301));
OR2 U322 ( .A(n304), .B(pi35), .Z(n303));
AN2 U323 ( .A(n305), .B(pi25), .Z(n304));
AN2 U324 ( .A(pi11), .B(n306), .Z(n305));
AN2 U325 ( .A(n272), .B(n307), .Z(n302));
AN2 U326 ( .A(n308), .B(pi01), .Z(n300));
AN2 U327 ( .A(n279), .B(pi17), .Z(n308));
AN2 U328 ( .A(pi34), .B(n309), .Z(n290));
OR2 U329 ( .A(n310), .B(n311), .Z(po23));
AN2 U330 ( .A(n312), .B(n313), .Z(n310));
OR2 U331 ( .A(n314), .B(n315), .Z(po22));
AN2 U332 ( .A(n316), .B(n317), .Z(n315));
AN2 U333 ( .A(n318), .B(n319), .Z(n317));
OR2 U334 ( .A(n320), .B(n272), .Z(n319));
AN2 U335 ( .A(n321), .B(n322), .Z(n320));
IV2 U336 ( .A(pi02), .Z(n322));
AN2 U337 ( .A(n296), .B(n323), .Z(n321));
OR2 U338 ( .A(pi09), .B(n324), .Z(n318));
AN2 U339 ( .A(pi05), .B(pi21), .Z(n324));
AN2 U340 ( .A(pi31), .B(n309), .Z(n316));
AN2 U341 ( .A(n325), .B(n326), .Z(n314));
AN2 U342 ( .A(n283), .B(n327), .Z(n325));
OR2 U343 ( .A(n328), .B(n329), .Z(n327));
OR2 U344 ( .A(n330), .B(n331), .Z(n329));
OR2 U345 ( .A(n332), .B(n333), .Z(n331));
AN2 U346 ( .A(po05), .B(n272), .Z(n333));
AN2 U347 ( .A(pi43), .B(n296), .Z(n332));
AN2 U348 ( .A(pi47), .B(pi39), .Z(n330));
OR2 U349 ( .A(n334), .B(n335), .Z(n328));
OR2 U350 ( .A(n336), .B(n337), .Z(n335));
AN2 U351 ( .A(n338), .B(pi40), .Z(n337));
AN2 U352 ( .A(n339), .B(n340), .Z(n338));
AN2 U353 ( .A(n341), .B(n342), .Z(n336));
AN2 U354 ( .A(n343), .B(n344), .Z(n342));
AN2 U355 ( .A(n345), .B(pi41), .Z(n341));
AN2 U356 ( .A(pi29), .B(n346), .Z(n334));
OR2 U357 ( .A(n347), .B(n348), .Z(po21));
AN2 U358 ( .A(pi09), .B(po05), .Z(n348));
AN2 U359 ( .A(n349), .B(n350), .Z(n347));
AN2 U360 ( .A(n346), .B(n279), .Z(n350));
AN2 U361 ( .A(n351), .B(n326), .Z(n349));
OR2 U362 ( .A(n352), .B(n353), .Z(po20));
OR2 U363 ( .A(n354), .B(n355), .Z(n353));
AN2 U364 ( .A(pi22), .B(po05), .Z(n355));
AN2 U365 ( .A(n356), .B(n357), .Z(n354));
OR2 U366 ( .A(n358), .B(n359), .Z(n356));
OR2 U367 ( .A(po05), .B(n360), .Z(n359));
AN2 U368 ( .A(n361), .B(n362), .Z(n360));
OR2 U369 ( .A(n363), .B(n364), .Z(n362));
AN2 U370 ( .A(n346), .B(n365), .Z(n364));
AN2 U371 ( .A(n366), .B(pi14), .Z(n346));
AN2 U372 ( .A(n367), .B(n343), .Z(n363));
OR2 U373 ( .A(n368), .B(n365), .Z(n367));
OR2 U374 ( .A(n351), .B(pi29), .Z(n365));
AN2 U375 ( .A(pi28), .B(n345), .Z(n368));
AN2 U376 ( .A(n309), .B(n369), .Z(n361));
AN2 U377 ( .A(pi07), .B(n370), .Z(n358));
OR2 U378 ( .A(pi28), .B(pi29), .Z(n370));
OR2 U379 ( .A(n371), .B(n372), .Z(n352));
AN2 U380 ( .A(pi01), .B(n373), .Z(n372));
OR2 U381 ( .A(n374), .B(pi30), .Z(n373));
AN2 U382 ( .A(pi10), .B(pi25), .Z(n374));
AN2 U383 ( .A(n375), .B(n376), .Z(n371));
OR2 U384 ( .A(pi40), .B(pi41), .Z(n376));
OR2 U385 ( .A(n377), .B(n378), .Z(po19));
OR2 U386 ( .A(n379), .B(n380), .Z(n378));
AN2 U387 ( .A(pi42), .B(pi01), .Z(n380));
AN2 U388 ( .A(pi12), .B(n381), .Z(n379));
OR2 U389 ( .A(n382), .B(n383), .Z(n381));
OR2 U390 ( .A(n384), .B(n385), .Z(n383));
AN2 U391 ( .A(n386), .B(n369), .Z(n384));
OR2 U392 ( .A(po34), .B(n387), .Z(n386));
OR2 U393 ( .A(pi40), .B(pi26), .Z(n387));
OR2 U394 ( .A(pi27), .B(pi28), .Z(po34));
OR2 U395 ( .A(pi31), .B(pi29), .Z(n382));
OR2 U396 ( .A(n388), .B(n389), .Z(n377));
OR2 U397 ( .A(n390), .B(n391), .Z(n389));
AN2 U398 ( .A(n392), .B(pi18), .Z(n391));
AN2 U399 ( .A(pi17), .B(n393), .Z(n392));
OR2 U400 ( .A(pi36), .B(pi40), .Z(n393));
AN2 U401 ( .A(n394), .B(pi22), .Z(n390));
AN2 U402 ( .A(n351), .B(n369), .Z(n394));
AN2 U403 ( .A(pi00), .B(n395), .Z(n388));
OR2 U404 ( .A(n396), .B(n397), .Z(n395));
OR2 U405 ( .A(n385), .B(n398), .Z(n397));
OR2 U406 ( .A(n399), .B(n400), .Z(n398));
AN2 U407 ( .A(pi31), .B(n272), .Z(n399));
OR2 U408 ( .A(n401), .B(n402), .Z(n385));
OR2 U409 ( .A(pi41), .B(pi35), .Z(n402));
OR2 U410 ( .A(po05), .B(pi43), .Z(n401));
OR2 U411 ( .A(n403), .B(n404), .Z(n396));
OR2 U412 ( .A(pi25), .B(n289), .Z(n404));
OR2 U413 ( .A(pi34), .B(pi28), .Z(n403));
IV2 U414 ( .A(po17), .Z(po15));
OR2 U415 ( .A(n405), .B(n406), .Z(po17));
OR2 U416 ( .A(n407), .B(n408), .Z(n406));
OR2 U417 ( .A(n409), .B(n410), .Z(n408));
AN2 U418 ( .A(pi28), .B(n411), .Z(n410));
OR2 U419 ( .A(pi03), .B(n296), .Z(n411));
AN2 U420 ( .A(n412), .B(n413), .Z(n409));
OR2 U421 ( .A(n414), .B(n415), .Z(n413));
AN2 U422 ( .A(pi02), .B(pi31), .Z(n415));
AN2 U423 ( .A(n416), .B(n417), .Z(n414));
AN2 U424 ( .A(n418), .B(n309), .Z(n416));
OR2 U425 ( .A(pi25), .B(n272), .Z(n418));
OR2 U426 ( .A(pi09), .B(n419), .Z(n412));
AN2 U427 ( .A(n420), .B(n421), .Z(n419));
AN2 U428 ( .A(n275), .B(n309), .Z(n421));
OR2 U429 ( .A(pi25), .B(pi35), .Z(n275));
AN2 U430 ( .A(n417), .B(pi21), .Z(n420));
OR2 U431 ( .A(pi26), .B(n313), .Z(n407));
AN2 U432 ( .A(pi33), .B(pi08), .Z(n313));
OR2 U433 ( .A(n422), .B(n423), .Z(n405));
OR2 U434 ( .A(po05), .B(pi27), .Z(n423));
AN2 U435 ( .A(n424), .B(n425), .Z(po14));
AN2 U436 ( .A(n426), .B(n309), .Z(n425));
OR2 U437 ( .A(n427), .B(n428), .Z(n426));
OR2 U438 ( .A(n429), .B(n430), .Z(n428));
AN2 U439 ( .A(pi29), .B(n431), .Z(n430));
OR2 U440 ( .A(pi43), .B(pi40), .Z(n427));
AN2 U441 ( .A(n326), .B(pi07), .Z(n424));
OR2 U442 ( .A(n432), .B(n433), .Z(po12));
OR2 U443 ( .A(n434), .B(n435), .Z(n433));
AN2 U444 ( .A(pi28), .B(n436), .Z(n435));
OR2 U445 ( .A(n437), .B(pi21), .Z(n436));
AN2 U446 ( .A(n438), .B(pi14), .Z(n437));
AN2 U447 ( .A(n439), .B(n323), .Z(n438));
OR2 U448 ( .A(n440), .B(n441), .Z(n439));
IV2 U449 ( .A(n442), .Z(n441));
AN2 U450 ( .A(n443), .B(pi15), .Z(n440));
AN2 U451 ( .A(n444), .B(n445), .Z(n434));
AN2 U452 ( .A(n446), .B(n312), .Z(n445));
AN2 U453 ( .A(n447), .B(n448), .Z(n446));
OR2 U454 ( .A(n282), .B(n307), .Z(n447));
IV2 U455 ( .A(pi18), .Z(n307));
AN2 U456 ( .A(n449), .B(pi40), .Z(n444));
AN2 U457 ( .A(n450), .B(n451), .Z(n449));
OR2 U458 ( .A(n339), .B(n297), .Z(n451));
IV2 U459 ( .A(n452), .Z(n450));
AN2 U460 ( .A(n453), .B(n339), .Z(n452));
OR2 U461 ( .A(n340), .B(pi12), .Z(n453));
AN2 U462 ( .A(pi02), .B(pi03), .Z(n340));
AN2 U463 ( .A(pi46), .B(pi39), .Z(n432));
IV2 U464 ( .A(po13), .Z(po11));
OR2 U465 ( .A(n454), .B(n455), .Z(po13));
OR2 U466 ( .A(n456), .B(n457), .Z(n455));
AN2 U467 ( .A(pi25), .B(n458), .Z(n457));
OR2 U468 ( .A(n459), .B(n460), .Z(n458));
OR2 U469 ( .A(n461), .B(n462), .Z(n460));
AN2 U470 ( .A(n463), .B(n464), .Z(n461));
OR2 U471 ( .A(n282), .B(n465), .Z(n464));
OR2 U472 ( .A(pi12), .B(pi09), .Z(n465));
IV2 U473 ( .A(pi50), .Z(n463));
AN2 U474 ( .A(pi07), .B(n466), .Z(n456));
OR2 U475 ( .A(n467), .B(n468), .Z(n466));
OR2 U476 ( .A(n469), .B(n429), .Z(n468));
AN2 U477 ( .A(pi28), .B(n470), .Z(n429));
AN2 U478 ( .A(n400), .B(n471), .Z(n469));
OR2 U479 ( .A(pi40), .B(n431), .Z(n471));
OR2 U480 ( .A(pi43), .B(n289), .Z(n467));
AN2 U481 ( .A(pi19), .B(pi33), .Z(n289));
OR2 U482 ( .A(po01), .B(n472), .Z(n454));
OR2 U483 ( .A(po28), .B(po16), .Z(n472));
OR2 U484 ( .A(n473), .B(n474), .Z(po10));
AN2 U485 ( .A(n475), .B(pi41), .Z(n474));
AN2 U486 ( .A(n476), .B(n477), .Z(n475));
OR2 U487 ( .A(n297), .B(n343), .Z(n476));
AN2 U488 ( .A(n478), .B(n479), .Z(n473));
AN2 U489 ( .A(n283), .B(n296), .Z(n479));
AN2 U490 ( .A(pi29), .B(n345), .Z(n478));
IV2 U491 ( .A(n480), .Z(n345));
IV2 U492 ( .A(po07), .Z(po09));
OR2 U493 ( .A(n481), .B(n482), .Z(po08));
AN2 U494 ( .A(pi45), .B(pi39), .Z(n482));
AN2 U495 ( .A(n483), .B(n484), .Z(n481));
OR2 U496 ( .A(n485), .B(n486), .Z(n484));
AN2 U497 ( .A(pi29), .B(n312), .Z(n486));
AN2 U498 ( .A(n296), .B(n309), .Z(n312));
AN2 U499 ( .A(n351), .B(n487), .Z(n485));
OR2 U500 ( .A(n488), .B(n326), .Z(n487));
AN2 U501 ( .A(pi06), .B(n357), .Z(n488));
AN2 U502 ( .A(pi03), .B(pi28), .Z(n351));
AN2 U503 ( .A(n323), .B(n431), .Z(n483));
OR2 U504 ( .A(n489), .B(n490), .Z(po07));
OR2 U505 ( .A(pi33), .B(n311), .Z(n490));
IV2 U506 ( .A(n491), .Z(n311));
OR2 U507 ( .A(n492), .B(n493), .Z(n491));
OR2 U508 ( .A(n494), .B(n297), .Z(n493));
IV2 U509 ( .A(pi08), .Z(n297));
AN2 U510 ( .A(n375), .B(n369), .Z(n494));
IV2 U511 ( .A(n448), .Z(n375));
OR2 U512 ( .A(n477), .B(n366), .Z(n448));
OR2 U513 ( .A(n431), .B(n344), .Z(n477));
IV2 U514 ( .A(pi16), .Z(n344));
OR2 U515 ( .A(n495), .B(n496), .Z(n492));
OR2 U516 ( .A(pi00), .B(n339), .Z(n496));
AN2 U517 ( .A(n369), .B(n343), .Z(n339));
IV2 U518 ( .A(n497), .Z(n495));
OR2 U519 ( .A(n498), .B(pi40), .Z(n497));
AN2 U520 ( .A(n369), .B(pi41), .Z(n498));
OR2 U521 ( .A(po05), .B(n422), .Z(n489));
OR2 U522 ( .A(po25), .B(po24), .Z(n422));
OR2 U523 ( .A(n499), .B(n500), .Z(po06));
AN2 U524 ( .A(pi27), .B(n501), .Z(n500));
AN2 U525 ( .A(n502), .B(n503), .Z(n499));
AN2 U526 ( .A(n504), .B(n480), .Z(n503));
OR2 U527 ( .A(n431), .B(n366), .Z(n480));
IV2 U528 ( .A(pi14), .Z(n431));
AN2 U529 ( .A(n470), .B(n296), .Z(n504));
IV2 U530 ( .A(pi07), .Z(n296));
IV2 U531 ( .A(pi03), .Z(n470));
AN2 U532 ( .A(pi28), .B(n279), .Z(n502));
AN2 U533 ( .A(pi26), .B(n501), .Z(po04));
OR2 U534 ( .A(pi21), .B(n323), .Z(n501));
AN2 U535 ( .A(n505), .B(n506), .Z(po03));
AN2 U536 ( .A(n507), .B(n279), .Z(n506));
AN2 U537 ( .A(n369), .B(n283), .Z(n279));
IV2 U538 ( .A(pi21), .Z(n369));
AN2 U539 ( .A(n442), .B(n400), .Z(n507));
OR2 U540 ( .A(pi29), .B(pi40), .Z(n400));
OR2 U541 ( .A(n366), .B(n343), .Z(n442));
IV2 U542 ( .A(pi06), .Z(n343));
IV2 U543 ( .A(pi15), .Z(n366));
AN2 U544 ( .A(n326), .B(pi14), .Z(n505));
AN2 U545 ( .A(n508), .B(n443), .Z(n326));
IV2 U546 ( .A(n357), .Z(n443));
OR2 U547 ( .A(pi04), .B(pi20), .Z(n357));
OR2 U548 ( .A(n509), .B(n510), .Z(po02));
OR2 U549 ( .A(n511), .B(n512), .Z(n510));
AN2 U550 ( .A(pi44), .B(pi39), .Z(n512));
AN2 U551 ( .A(n513), .B(n514), .Z(n511));
AN2 U552 ( .A(n515), .B(n516), .Z(n514));
AN2 U553 ( .A(n309), .B(n306), .Z(n515));
IV2 U554 ( .A(pi10), .Z(n306));
AN2 U555 ( .A(n417), .B(pi25), .Z(n513));
IV2 U556 ( .A(n517), .Z(n417));
OR2 U557 ( .A(n518), .B(n519), .Z(n509));
AN2 U558 ( .A(n520), .B(pi09), .Z(n519));
AN2 U559 ( .A(n521), .B(pi02), .Z(n520));
AN2 U560 ( .A(pi31), .B(n508), .Z(n521));
IV2 U561 ( .A(pi22), .Z(n508));
AN2 U562 ( .A(n522), .B(n272), .Z(n518));
IV2 U563 ( .A(pi09), .Z(n272));
AN2 U564 ( .A(n523), .B(n524), .Z(n522));
AN2 U565 ( .A(n525), .B(pi35), .Z(n524));
AN2 U566 ( .A(pi21), .B(n526), .Z(n525));
IV2 U567 ( .A(pi13), .Z(n526));
AN2 U568 ( .A(pi01), .B(n283), .Z(n523));
AN2 U569 ( .A(n323), .B(n309), .Z(n283));
IV2 U570 ( .A(pi00), .Z(n309));
IV2 U571 ( .A(pi12), .Z(n323));
OR2 U572 ( .A(n527), .B(n528), .Z(po00));
AN2 U573 ( .A(po01), .B(n459), .Z(n528));
OR2 U574 ( .A(pi30), .B(pi42), .Z(po01));
AN2 U575 ( .A(pi25), .B(n529), .Z(n527));
OR2 U576 ( .A(n530), .B(n517), .Z(n529));
OR2 U577 ( .A(n531), .B(n532), .Z(n517));
OR2 U578 ( .A(n462), .B(n459), .Z(n532));
IV2 U579 ( .A(pi01), .Z(n459));
IV2 U580 ( .A(pi11), .Z(n462));
OR2 U581 ( .A(pi13), .B(pi12), .Z(n531));
AN2 U582 ( .A(n533), .B(n282), .Z(n530));
IV2 U583 ( .A(pi17), .Z(n282));
IV2 U584 ( .A(n516), .Z(n533));
OR2 U585 ( .A(pi09), .B(pi21), .Z(n516));
endmodule
module IV2(A, Z);
input A;
output Z;
assign Z = ~A;
endmodule
module AN2(A, B, Z);
input A, B;
output Z;
assign Z = A & B;
endmodule
module OR2(A, B, Z);
input A, B;
output Z;
assign Z = A | B;
endmodule

41
examples/smtbmc/glift/x1.ys Normal file
View File

@ -0,0 +1,41 @@
read_verilog x1.v
techmap
flatten
select x1_lev2
glift -create-instrumented-model
techmap
opt
rename x1_lev2 uut
cd ..
delete [AIONX][NVXR]2
read_verilog x1.v
techmap
flatten
select x1_lev2
glift -create-precise-model
techmap
opt
rename x1_lev2 spec
cd ..
delete [AIONX][NVXR]2
design -push-copy
miter -equiv spec uut miter
flatten
delete uut spec
techmap
opt
stat miter
qbfsat -O2 -write-solution x1.soln -solver yices -timeout 3600 -nocleanup -assume-outputs -assume-negative-polarity miter
design -pop
stat
copy uut solved
qbfsat -specialize-from-file x1.soln solved
opt solved
miter -equiv spec solved satmiter
flatten
sat -prove trigger 0 satmiter
delete satmiter
stat
shell

2
frontends/aiger/aigerparse.cc
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
* 2019 Eddie Hung <eddie@fpgeh.com>
*
* Permission to use, copy, modify, and/or distribute this software for any

2
frontends/aiger/aigerparse.h
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
* 2019 Eddie Hung <eddie@fpgeh.com>
*
* Permission to use, copy, modify, and/or distribute this software for any

1
frontends/ast/Makefile.inc
View File

@ -3,4 +3,5 @@ OBJS += frontends/ast/ast.o
OBJS += frontends/ast/simplify.o
OBJS += frontends/ast/genrtlil.o
OBJS += frontends/ast/dpicall.o
OBJS += frontends/ast/ast_binding.o

311
frontends/ast/ast.cc
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
* Copyright (C) 2018 Ruben Undheim <ruben.undheim@gmail.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
@ -52,8 +52,10 @@ namespace AST_INTERNAL {
const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr = NULL;
RTLIL::SigSpec ignoreThisSignalsInInitial;
AstNode *current_always, *current_top_block, *current_block, *current_block_child;
AstModule *current_module;
Module *current_module;
bool current_always_clocked;
dict<std::string, int> current_memwr_count;
dict<std::string, pool<int>> current_memwr_visible;
}
// convert node types to string
@ -175,6 +177,7 @@ std::string AST::type2str(AstNodeType type)
X(AST_STRUCT)
X(AST_UNION)
X(AST_STRUCT_ITEM)
X(AST_BIND)
#undef X
default:
log_abort();
@ -196,7 +199,7 @@ bool AstNode::get_bool_attribute(RTLIL::IdString id)
// create new node (AstNode constructor)
// (the optional child arguments make it easier to create AST trees)
AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2, AstNode *child3)
AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2, AstNode *child3, AstNode *child4)
{
static unsigned int hashidx_count = 123456789;
hashidx_count = mkhash_xorshift(hashidx_count);
@ -233,6 +236,8 @@ AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2, AstNode *ch
children.push_back(child2);
if (child3)
children.push_back(child3);
if (child4)
children.push_back(child4);
}
// create a (deep recursive) copy of a node
@ -317,6 +322,8 @@ void AstNode::dumpAst(FILE *f, std::string indent) const
fprintf(f, " reg");
if (is_signed)
fprintf(f, " signed");
if (is_unsized)
fprintf(f, " unsized");
if (basic_prep)
fprintf(f, " basic_prep");
if (lookahead)
@ -847,7 +854,7 @@ RTLIL::Const AstNode::bitsAsConst(int width)
return bitsAsConst(width, is_signed);
}
RTLIL::Const AstNode::asAttrConst()
RTLIL::Const AstNode::asAttrConst() const
{
log_assert(type == AST_CONSTANT);
@ -862,8 +869,17 @@ RTLIL::Const AstNode::asAttrConst()
return val;
}
RTLIL::Const AstNode::asParaConst()
RTLIL::Const AstNode::asParaConst() const
{
if (type == AST_REALVALUE)
{
AstNode *strnode = AstNode::mkconst_str(stringf("%f", realvalue));
RTLIL::Const val = strnode->asAttrConst();
val.flags |= RTLIL::CONST_FLAG_REAL;
delete strnode;
return val;
}
RTLIL::Const val = asAttrConst();
if (is_signed)
val.flags |= RTLIL::CONST_FLAG_SIGNED;
@ -968,8 +984,15 @@ void AST::set_src_attr(RTLIL::AttrObject *obj, const AstNode *ast)
obj->attributes[ID::src] = ast->loc_string();
}
// create a new AstModule from an AST_MODULE AST node
static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast = NULL, bool quiet = false)
static bool param_has_no_default(const AstNode *param) {
const auto &children = param->children;
log_assert(param->type == AST_PARAMETER);
log_assert(children.size() <= 2);
return children.empty() ||
(children.size() == 1 && children[0]->type == AST_RANGE);
}
static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool defer, AstNode *original_ast = NULL, bool quiet = false)
{
log_assert(current_scope.empty());
log_assert(ast->type == AST_MODULE || ast->type == AST_INTERFACE);
@ -980,11 +1003,13 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
log("Generating RTLIL representation for module `%s'.\n", ast->str.c_str());
}
current_module = new AstModule;
current_module->ast = NULL;
current_module->name = ast->str;
set_src_attr(current_module, ast);
current_module->set_bool_attribute(ID::cells_not_processed);
AstModule *module = new AstModule;
current_module = module;
module->ast = NULL;
module->name = ast->str;
set_src_attr(module, ast);
module->set_bool_attribute(ID::cells_not_processed);
current_ast_mod = ast;
AstNode *ast_before_simplify;
@ -1006,6 +1031,10 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
if (!defer)
{
for (const AstNode *node : ast->children)
if (node->type == AST_PARAMETER && param_has_no_default(node))
log_file_error(node->filename, node->location.first_line, "Parameter `%s' has no default value and has not been overridden!\n", node->str.c_str());
bool blackbox_module = flag_lib;
if (!blackbox_module && !flag_noblackbox) {
@ -1023,7 +1052,11 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
}
}
// simplify this module or interface using the current design as context
// for lookup up ports and wires within cells
set_simplify_design_context(design);
while (ast->simplify(!flag_noopt, false, false, 0, -1, false, false)) { }
set_simplify_design_context(nullptr);
if (flag_dump_ast2) {
log("Dumping AST after simplification:\n");
@ -1120,7 +1153,7 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
for (auto &attr : ast->attributes) {
if (attr.second->type != AST_CONSTANT)
log_file_error(ast->filename, ast->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
current_module->attributes[attr.first] = attr.second->asAttrConst();
module->attributes[attr.first] = attr.second->asAttrConst();
}
for (size_t i = 0; i < ast->children.size(); i++) {
AstNode *node = ast->children[i];
@ -1148,35 +1181,93 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
for (auto &attr : ast->attributes) {
if (attr.second->type != AST_CONSTANT)
continue;
current_module->attributes[attr.first] = attr.second->asAttrConst();
module->attributes[attr.first] = attr.second->asAttrConst();
}
for (const AstNode *node : ast->children)
if (node->type == AST_PARAMETER)
current_module->avail_parameters(node->str);
}
if (ast->type == AST_INTERFACE)
current_module->set_bool_attribute(ID::is_interface);
current_module->ast = ast_before_simplify;
current_module->nolatches = flag_nolatches;
current_module->nomeminit = flag_nomeminit;
current_module->nomem2reg = flag_nomem2reg;
current_module->mem2reg = flag_mem2reg;
current_module->noblackbox = flag_noblackbox;
current_module->lib = flag_lib;
current_module->nowb = flag_nowb;
current_module->noopt = flag_noopt;
current_module->icells = flag_icells;
current_module->pwires = flag_pwires;
current_module->autowire = flag_autowire;
current_module->fixup_ports();
module->set_bool_attribute(ID::is_interface);
module->ast = ast_before_simplify;
module->nolatches = flag_nolatches;
module->nomeminit = flag_nomeminit;
module->nomem2reg = flag_nomem2reg;
module->mem2reg = flag_mem2reg;
module->noblackbox = flag_noblackbox;
module->lib = flag_lib;
module->nowb = flag_nowb;
module->noopt = flag_noopt;
module->icells = flag_icells;
module->pwires = flag_pwires;
module->autowire = flag_autowire;
module->fixup_ports();
if (flag_dump_rtlil) {
log("Dumping generated RTLIL:\n");
log_module(current_module);
log_module(module);
log("--- END OF RTLIL DUMP ---\n");
}
design->add(current_module);
return current_module;
}
RTLIL::Module *
AST_INTERNAL::process_and_replace_module(RTLIL::Design *design,
RTLIL::Module *old_module,
AstNode *new_ast,
AstNode *original_ast)
{
// The old module will be deleted. Rename and mark for deletion, using
// a static counter to make sure we get a unique name.
static unsigned counter;
std::ostringstream new_name;
new_name << old_module->name.str()
<< "_before_process_and_replace_module_"
<< counter;
++counter;
design->rename(old_module, new_name.str());
old_module->set_bool_attribute(ID::to_delete);
// Check if the module was the top module. If it was, we need to remove
// the top attribute and put it on the new module.
bool is_top = false;
if (old_module->get_bool_attribute(ID::initial_top)) {
old_module->attributes.erase(ID::initial_top);
is_top = true;
}
// Generate RTLIL from AST for the new module and add to the design:
RTLIL::Module* new_module = process_module(design, new_ast, false, original_ast);
if (is_top)
new_module->set_bool_attribute(ID::top);
return new_module;
}
// renames identifiers in tasks and functions within a package
static void rename_in_package_stmts(AstNode *pkg)
{
std::unordered_set<std::string> idents;
for (AstNode *item : pkg->children)
idents.insert(item->str);
std::function<void(AstNode*)> rename =
[&rename, &idents, pkg](AstNode *node) {
for (AstNode *child : node->children) {
if (idents.count(child->str))
child->str = pkg->str + "::" + child->str.substr(1);
rename(child);
}
};
for (AstNode *item : pkg->children)
if (item->type == AST_FUNCTION || item->type == AST_TASK)
rename(item);
}
// create AstModule instances for all modules in the AST tree and add them to 'design'
void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil,
bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool noblackbox, bool lib, bool nowb, bool noopt, bool icells, bool pwires, bool nooverwrite, bool overwrite, bool defer, bool autowire)
@ -1202,12 +1293,12 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
flag_autowire = autowire;
log_assert(current_ast->type == AST_DESIGN);
for (auto it = current_ast->children.begin(); it != current_ast->children.end(); it++)
for (AstNode *child : current_ast->children)
{
if ((*it)->type == AST_MODULE || (*it)->type == AST_INTERFACE)
if (child->type == AST_MODULE || child->type == AST_INTERFACE)
{
for (auto n : design->verilog_globals)
(*it)->children.push_back(n->clone());
child->children.push_back(n->clone());
// append nodes from previous packages using package-qualified names
for (auto &n : design->verilog_packages) {
@ -1222,45 +1313,63 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
} else {
cloned_node->str = n->str + std::string("::") + cloned_node->str.substr(1);
}
(*it)->children.push_back(cloned_node);
child->children.push_back(cloned_node);
}
}
if (flag_icells && (*it)->str.compare(0, 2, "\\$") == 0)
(*it)->str = (*it)->str.substr(1);
if (flag_icells && child->str.compare(0, 2, "\\$") == 0)
child->str = child->str.substr(1);
if (defer)
(*it)->str = "$abstract" + (*it)->str;
bool defer_local = defer;
if (!defer_local)
for (const AstNode *node : child->children)
if (node->type == AST_PARAMETER && param_has_no_default(node))
{
log("Deferring `%s' because it contains parameter(s) without defaults.\n", child->str.c_str());
defer_local = true;
break;
}
if (design->has((*it)->str)) {
RTLIL::Module *existing_mod = design->module((*it)->str);
if (defer_local)
child->str = "$abstract" + child->str;
if (design->has(child->str)) {
RTLIL::Module *existing_mod = design->module(child->str);
if (!nooverwrite && !overwrite && !existing_mod->get_blackbox_attribute()) {
log_file_error((*it)->filename, (*it)->location.first_line, "Re-definition of module `%s'!\n", (*it)->str.c_str());
log_file_error(child->filename, child->location.first_line, "Re-definition of module `%s'!\n", child->str.c_str());
} else if (nooverwrite) {
log("Ignoring re-definition of module `%s' at %s.\n",
(*it)->str.c_str(), (*it)->loc_string().c_str());
child->str.c_str(), child->loc_string().c_str());
continue;
} else {
log("Replacing existing%s module `%s' at %s.\n",
existing_mod->get_bool_attribute(ID::blackbox) ? " blackbox" : "",
(*it)->str.c_str(), (*it)->loc_string().c_str());
child->str.c_str(), child->loc_string().c_str());
design->remove(existing_mod);
}
}
design->add(process_module(*it, defer));
process_module(design, child, defer_local);
current_ast_mod = nullptr;
}
else if ((*it)->type == AST_PACKAGE) {
else if (child->type == AST_PACKAGE) {
// process enum/other declarations
(*it)->simplify(true, false, false, 1, -1, false, false);
design->verilog_packages.push_back((*it)->clone());
child->simplify(true, false, false, 1, -1, false, false);
rename_in_package_stmts(child);
design->verilog_packages.push_back(child->clone());
current_scope.clear();
}
else if (child->type == AST_BIND) {
// top-level bind construct
for (RTLIL::Binding *binding : child->genBindings())
design->add(binding);
}
else {
// must be global definition
(*it)->simplify(false, false, false, 1, -1, false, false); //process enum/other declarations
design->verilog_globals.push_back((*it)->clone());
if (child->type == AST_PARAMETER)
child->type = AST_LOCALPARAM; // cannot be overridden
design->verilog_globals.push_back(child->clone());
current_scope.clear();
}
}
@ -1351,13 +1460,32 @@ void AST::explode_interface_port(AstNode *module_ast, RTLIL::Module * intfmodule
}
}
// AstModules may contain cells marked with ID::reprocess_after, which indicates
// that it should be reprocessed once the specified module has been elaborated.
bool AstModule::reprocess_if_necessary(RTLIL::Design *design)
{
for (const RTLIL::Cell *cell : cells())
{
std::string modname = cell->get_string_attribute(ID::reprocess_after);
if (modname.empty())
continue;
if (design->module(modname) || design->module("$abstract" + modname)) {
log("Reprocessing module %s because instantiated module %s has become available.\n",
log_id(name), log_id(modname));
loadconfig();
process_and_replace_module(design, this, ast, NULL);
return true;
}
}
return false;
}
// When an interface instance is found in a module, the whole RTLIL for the module will be rederived again
// from AST. The interface members are copied into the AST module with the prefix of the interface.
void AstModule::reprocess_module(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module*> &local_interfaces)
void AstModule::expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module*> &local_interfaces)
{
loadconfig();
bool is_top = false;
AstNode *new_ast = ast->clone();
for (auto &intf : local_interfaces) {
std::string intfname = intf.first.str();
@ -1414,29 +1542,15 @@ void AstModule::reprocess_module(RTLIL::Design *design, const dict<RTLIL::IdStri
}
}
// The old module will be deleted. Rename and mark for deletion:
std::string original_name = this->name.str();
std::string changed_name = original_name + "_before_replacing_local_interfaces";
design->rename(this, changed_name);
this->set_bool_attribute(ID::to_delete);
// Generate RTLIL from AST for the new module and add to the design,
// renaming this module to move it out of the way.
RTLIL::Module* new_module =
process_and_replace_module(design, this, new_ast, ast_before_replacing_interface_ports);
// Check if the module was the top module. If it was, we need to remove the top attribute and put it on the
// new module.
if (this->get_bool_attribute(ID::initial_top)) {
this->attributes.erase(ID::initial_top);
is_top = true;
}
// Generate RTLIL from AST for the new module and add to the design:
AstModule *newmod = process_module(new_ast, false, ast_before_replacing_interface_ports);
delete(new_ast);
design->add(newmod);
RTLIL::Module* mod = design->module(original_name);
if (is_top)
mod->set_bool_attribute(ID::top);
delete new_ast;
// Set the attribute "interfaces_replaced_in_module" so that it does not happen again.
mod->set_bool_attribute(ID::interfaces_replaced_in_module);
new_module->set_bool_attribute(ID::interfaces_replaced_in_module);
}
// create a new parametric module (when needed) and return the name of the generated module - WITH support for interfaces
@ -1486,7 +1600,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
explode_interface_port(new_ast, intfmodule, intfname, modport);
}
design->add(process_module(new_ast, false));
process_module(design, new_ast, false);
design->module(modname)->check();
RTLIL::Module* mod = design->module(modname);
@ -1537,7 +1651,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
if (!design->has(modname)) {
new_ast->str = modname;
design->add(process_module(new_ast, false, NULL, quiet));
process_module(design, new_ast, false, NULL, quiet);
design->module(modname)->check();
} else if (!quiet) {
log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
@ -1547,6 +1661,40 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
return modname;
}
static std::string serialize_param_value(const RTLIL::Const &val) {
std::string res;
if (val.flags & RTLIL::ConstFlags::CONST_FLAG_STRING)
res.push_back('t');
if (val.flags & RTLIL::ConstFlags::CONST_FLAG_SIGNED)
res.push_back('s');
if (val.flags & RTLIL::ConstFlags::CONST_FLAG_REAL)
res.push_back('r');
res += stringf("%d", GetSize(val));
res.push_back('\'');
for (int i = GetSize(val) - 1; i >= 0; i--) {
switch (val.bits[i]) {
case RTLIL::State::S0: res.push_back('0'); break;
case RTLIL::State::S1: res.push_back('1'); break;
case RTLIL::State::Sx: res.push_back('x'); break;
case RTLIL::State::Sz: res.push_back('z'); break;
case RTLIL::State::Sa: res.push_back('?'); break;
case RTLIL::State::Sm: res.push_back('m'); break;
}
}
return res;
}
std::string AST::derived_module_name(std::string stripped_name, const std::vector<std::pair<RTLIL::IdString, RTLIL::Const>> &parameters) {
std::string para_info;
for (const auto &elem : parameters)
para_info += stringf("%s=%s", elem.first.c_str(), serialize_param_value(elem.second).c_str());
if (para_info.size() > 60)
return "$paramod$" + sha1(para_info) + stripped_name;
else
return "$paramod" + stripped_name + para_info;
}
// create a new parametric module (when needed) and return the name of the generated module
std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, AstNode **new_ast_out, bool quiet)
{
@ -1555,9 +1703,8 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
if (stripped_name.compare(0, 9, "$abstract") == 0)
stripped_name = stripped_name.substr(9);
std::string para_info;
int para_counter = 0;
std::vector<std::pair<RTLIL::IdString, RTLIL::Const>> named_parameters;
for (const auto child : ast->children) {
if (child->type != AST_PARAMETER)
continue;
@ -1566,25 +1713,21 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
if (it != parameters.end()) {
if (!quiet)
log("Parameter %s = %s\n", child->str.c_str(), log_signal(it->second));
para_info += stringf("%s=%s", child->str.c_str(), log_signal(it->second));
named_parameters.emplace_back(child->str, it->second);
continue;
}
it = parameters.find(stringf("$%d", para_counter));
if (it != parameters.end()) {
if (!quiet)
log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(it->second));
para_info += stringf("%s=%s", child->str.c_str(), log_signal(it->second));
named_parameters.emplace_back(child->str, it->second);
continue;
}
}
std::string modname;
if (parameters.size() == 0)
modname = stripped_name;
else if (para_info.size() > 60)
modname = "$paramod$" + sha1(para_info) + stripped_name;
else
modname = "$paramod" + stripped_name + para_info;
std::string modname = stripped_name;
if (parameters.size()) // not named_parameters to cover hierarchical defparams
modname = derived_module_name(stripped_name, named_parameters);
if (design->has(modname))
return modname;
@ -1619,6 +1762,8 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
}
continue;
rewrite_parameter:
if (param_has_no_default(child))
child->children.insert(child->children.begin(), nullptr);
delete child->children.at(0);
if ((it->second.flags & RTLIL::CONST_FLAG_REAL) != 0) {
child->children[0] = new AstNode(AST_REALVALUE);

50
frontends/ast/ast.h
View File

@ -1,7 +1,7 @@
/* -*- c++ -*-
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -160,7 +160,8 @@ namespace AST
AST_TYPEDEF,
AST_STRUCT,
AST_UNION,
AST_STRUCT_ITEM
AST_STRUCT_ITEM,
AST_BIND
};
struct AstSrcLocType {
@ -220,7 +221,7 @@ namespace AST
AstSrcLocType location;
// creating and deleting nodes
AstNode(AstNodeType type = AST_NONE, AstNode *child1 = NULL, AstNode *child2 = NULL, AstNode *child3 = NULL);
AstNode(AstNodeType type = AST_NONE, AstNode *child1 = nullptr, AstNode *child2 = nullptr, AstNode *child3 = nullptr, AstNode *child4 = nullptr);
AstNode *clone() const;
void cloneInto(AstNode *other) const;
void delete_children();
@ -261,6 +262,7 @@ namespace AST
void mem2reg_remove(pool<AstNode*> &mem2reg_set, vector<AstNode*> &delnodes);
void meminfo(int &mem_width, int &mem_size, int &addr_bits);
bool detect_latch(const std::string &var);
const RTLIL::Module* lookup_cell_module();
// additional functionality for evaluating constant functions
struct varinfo_t {
@ -283,6 +285,9 @@ namespace AST
void dumpAst(FILE *f, std::string indent) const;
void dumpVlog(FILE *f, std::string indent) const;
// Generate RTLIL for a bind construct
std::vector<RTLIL::Binding *> genBindings() const;
// used by genRTLIL() for detecting expression width and sign
void detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *found_real = NULL);
void detectSignWidth(int &width_hint, bool &sign_hint, bool *found_real = NULL);
@ -291,7 +296,7 @@ namespace AST
// for expressions the resulting signal vector is returned
// all generated cell instances, etc. are written to the RTLIL::Module pointed to by AST_INTERNAL::current_module
RTLIL::SigSpec genRTLIL(int width_hint = -1, bool sign_hint = false);
RTLIL::SigSpec genWidthRTLIL(int width, const dict<RTLIL::SigBit, RTLIL::SigBit> *new_subst_ptr = NULL);
RTLIL::SigSpec genWidthRTLIL(int width, bool sgn, const dict<RTLIL::SigBit, RTLIL::SigBit> *new_subst_ptr = NULL);
// compare AST nodes
bool operator==(const AstNode &other) const;
@ -309,8 +314,8 @@ namespace AST
RTLIL::Const bitsAsConst(int width, bool is_signed);
RTLIL::Const bitsAsConst(int width = -1);
RTLIL::Const bitsAsUnsizedConst(int width);
RTLIL::Const asAttrConst();
RTLIL::Const asParaConst();
RTLIL::Const asAttrConst() const;
RTLIL::Const asParaConst() const;
uint64_t asInt(bool is_signed);
bool bits_only_01() const;
bool asBool() const;
@ -326,6 +331,9 @@ namespace AST
// helpers for locations
std::string loc_string() const;
// Helper for looking up identifiers which are prefixed with the current module name
std::string try_pop_module_prefix() const;
};
// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
@ -341,7 +349,8 @@ namespace AST
RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail) override;
RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail) override;
std::string derive_common(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, AstNode **new_ast_out, bool quiet = false);
void reprocess_module(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces) override;
void expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces) override;
bool reprocess_if_necessary(RTLIL::Design *design) override;
RTLIL::Module *clone() const override;
void loadconfig() const;
};
@ -367,6 +376,17 @@ namespace AST
// Helper for setting the src attribute.
void set_src_attr(RTLIL::AttrObject *obj, const AstNode *ast);
// struct helper exposed from simplify for genrtlil
AstNode *make_struct_member_range(AstNode *node, AstNode *member_node);
// generate standard $paramod... derived module name; parameters should be
// in the order they are declared in the instantiated module
std::string derived_module_name(std::string stripped_name, const std::vector<std::pair<RTLIL::IdString, RTLIL::Const>> &parameters);
// used to provide simplify() access to the current design for looking up
// modules, ports, wires, etc.
void set_simplify_design_context(const RTLIL::Design *design);
}
namespace AST_INTERNAL
@ -379,10 +399,24 @@ namespace AST_INTERNAL
extern const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr;
extern RTLIL::SigSpec ignoreThisSignalsInInitial;
extern AST::AstNode *current_always, *current_top_block, *current_block, *current_block_child;
extern AST::AstModule *current_module;
extern RTLIL::Module *current_module;
extern bool current_always_clocked;
extern dict<std::string, int> current_memwr_count;
extern dict<std::string, pool<int>> current_memwr_visible;
struct LookaheadRewriter;
struct ProcessGenerator;
// Create and add a new AstModule from new_ast, then use it to replace
// old_module in design, renaming old_module to move it out of the way.
// Return the new module.
//
// If original_ast is not null, it will be used as the AST node for the
// new module. Otherwise, new_ast will be used.
RTLIL::Module *
process_and_replace_module(RTLIL::Design *design,
RTLIL::Module *old_module,
AST::AstNode *new_ast,
AST::AstNode *original_ast = nullptr);
}
YOSYS_NAMESPACE_END

49
frontends/ast/ast_binding.cc Normal file
View File

@ -0,0 +1,49 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "ast_binding.h"
#include "ast.h"
YOSYS_NAMESPACE_BEGIN
using namespace AST_INTERNAL;
AST::Binding::Binding(RTLIL::IdString target_type,
RTLIL::IdString target_name,
const AstNode &cell)
: RTLIL::Binding(target_type, target_name),
ast_node(cell.clone())
{
log_assert(cell.type == AST_CELL);
}
std::string
AST::Binding::describe() const
{
std::ostringstream oss;
oss << "directive to bind " << ast_node->str
<< " to " << target_name.str();
if (!target_type.empty())
oss << " (target type: "
<< target_type.str()
<< ")";
return oss.str();
}
PRIVATE_NAMESPACE_END

58
frontends/ast/ast_binding.h Normal file
View File

@ -0,0 +1,58 @@
/* -*- c++ -*-
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* ---
*
* This header declares the AST::Binding class
*
* This is used to support the bind directive and is to RTLIL::Binding as
* AST::AstModule is to RTLIL::Module, holding a syntax-level representation of
* cells until we get to a stage where they make sense. In the case of a bind
* directive, this is when we elaborate the design in the hierarchy pass.
*
*/
#ifndef AST_BINDING_H
#define AST_BINDING_H
#include "kernel/rtlil.h"
#include "kernel/binding.h"
#include <memory>
YOSYS_NAMESPACE_BEGIN
namespace AST
{
class Binding : public RTLIL::Binding
{
public:
Binding(RTLIL::IdString target_type,
RTLIL::IdString target_name,
const AstNode &cell);
std::string describe() const override;
private:
// The syntax-level representation of the cell to be bound.
std::unique_ptr<AstNode> ast_node;
};
}
YOSYS_NAMESPACE_END
#endif

2
frontends/ast/dpicall.cc
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

268
frontends/ast/genrtlil.cc
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -28,8 +28,10 @@
#include "kernel/log.h"
#include "kernel/utils.h"
#include "kernel/binding.h"
#include "libs/sha1/sha1.h"
#include "ast.h"
#include "ast_binding.h"
#include <sstream>
#include <stdarg.h>
@ -319,16 +321,14 @@ struct AST_INTERNAL::ProcessGenerator
LookaheadRewriter la_rewriter(always);
// generate process and simple root case
proc = new RTLIL::Process;
proc = current_module->addProcess(stringf("$proc$%s:%d$%d", always->filename.c_str(), always->location.first_line, autoidx++));
set_src_attr(proc, always);
proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->location.first_line, autoidx++);
for (auto &attr : always->attributes) {
if (attr.second->type != AST_CONSTANT)
log_file_error(always->filename, always->location.first_line, "Attribute `%s' with non-constant value!\n",
attr.first.c_str());
proc->attributes[attr.first] = attr.second->asAttrConst();
}
current_module->processes[proc->name] = proc;
current_case = &proc->root_case;
// create initial temporary signal for all output registers
@ -399,6 +399,9 @@ struct AST_INTERNAL::ProcessGenerator
if (child->type == AST_BLOCK)
processAst(child);
for (auto sync: proc->syncs)
processMemWrites(sync);
if (initSyncSignals.size() > 0)
{
RTLIL::SyncRule *sync = new RTLIL::SyncRule;
@ -563,7 +566,7 @@ struct AST_INTERNAL::ProcessGenerator
case AST_ASSIGN_LE:
{
RTLIL::SigSpec unmapped_lvalue = ast->children[0]->genRTLIL(), lvalue = unmapped_lvalue;
RTLIL::SigSpec rvalue = ast->children[1]->genWidthRTLIL(lvalue.size(), &subst_rvalue_map.stdmap());
RTLIL::SigSpec rvalue = ast->children[1]->genWidthRTLIL(lvalue.size(), true, &subst_rvalue_map.stdmap());
pool<SigBit> lvalue_sigbits;
for (int i = 0; i < GetSize(lvalue); i++) {
@ -590,9 +593,13 @@ struct AST_INTERNAL::ProcessGenerator
case AST_CASE:
{
int width_hint;
bool sign_hint;
ast->detectSignWidth(width_hint, sign_hint);
RTLIL::SwitchRule *sw = new RTLIL::SwitchRule;
set_src_attr(sw, ast);
sw->signal = ast->children[0]->genWidthRTLIL(-1, &subst_rvalue_map.stdmap());
sw->signal = ast->children[0]->genWidthRTLIL(width_hint, sign_hint, &subst_rvalue_map.stdmap());
current_case->switches.push_back(sw);
for (auto &attr : ast->attributes) {
@ -634,7 +641,7 @@ struct AST_INTERNAL::ProcessGenerator
else if (node->type == AST_BLOCK)
processAst(node);
else
current_case->compare.push_back(node->genWidthRTLIL(sw->signal.size(), &subst_rvalue_map.stdmap()));
current_case->compare.push_back(node->genWidthRTLIL(width_hint, sign_hint, &subst_rvalue_map.stdmap()));
}
if (default_case != current_case)
sw->cases.push_back(current_case);
@ -698,8 +705,99 @@ struct AST_INTERNAL::ProcessGenerator
log_abort();
}
}
void processMemWrites(RTLIL::SyncRule *sync)
{
// Maps per-memid AST_MEMWR IDs to indices in the mem_write_actions array.
dict<std::pair<std::string, int>, int> port_map;
for (auto child : always->children)
if (child->type == AST_MEMWR)
{
std::string memid = child->str;
int portid = child->children[3]->asInt(false);
int cur_idx = GetSize(sync->mem_write_actions);
RTLIL::MemWriteAction action;
set_src_attr(&action, child);
action.memid = memid;
action.address = child->children[0]->genWidthRTLIL(-1, true, &subst_rvalue_map.stdmap());
action.data = child->children[1]->genWidthRTLIL(current_module->memories[memid]->width, true, &subst_rvalue_map.stdmap());
action.enable = child->children[2]->genWidthRTLIL(-1, true, &subst_rvalue_map.stdmap());
RTLIL::Const orig_priority_mask = child->children[4]->bitsAsConst();
RTLIL::Const priority_mask = RTLIL::Const(0, cur_idx);
for (int i = 0; i < portid; i++) {
int new_bit = port_map[std::make_pair(memid, i)];
priority_mask.bits[new_bit] = orig_priority_mask.bits[i];
}
action.priority_mask = priority_mask;
sync->mem_write_actions.push_back(action);
port_map[std::make_pair(memid, portid)] = cur_idx;
}
}
};
// Generate RTLIL for a bind construct
//
// The AST node will have one or more AST_IDENTIFIER children, which were added
// by bind_target_instance in the parser. After these, it will have one or more
// cells, as parsed by single_cell. These have type AST_CELL.
//
// If there is more than one AST_IDENTIFIER, the first one should be considered
// a module identifier. If there is only one AST_IDENTIFIER, we can't tell at
// this point whether it's a module/interface name or the name of an instance
// because the correct interpretation depends on what's visible at elaboration
// time. For now, we just treat it as a target instance with unknown type, and
// we'll deal with the corner case in the hierarchy pass.
//
// To simplify downstream code, RTLIL::Binding only has a single target and
// single bound instance. If we see the syntax that allows more than one of
// either, we split it into multiple Binding objects.
std::vector<RTLIL::Binding *> AstNode::genBindings() const
{
// Partition children into identifiers and cells
int num_ids = 0;
for (int i = 0; i < GetSize(children); ++i) {
if (children[i]->type != AST_IDENTIFIER) {
log_assert(i > 0);
num_ids = i;
break;
}
}
// We should have found at least one child that's not an identifier
log_assert(num_ids > 0);
// Make sense of the identifiers, extracting a possible type name and a
// list of hierarchical IDs. We represent an unknown type with an empty
// string.
RTLIL::IdString tgt_type;
int first_tgt_inst = 0;
if (num_ids > 1) {
tgt_type = children[0]->str;
first_tgt_inst = 1;
}
std::vector<RTLIL::Binding *> ret;
// At this point, we know that children with index >= first_tgt_inst and
// index < num_ids are (hierarchical?) names of target instances. Make a
// binding object for each of them, and fill in the generated instance
// cells each time.
for (int i = first_tgt_inst; i < num_ids; ++i) {
const AstNode &tgt_child = *children[i];
for (int j = num_ids; j < GetSize(children); ++j) {
const AstNode &cell_child = *children[j];
log_assert(cell_child.type == AST_CELL);
ret.push_back(new AST::Binding(tgt_type, tgt_child.str,
cell_child));
}
}
return ret;
}
// detect sign and width of an expression
void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *found_real)
{
@ -732,8 +830,15 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
case AST_IDENTIFIER:
id_ast = id2ast;
if (id_ast == NULL && current_scope.count(str))
id_ast = current_scope.at(str);
if (!id_ast) {
if (current_scope.count(str))
id_ast = current_scope[str];
else {
std::string alt = try_pop_module_prefix();
if (current_scope.count(alt))
id_ast = current_scope[alt];
}
}
if (!id_ast)
log_file_error(filename, location.first_line, "Failed to resolve identifier %s for width detection!\n", str.c_str());
if (id_ast->type == AST_PARAMETER || id_ast->type == AST_LOCALPARAM || id_ast->type == AST_ENUM_ITEM) {
@ -772,6 +877,10 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
this_width = id_ast->children[0]->range_left - id_ast->children[0]->range_right + 1;
if (children.size() > 1)
range = children[1];
} else if (id_ast->type == AST_STRUCT_ITEM) {
AstNode *tmp_range = make_struct_member_range(this, id_ast);
this_width = tmp_range->range_left - tmp_range->range_right + 1;
delete tmp_range;
} else
log_file_error(filename, location.first_line, "Failed to detect width for identifier %s!\n", str.c_str());
if (range) {
@ -823,7 +932,8 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
if (children.at(0)->type != AST_CONSTANT)
log_file_error(filename, location.first_line, "Static cast with non constant expression!\n");
children.at(1)->detectSignWidthWorker(width_hint, sign_hint);
width_hint = children.at(0)->bitsAsConst().as_int();
this_width = children.at(0)->bitsAsConst().as_int();
width_hint = max(width_hint, this_width);
if (width_hint <= 0)
log_file_error(filename, location.first_line, "Static cast with zero or negative size!\n");
break;
@ -923,6 +1033,40 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
width_hint = max(width_hint, this_width);
break;
case AST_CASE:
{
// This detects the _overall_ sign and width to be used for comparing
// the case expression with the case item expressions. The case
// expression and case item expressions are extended to the maximum
// width among them, and are only interpreted as signed if all of them
// are signed.
width_hint = -1;
sign_hint = true;
auto visit_case_expr = [&width_hint, &sign_hint] (AstNode *node) {
int sub_width_hint = -1;
bool sub_sign_hint = true;
node->detectSignWidth(sub_width_hint, sub_sign_hint);
width_hint = max(width_hint, sub_width_hint);
sign_hint &= sub_sign_hint;
};
visit_case_expr(children[0]);
for (size_t i = 1; i < children.size(); i++) {
AstNode *child = children[i];
for (AstNode *v : child->children)
if (v->type != AST_DEFAULT && v->type != AST_BLOCK)
visit_case_expr(v);
}
break;
}
case AST_PREFIX:
// Prefix nodes always resolve to identifiers in generate loops, so we
// can simply perform the resolution to determine the sign and width.
simplify(true, false, false, 1, -1, false, false);
log_assert(type == AST_IDENTIFIER);
detectSignWidthWorker(width_hint, sign_hint, found_real);
break;
case AST_FCALL:
if (str == "\\$anyconst" || str == "\\$anyseq" || str == "\\$allconst" || str == "\\$allseq") {
if (GetSize(children) == 1) {
@ -944,6 +1088,11 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
}
break;
}
if (str == "\\$size" || str == "\\$bits" || str == "\\$high" || str == "\\$low" || str == "\\$left" || str == "\\$right") {
width_hint = 32;
sign_hint = true;
break;
}
if (current_scope.count(str))
{
// This width detection is needed for function calls which are
@ -983,8 +1132,9 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
// everything should have been handled above -> print error if not.
default:
AstNode *current_scope_ast = current_ast_mod == nullptr ? current_ast : current_ast_mod;
for (auto f : log_files)
current_ast_mod->dumpAst(f, "verilog-ast> ");
current_scope_ast->dumpAst(f, "verilog-ast> ");
log_file_error(filename, location.first_line, "Don't know how to detect sign and width for %s node!\n", type2str(type).c_str());
}
@ -1000,6 +1150,12 @@ void AstNode::detectSignWidth(int &width_hint, bool &sign_hint, bool *found_real
if (found_real)
*found_real = false;
detectSignWidthWorker(width_hint, sign_hint, found_real);
constexpr int kWidthLimit = 1 << 24;
if (width_hint >= kWidthLimit)
log_file_error(filename, location.first_line,
"Expression width %d exceeds implementation limit of %d!\n",
width_hint, kWidthLimit);
}
static void check_unique_id(RTLIL::Module *module, RTLIL::IdString id,
@ -1227,7 +1383,15 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
RTLIL::Wire *wire = current_module->addWire(str);
set_src_attr(wire, this);
wire->name = str;
if (flag_autowire)
// If we are currently processing a bind directive which wires up
// signals or parameters explicitly, rather than with .*, then
// current_module will start out empty and we don't want to warn the
// user about it: we'll spot broken wiring later, when we run the
// hierarchy pass.
if (dynamic_cast<RTLIL::Binding*>(current_module)) {
/* nothing to do here */
} else if (flag_autowire)
log_file_warning(filename, location.first_line, "Identifier `%s' is implicitly declared.\n", str.c_str());
else
log_file_error(filename, location.first_line, "Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str());
@ -1367,13 +1531,20 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// changing the size of signal can be done directly using RTLIL::SigSpec
case AST_CAST_SIZE: {
RTLIL::SigSpec size = children[0]->genRTLIL();
RTLIL::SigSpec sig = children[1]->genRTLIL();
if (!size.is_fully_const())
log_file_error(filename, location.first_line, "Static cast with non constant expression!\n");
int width = size.as_int();
if (width <= 0)
log_file_error(filename, location.first_line, "Static cast with zero or negative size!\n");
sig.extend_u0(width, sign_hint);
// determine the *signedness* of the expression
int sub_width_hint = -1;
bool sub_sign_hint = true;
children[1]->detectSignWidth(sub_width_hint, sub_sign_hint);
// generate the signal given the *cast's* size and the
// *expression's* signedness
RTLIL::SigSpec sig = children[1]->genWidthRTLIL(width, sub_sign_hint);
// context may effect this node's signedness, but not that of the
// casted expression
is_signed = sign_hint;
return sig;
}
@ -1638,43 +1809,35 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
return RTLIL::SigSpec(wire);
}
// generate $memwr cells for memory write ports
case AST_MEMWR:
// generate $meminit cells
case AST_MEMINIT:
{
std::stringstream sstr;
sstr << (type == AST_MEMWR ? "$memwr$" : "$meminit$") << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
sstr << "$meminit$" << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
RTLIL::Cell *cell = current_module->addCell(sstr.str(), type == AST_MEMWR ? ID($memwr) : ID($meminit));
SigSpec en_sig = children[2]->genRTLIL();
RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($meminit_v2));
set_src_attr(cell, this);
int mem_width, mem_size, addr_bits;
id2ast->meminfo(mem_width, mem_size, addr_bits);
int num_words = 1;
if (type == AST_MEMINIT) {
if (children[2]->type != AST_CONSTANT)
log_file_error(filename, location.first_line, "Memory init with non-constant word count!\n");
num_words = int(children[2]->asInt(false));
cell->parameters[ID::WORDS] = RTLIL::Const(num_words);
}
if (children[3]->type != AST_CONSTANT)
log_file_error(filename, location.first_line, "Memory init with non-constant word count!\n");
int num_words = int(children[3]->asInt(false));
cell->parameters[ID::WORDS] = RTLIL::Const(num_words);
SigSpec addr_sig = children[0]->genRTLIL();
cell->setPort(ID::ADDR, addr_sig);
cell->setPort(ID::DATA, children[1]->genWidthRTLIL(current_module->memories[str]->width * num_words));
cell->setPort(ID::DATA, children[1]->genWidthRTLIL(current_module->memories[str]->width * num_words, true));
cell->setPort(ID::EN, en_sig);
cell->parameters[ID::MEMID] = RTLIL::Const(str);
cell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr_sig));
cell->parameters[ID::WIDTH] = RTLIL::Const(current_module->memories[str]->width);
if (type == AST_MEMWR) {
cell->setPort(ID::CLK, RTLIL::SigSpec(RTLIL::State::Sx, 1));
cell->setPort(ID::EN, children[2]->genRTLIL());
cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(0);
cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(0);
}
cell->parameters[ID::PRIORITY] = RTLIL::Const(autoidx-1);
}
break;
@ -1728,7 +1891,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_ASSIGN:
{
RTLIL::SigSpec left = children[0]->genRTLIL();
RTLIL::SigSpec right = children[1]->genWidthRTLIL(left.size());
RTLIL::SigSpec right = children[1]->genWidthRTLIL(left.size(), true);
if (left.has_const()) {
RTLIL::SigSpec new_left, new_right;
for (int i = 0; i < GetSize(left); i++)
@ -1768,21 +1931,15 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
continue;
}
if (child->type == AST_PARASET) {
int extra_const_flags = 0;
IdString paraname = child->str.empty() ? stringf("$%d", ++para_counter) : child->str;
if (child->children[0]->type == AST_REALVALUE) {
const AstNode *value = child->children[0];
if (value->type == AST_REALVALUE)
log_file_warning(filename, location.first_line, "Replacing floating point parameter %s.%s = %f with string.\n",
log_id(cell), log_id(paraname), child->children[0]->realvalue);
extra_const_flags = RTLIL::CONST_FLAG_REAL;
auto strnode = AstNode::mkconst_str(stringf("%f", child->children[0]->realvalue));
strnode->cloneInto(child->children[0]);
delete strnode;
}
if (child->children[0]->type != AST_CONSTANT)
log_id(cell), log_id(paraname), value->realvalue);
else if (value->type != AST_CONSTANT)
log_file_error(filename, location.first_line, "Parameter %s.%s with non-constant value!\n",
log_id(cell), log_id(paraname));
cell->parameters[paraname] = child->children[0]->asParaConst();
cell->parameters[paraname].flags |= extra_const_flags;
cell->parameters[paraname] = value->asParaConst();
continue;
}
if (child->type == AST_ARGUMENT) {
@ -1799,7 +1956,12 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
if (sig.is_wire()) {
// if the resulting SigSpec is a wire, its
// signedness should match that of the AstNode
log_assert(arg->is_signed == sig.as_wire()->is_signed);
if (arg->type == AST_IDENTIFIER && arg->id2ast && arg->id2ast->is_signed && !arg->is_signed)
// fully-sliced signed wire will be resolved
// once the module becomes available
log_assert(attributes.count(ID::reprocess_after));
else
log_assert(arg->is_signed == sig.as_wire()->is_signed);
} else if (arg->is_signed) {
// non-trivial signed nodes are indirected through
// signed wires to enable sign extension
@ -1898,6 +2060,13 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
}
} break;
case AST_BIND: {
// Read a bind construct. This should have one or more cells as children.
for (RTLIL::Binding *binding : genBindings())
current_module->add(binding);
break;
}
case AST_FCALL: {
if (str == "\\$anyconst" || str == "\\$anyseq" || str == "\\$allconst" || str == "\\$allseq")
{
@ -1943,8 +2112,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
default:
for (auto f : log_files)
current_ast_mod->dumpAst(f, "verilog-ast> ");
type_name = type2str(type);
log_file_error(filename, location.first_line, "Don't know how to generate RTLIL code for %s node!\n", type_name.c_str());
log_file_error(filename, location.first_line, "Don't know how to generate RTLIL code for %s node!\n", type2str(type).c_str());
}
return RTLIL::SigSpec();
@ -1953,14 +2121,14 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// this is a wrapper for AstNode::genRTLIL() when a specific signal width is requested and/or
// signals must be substituted before being used as input values (used by ProcessGenerator)
// note that this is using some global variables to communicate this special settings to AstNode::genRTLIL().
RTLIL::SigSpec AstNode::genWidthRTLIL(int width, const dict<RTLIL::SigBit, RTLIL::SigBit> *new_subst_ptr)
RTLIL::SigSpec AstNode::genWidthRTLIL(int width, bool sgn, const dict<RTLIL::SigBit, RTLIL::SigBit> *new_subst_ptr)
{
const dict<RTLIL::SigBit, RTLIL::SigBit> *backup_subst_ptr = genRTLIL_subst_ptr;
if (new_subst_ptr)
genRTLIL_subst_ptr = new_subst_ptr;
bool sign_hint = true;
bool sign_hint = sgn;
int width_hint = width;
detectSignWidthWorker(width_hint, sign_hint);
RTLIL::SigSpec sig = genRTLIL(width_hint, sign_hint);

686
frontends/ast/simplify.cc
View File

File diff suppressed because it is too large Load Diff

39
frontends/blif/blifparse.cc
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -65,17 +65,21 @@ static std::pair<RTLIL::IdString, int> wideports_split(std::string name)
for (int i = 0; i+1 < GetSize(name); i++) {
if (name[i] == '[')
pos = i;
else if (name[i] < '0' || name[i] > '9')
else if (name[i] != '-' && (name[i] < '0' || name[i] > '9'))
pos = -1;
else if (name[i] == '-' && ((i != pos+1) || name[i+1] == ']'))
pos = -1;
else if (i == pos+2 && name[i] == '0' && name[i-1] == '-')
pos = -1;
else if (i == pos+1 && name[i] == '0' && name[i+1] != ']')
pos = -1;
}
if (pos >= 0)
return std::pair<RTLIL::IdString, int>("\\" + name.substr(0, pos), atoi(name.c_str() + pos+1)+1);
return std::pair<RTLIL::IdString, int>("\\" + name.substr(0, pos), atoi(name.c_str() + pos+1));
failed:
return std::pair<RTLIL::IdString, int>("\\" + name, 0);
return std::pair<RTLIL::IdString, int>(RTLIL::IdString(), 0);
}
void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool run_clean, bool sop_mode, bool wideports)
@ -263,8 +267,8 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
if (wideports) {
std::pair<RTLIL::IdString, int> wp = wideports_split(p);
if (wp.second > 0) {
wideports_cache[wp.first].first = std::max(wideports_cache[wp.first].first, wp.second);
if (!wp.first.empty() && wp.second >= 0) {
wideports_cache[wp.first].first = std::max(wideports_cache[wp.first].first, wp.second + 1);
wideports_cache[wp.first].second = !strcmp(cmd, ".inputs");
}
}
@ -375,6 +379,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
IdString celltype = RTLIL::escape_id(p);
RTLIL::Cell *cell = module->addCell(NEW_ID, celltype);
RTLIL::Module *cell_mod = design->module(celltype);
dict<RTLIL::IdString, dict<int, SigBit>> cell_wideports_cache;
@ -387,10 +392,10 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
if (wideports) {
std::pair<RTLIL::IdString, int> wp = wideports_split(p);
if (wp.second > 0)
cell_wideports_cache[wp.first][wp.second-1] = blif_wire(q);
else
if (wp.first.empty())
cell->setPort(RTLIL::escape_id(p), *q ? blif_wire(q) : SigSpec());
else
cell_wideports_cache[wp.first][wp.second] = blif_wire(q);
} else {
cell->setPort(RTLIL::escape_id(p), *q ? blif_wire(q) : SigSpec());
}
@ -399,14 +404,26 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
for (auto &it : cell_wideports_cache)
{
int width = 0;
int offset = 0;
bool upto = false;
for (auto &b : it.second)
width = std::max(width, b.first + 1);
if (cell_mod) {
Wire *cell_port = cell_mod->wire(it.first);
if (cell_port && (cell_port->port_input || cell_port->port_output)) {
offset = cell_port->start_offset;
upto = cell_port->upto;
width = cell_port->width;
}
}
SigSpec sig;
for (int i = 0; i < width; i++) {
if (it.second.count(i))
sig.append(it.second.at(i));
int idx = offset + (upto ? width - 1 - i: i);
if (it.second.count(idx))
sig.append(it.second.at(idx));
else
sig.append(module->addWire(NEW_ID));
}

2
frontends/blif/blifparse.h
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

52
frontends/json/jsonparse.cc
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -539,6 +539,56 @@ void json_import(Design *design, string &modname, JsonNode *node)
json_parse_attr_param(cell->parameters, cell_node->data_dict.at("parameters"));
}
}
if (node->data_dict.count("memories"))
{
JsonNode *memories_node = node->data_dict.at("memories");
if (memories_node->type != 'D')
log_error("JSON memories node is not a dictionary.\n");
for (auto &memory_node_it : memories_node->data_dict)
{
IdString memory_name = RTLIL::escape_id(memory_node_it.first.c_str());
JsonNode *memory_node = memory_node_it.second;
RTLIL::Memory *mem = new RTLIL::Memory;
mem->name = memory_name;
if (memory_node->type != 'D')
log_error("JSON memory node '%s' is not a dictionary.\n", log_id(memory_name));
if (memory_node->data_dict.count("width") == 0)
log_error("JSON memory node '%s' has no width attribute.\n", log_id(memory_name));
JsonNode *width_node = memory_node->data_dict.at("width");
if (width_node->type != 'N')
log_error("JSON memory node '%s' has a non-number width.\n", log_id(memory_name));
mem->width = width_node->data_number;
if (memory_node->data_dict.count("size") == 0)
log_error("JSON memory node '%s' has no size attribute.\n", log_id(memory_name));
JsonNode *size_node = memory_node->data_dict.at("size");
if (size_node->type != 'N')
log_error("JSON memory node '%s' has a non-number size.\n", log_id(memory_name));
mem->size = size_node->data_number;
mem->start_offset = 0;
if (memory_node->data_dict.count("start_offset") != 0) {
JsonNode *val = memory_node->data_dict.at("start_offset");
if (val->type == 'N')
mem->start_offset = val->data_number;
}
if (memory_node->data_dict.count("attributes"))
json_parse_attr_param(mem->attributes, memory_node->data_dict.at("attributes"));
module->memories[mem->name] = mem;
}
}
// remove duplicates from connections array
pool<RTLIL::SigSig> unique_connections(module->connections_.begin(), module->connections_.end());
module->connections_ = std::vector<RTLIL::SigSig>(unique_connections.begin(), unique_connections.end());
}
struct JsonFrontend : public Frontend {

2
frontends/liberty/liberty.cc
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

2
frontends/rtlil/rtlil_frontend.cc
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

2
frontends/rtlil/rtlil_frontend.h
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

3
frontends/rtlil/rtlil_lexer.l
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -79,6 +79,7 @@ USING_YOSYS_NAMESPACE
"global" { return TOK_GLOBAL; }
"init" { return TOK_INIT; }
"update" { return TOK_UPDATE; }
"memwr" { return TOK_MEMWR; }
"process" { return TOK_PROCESS; }
"end" { return TOK_END; }

27
frontends/rtlil/rtlil_parser.y
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -22,6 +22,8 @@
*
*/
%require "3.0"
%{
#include <list>
#include "frontends/rtlil/rtlil_frontend.h"
@ -69,7 +71,7 @@ USING_YOSYS_NAMESPACE
%token TOK_AUTOIDX TOK_MODULE TOK_WIRE TOK_WIDTH TOK_INPUT TOK_OUTPUT TOK_INOUT
%token TOK_CELL TOK_CONNECT TOK_SWITCH TOK_CASE TOK_ASSIGN TOK_SYNC
%token TOK_LOW TOK_HIGH TOK_POSEDGE TOK_NEGEDGE TOK_EDGE TOK_ALWAYS TOK_GLOBAL TOK_INIT
%token TOK_UPDATE TOK_PROCESS TOK_END TOK_INVALID TOK_EOL TOK_OFFSET
%token TOK_UPDATE TOK_MEMWR TOK_PROCESS TOK_END TOK_INVALID TOK_EOL TOK_OFFSET
%token TOK_PARAMETER TOK_ATTRIBUTE TOK_MEMORY TOK_SIZE TOK_SIGNED TOK_REAL TOK_UPTO
%type <rsigspec> sigspec_list_reversed
@ -155,6 +157,7 @@ param_defval_stmt:
TOK_PARAMETER TOK_ID constant EOL {
current_module->avail_parameters($2);
current_module->parameter_default_values[$2] = *$3;
delete $3;
free($2);
};
@ -282,10 +285,8 @@ proc_stmt:
TOK_PROCESS TOK_ID EOL {
if (current_module->processes.count($2) != 0)
rtlil_frontend_yyerror(stringf("RTLIL error: redefinition of process %s.", $2).c_str());
current_process = new RTLIL::Process;
current_process->name = $2;
current_process = current_module->addProcess($2);
current_process->attributes = attrbuf;
current_module->processes[$2] = current_process;
switch_stack.clear();
switch_stack.push_back(&current_process->root_case.switches);
case_stack.clear();
@ -389,6 +390,22 @@ update_list:
delete $3;
delete $4;
} |
update_list attr_list TOK_MEMWR TOK_ID sigspec sigspec sigspec constant EOL {
RTLIL::MemWriteAction act;
act.attributes = attrbuf;
act.memid = $4;
act.address = *$5;
act.data = *$6;
act.enable = *$7;
act.priority_mask = *$8;
current_process->syncs.back()->mem_write_actions.push_back(std::move(act));
attrbuf.clear();
free($4);
delete $5;
delete $6;
delete $7;
delete $8;
} |
/* empty */;
constant:

2
frontends/verific/Makefile.inc
View File

@ -10,9 +10,11 @@ EXTRA_TARGETS += share/verific
share/verific:
$(P) rm -rf share/verific.new
$(Q) mkdir -p share/verific.new
ifneq ($(DISABLE_VERIFIC_VHDL),1)
$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_1987/. share/verific.new/vhdl_vdbs_1987
$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_1993/. share/verific.new/vhdl_vdbs_1993
$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_2008/. share/verific.new/vhdl_vdbs_2008
endif
$(Q) chmod -R a+rX share/verific.new
$(Q) mv share/verific.new share/verific

8
frontends/verific/README
View File

@ -1,11 +1,11 @@
This directory contains Verific bindings for Yosys.
Use Symbiotic EDA Suite if you need Yosys+Verifc.
https://www.symbioticeda.com/seda-suite
Use Tabby CAD Suite from YosysHQ if you need Yosys+Verifc.
https://www.yosyshq.com/
Contact office@symbioticeda.com for free evaluation
binaries of Symbiotic EDA Suite.
Contact YosysHQ at contact@yosyshq.com for free evaluation
binaries of Tabby CAD Suite.
Verific Features that should be enabled in your Verific library

521
frontends/verific/verific.cc
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -43,22 +43,25 @@ USING_YOSYS_NAMESPACE
#endif
#include "veri_file.h"
#include "vhdl_file.h"
#include "hier_tree.h"
#include "VeriModule.h"
#include "VeriWrite.h"
#include "VhdlUnits.h"
#include "VeriLibrary.h"
#if defined(YOSYSHQ_VERIFIC_INITSTATE) || defined(YOSYSHQ_VERIFIC_TEMPLATES) || defined(YOSYSHQ_VERIFIC_FORMALAPPS)
#include "VeriExtensions.h"
#ifdef VERIFIC_VHDL_SUPPORT
#include "vhdl_file.h"
#include "VhdlUnits.h"
#endif
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
#include "InitialAssertions.h"
#endif
#ifndef YOSYSHQ_VERIFIC_API_VERSION
# error "Only YosysHQ flavored Verific is supported. Please contact office@yosyshq.com for commercial support for Yosys+Verific."
#endif
#if YOSYSHQ_VERIFIC_API_VERSION < 20210103
#if YOSYSHQ_VERIFIC_API_VERSION < 20210801
# error "Please update your version of YosysHQ flavored Verific."
#endif
@ -175,8 +178,10 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
return;
if (!type_range->IsTypeEnum())
return;
#ifdef VERIFIC_VHDL_SUPPORT
if (nl->IsFromVhdl() && strcmp(type_range->GetTypeName(), "STD_LOGIC") == 0)
return;
#endif
auto type_name = type_range->GetTypeName();
if (!type_name)
return;
@ -193,7 +198,7 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
p = nullptr;
else
for (auto q = p+2; *q != '\0'; q++)
if (*q != '0' && *q != '1') {
if (*q != '0' && *q != '1' && *q != 'x' && *q != 'z') {
p = nullptr;
break;
}
@ -202,6 +207,7 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
log_error("Expected TypeRange value '%s' to be of form <decimal>'b<binary>.\n", v);
attributes.emplace(stringf("\\enum_value_%s", p+2), RTLIL::escape_id(k));
}
#ifdef VERIFIC_VHDL_SUPPORT
else if (nl->IsFromVhdl()) {
// Expect "<binary>" or plain <binary>
auto p = v;
@ -237,6 +243,7 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
if (p == nullptr)
log_error("Expected TypeRange value '%s' to be of form \"<binary>\" or <binary>.\n", v);
}
#endif
}
}
}
@ -371,7 +378,7 @@ bool VerificImporter::import_netlist_instance_gates(Instance *inst, RTLIL::IdStr
return true;
}
if (inst->Type() == PRIM_TRI) {
if ((inst->Type() == PRIM_TRI) || (inst->Type() == PRIM_BUFIF1)) {
module->addMuxGate(inst_name, RTLIL::State::Sz, net_map_at(inst->GetInput()), net_map_at(inst->GetControl()), net_map_at(inst->GetOutput()));
return true;
}
@ -410,6 +417,42 @@ bool VerificImporter::import_netlist_instance_gates(Instance *inst, RTLIL::IdStr
return true;
}
if (inst->Type() == PRIM_DLATCHRS)
{
if (inst->GetSet()->IsGnd() && inst->GetReset()->IsGnd())
module->addDlatch(inst_name, net_map_at(inst->GetControl()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
else
module->addDlatchsr(inst_name, net_map_at(inst->GetControl()), net_map_at(inst->GetSet()), net_map_at(inst->GetReset()),
net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
return true;
}
if (inst->Type() == PRIM_DFF)
{
VerificClocking clocking(this, inst->GetClock());
log_assert(clocking.disable_sig == State::S0);
log_assert(clocking.body_net == nullptr);
if (inst->GetAsyncCond()->IsGnd())
clocking.addDff(inst_name, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
else
clocking.addAldff(inst_name, net_map_at(inst->GetAsyncCond()), net_map_at(inst->GetAsyncVal()),
net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
return true;
}
if (inst->Type() == PRIM_DLATCH)
{
if (inst->GetAsyncCond()->IsGnd()) {
module->addDlatch(inst_name, net_map_at(inst->GetControl()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
} else {
RTLIL::SigSpec sig_set = module->And(NEW_ID, net_map_at(inst->GetAsyncCond()), net_map_at(inst->GetAsyncVal()));
RTLIL::SigSpec sig_clr = module->And(NEW_ID, net_map_at(inst->GetAsyncCond()), module->Not(NEW_ID, net_map_at(inst->GetAsyncVal())));
module->addDlatchsr(inst_name, net_map_at(inst->GetControl()), sig_set, sig_clr, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
}
return true;
}
return false;
}
@ -471,7 +514,7 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
return true;
}
if (inst->Type() == PRIM_TRI) {
if ((inst->Type() == PRIM_TRI) || (inst->Type() == PRIM_BUFIF1)) {
cell = module->addMux(inst_name, RTLIL::State::Sz, net_map_at(inst->GetInput()), net_map_at(inst->GetControl()), net_map_at(inst->GetOutput()));
import_attributes(cell->attributes, inst);
return true;
@ -520,6 +563,34 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
return true;
}
if (inst->Type() == PRIM_DFF)
{
VerificClocking clocking(this, inst->GetClock());
log_assert(clocking.disable_sig == State::S0);
log_assert(clocking.body_net == nullptr);
if (inst->GetAsyncCond()->IsGnd())
cell = clocking.addDff(inst_name, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
else
cell = clocking.addAldff(inst_name, net_map_at(inst->GetAsyncCond()), net_map_at(inst->GetAsyncVal()),
net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
import_attributes(cell->attributes, inst);
return true;
}
if (inst->Type() == PRIM_DLATCH)
{
if (inst->GetAsyncCond()->IsGnd()) {
cell = module->addDlatch(inst_name, net_map_at(inst->GetControl()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
} else {
RTLIL::SigSpec sig_set = module->And(NEW_ID, net_map_at(inst->GetAsyncCond()), net_map_at(inst->GetAsyncVal()));
RTLIL::SigSpec sig_clr = module->And(NEW_ID, net_map_at(inst->GetAsyncCond()), module->Not(NEW_ID, net_map_at(inst->GetAsyncVal())));
cell = module->addDlatchsr(inst_name, net_map_at(inst->GetControl()), sig_set, sig_clr, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
}
import_attributes(cell->attributes, inst);
return true;
}
#define IN operatorInput(inst)
#define IN1 operatorInput1(inst)
#define IN2 operatorInput2(inst)
@ -727,28 +798,14 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
}
if (inst->Type() == OPER_NTO1MUX) {
cell = module->addShr(inst_name, IN2, IN1, net_map_at(inst->GetOutput()));
cell = module->addBmux(inst_name, IN2, IN1, net_map_at(inst->GetOutput()));
import_attributes(cell->attributes, inst);
return true;
}
if (inst->Type() == OPER_WIDE_NTO1MUX)
{
SigSpec data = IN2, out = OUT;
int wordsize_bits = ceil_log2(GetSize(out));
int wordsize = 1 << wordsize_bits;
SigSpec sel = {IN1, SigSpec(State::S0, wordsize_bits)};
SigSpec padded_data;
for (int i = 0; i < GetSize(data); i += GetSize(out)) {
SigSpec d = data.extract(i, GetSize(out));
d.extend_u0(wordsize);
padded_data.append(d);
}
cell = module->addShr(inst_name, padded_data, sel, out);
cell = module->addBmux(inst_name, IN2, IN1, OUT);
import_attributes(cell->attributes, inst);
return true;
}
@ -792,6 +849,74 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
return true;
}
if (inst->Type() == OPER_WIDE_DLATCHRS)
{
RTLIL::SigSpec sig_set = operatorInport(inst, "set");
RTLIL::SigSpec sig_reset = operatorInport(inst, "reset");
if (sig_set.is_fully_const() && !sig_set.as_bool() && sig_reset.is_fully_const() && !sig_reset.as_bool())
cell = module->addDlatch(inst_name, net_map_at(inst->GetControl()), IN, OUT);
else
cell = module->addDlatchsr(inst_name, net_map_at(inst->GetControl()), sig_set, sig_reset, IN, OUT);
import_attributes(cell->attributes, inst);
return true;
}
if (inst->Type() == OPER_WIDE_DFF)
{
VerificClocking clocking(this, inst->GetClock());
log_assert(clocking.disable_sig == State::S0);
log_assert(clocking.body_net == nullptr);
RTLIL::SigSpec sig_d = IN;
RTLIL::SigSpec sig_q = OUT;
RTLIL::SigSpec sig_adata = IN1;
RTLIL::SigSpec sig_acond = IN2;
if (sig_acond.is_fully_const() && !sig_acond.as_bool()) {
cell = clocking.addDff(inst_name, sig_d, sig_q);
import_attributes(cell->attributes, inst);
} else {
int offset = 0, width = 0;
for (offset = 0; offset < GetSize(sig_acond); offset += width) {
for (width = 1; offset+width < GetSize(sig_acond); width++)
if (sig_acond[offset] != sig_acond[offset+width]) break;
cell = clocking.addAldff(module->uniquify(inst_name), sig_acond[offset], sig_adata.extract(offset, width),
sig_d.extract(offset, width), sig_q.extract(offset, width));
import_attributes(cell->attributes, inst);
}
}
return true;
}
if (inst->Type() == OPER_WIDE_DLATCH)
{
RTLIL::SigSpec sig_d = IN;
RTLIL::SigSpec sig_q = OUT;
RTLIL::SigSpec sig_adata = IN1;
RTLIL::SigSpec sig_acond = IN2;
if (sig_acond.is_fully_const() && !sig_acond.as_bool()) {
cell = module->addDlatch(inst_name, net_map_at(inst->GetControl()), sig_d, sig_q);
import_attributes(cell->attributes, inst);
} else {
int offset = 0, width = 0;
for (offset = 0; offset < GetSize(sig_acond); offset += width) {
for (width = 1; offset+width < GetSize(sig_acond); width++)
if (sig_acond[offset] != sig_acond[offset+width]) break;
RTLIL::SigSpec sig_set = module->Mux(NEW_ID, RTLIL::SigSpec(0, width), sig_adata.extract(offset, width), sig_acond[offset]);
RTLIL::SigSpec sig_clr = module->Mux(NEW_ID, RTLIL::SigSpec(0, width), module->Not(NEW_ID, sig_adata.extract(offset, width)), sig_acond[offset]);
cell = module->addDlatchsr(module->uniquify(inst_name), net_map_at(inst->GetControl()), sig_set, sig_clr,
sig_d.extract(offset, width), sig_q.extract(offset, width));
import_attributes(cell->attributes, inst);
}
}
return true;
}
#undef IN
#undef IN1
#undef IN2
@ -917,6 +1042,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
} else {
log("Importing module %s.\n", RTLIL::id2cstr(module->name));
}
import_attributes(module->attributes, nl, nl);
SetIter si;
MapIter mi, mi2;
@ -965,18 +1091,28 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
wire->start_offset = min(portbus->LeftIndex(), portbus->RightIndex());
import_attributes(wire->attributes, portbus, nl);
if (portbus->GetDir() == DIR_INOUT || portbus->GetDir() == DIR_IN)
bool portbus_input = portbus->GetDir() == DIR_INOUT || portbus->GetDir() == DIR_IN;
if (portbus_input)
wire->port_input = true;
if (portbus->GetDir() == DIR_INOUT || portbus->GetDir() == DIR_OUT)
wire->port_output = true;
for (int i = portbus->LeftIndex();; i += portbus->IsUp() ? +1 : -1) {
if (portbus->ElementAtIndex(i) && portbus->ElementAtIndex(i)->GetNet()) {
bool bit_input = portbus_input;
if (portbus->GetDir() == DIR_NONE) {
Port *p = portbus->ElementAtIndex(i);
bit_input = p->GetDir() == DIR_INOUT || p->GetDir() == DIR_IN;
if (bit_input)
wire->port_input = true;
if (p->GetDir() == DIR_INOUT || p->GetDir() == DIR_OUT)
wire->port_output = true;
}
net = portbus->ElementAtIndex(i)->GetNet();
RTLIL::SigBit bit(wire, i - wire->start_offset);
if (net_map.count(net) == 0)
net_map[net] = bit;
else if (wire->port_input)
else if (bit_input)
module->connect(net_map_at(net), bit);
else
module->connect(bit, net_map_at(net));
@ -1003,7 +1139,6 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
module->memories[memory->name] = memory;
int number_of_bits = net->Size();
number_of_bits = 1 << ceil_log2(number_of_bits);
int bits_in_word = number_of_bits;
FOREACH_PORTREF_OF_NET(net, si, pr) {
if (pr->GetInst()->Type() == OPER_READ_PORT) {
@ -1474,9 +1609,10 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
continue;
}
#ifdef YOSYSHQ_VERIFIC_INITSTATE
if (inst->Type() == PRIM_YOSYSHQ_INITSTATE)
{
if (verific_verbose)
log(" adding YosysHQ init state\n");
SigBit initstate = module->Initstate(new_verific_id(inst));
SigBit sig_o = net_map_at(inst->GetOutput());
module->connect(sig_o, initstate);
@ -1484,7 +1620,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
if (!mode_keep)
continue;
}
#endif
if (!mode_keep && verific_sva_prims.count(inst->Type())) {
if (verific_verbose)
log(" skipping SVA cell in non k-mode\n");
@ -1756,30 +1892,62 @@ Cell *VerificClocking::addDff(IdString name, SigSpec sig_d, SigSpec sig_q, Const
{
log_assert(GetSize(sig_d) == GetSize(sig_q));
if (GetSize(init_value) != 0) {
log_assert(GetSize(sig_q) == GetSize(init_value));
if (sig_q.is_wire()) {
sig_q.as_wire()->attributes[ID::init] = init_value;
auto set_init_attribute = [&](SigSpec &s) {
if (GetSize(init_value) == 0)
return;
log_assert(GetSize(s) == GetSize(init_value));
if (s.is_wire()) {
s.as_wire()->attributes[ID::init] = init_value;
} else {
Wire *w = module->addWire(NEW_ID, GetSize(sig_q));
Wire *w = module->addWire(NEW_ID, GetSize(s));
w->attributes[ID::init] = init_value;
module->connect(sig_q, w);
sig_q = w;
module->connect(s, w);
s = w;
}
}
};
if (enable_sig != State::S1)
sig_d = module->Mux(NEW_ID, sig_q, sig_d, enable_sig);
if (disable_sig != State::S0) {
log_assert(gclk == false);
log_assert(GetSize(sig_q) == GetSize(init_value));
if (gclk) {
Wire *pre_d = module->addWire(NEW_ID, GetSize(sig_d));
Wire *post_q_w = module->addWire(NEW_ID, GetSize(sig_q));
Const initval(State::Sx, GetSize(sig_q));
int offset = 0;
for (auto c : sig_q.chunks()) {
if (c.wire && c.wire->attributes.count(ID::init)) {
Const val = c.wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(c); i++)
initval[offset+i] = val[c.offset+i];
}
offset += GetSize(c);
}
if (!initval.is_fully_undef())
post_q_w->attributes[ID::init] = initval;
module->addMux(NEW_ID, sig_d, init_value, disable_sig, pre_d);
module->addMux(NEW_ID, post_q_w, init_value, disable_sig, sig_q);
SigSpec post_q(post_q_w);
set_init_attribute(post_q);
return module->addFf(name, pre_d, post_q);
}
set_init_attribute(sig_q);
return module->addAdff(name, clock_sig, disable_sig, sig_d, sig_q, init_value, posedge);
}
if (gclk)
if (gclk) {
set_init_attribute(sig_q);
return module->addFf(name, sig_d, sig_q);
}
set_init_attribute(sig_q);
return module->addDff(name, clock_sig, sig_d, sig_q, posedge);
}
@ -1788,6 +1956,7 @@ Cell *VerificClocking::addAdff(IdString name, RTLIL::SigSpec sig_arst, SigSpec s
log_assert(gclk == false);
log_assert(disable_sig == State::S0);
// FIXME: Adffe
if (enable_sig != State::S1)
sig_d = module->Mux(NEW_ID, sig_q, sig_d, enable_sig);
@ -1799,12 +1968,48 @@ Cell *VerificClocking::addDffsr(IdString name, RTLIL::SigSpec sig_set, RTLIL::Si
log_assert(gclk == false);
log_assert(disable_sig == State::S0);
// FIXME: Dffsre
if (enable_sig != State::S1)
sig_d = module->Mux(NEW_ID, sig_q, sig_d, enable_sig);
return module->addDffsr(name, clock_sig, sig_set, sig_clr, sig_d, sig_q, posedge);
}
Cell *VerificClocking::addAldff(IdString name, RTLIL::SigSpec sig_aload, RTLIL::SigSpec sig_adata, SigSpec sig_d, SigSpec sig_q)
{
log_assert(disable_sig == State::S0);
// FIXME: Aldffe
if (enable_sig != State::S1)
sig_d = module->Mux(NEW_ID, sig_q, sig_d, enable_sig);
if (gclk) {
Wire *pre_d = module->addWire(NEW_ID, GetSize(sig_d));
Wire *post_q = module->addWire(NEW_ID, GetSize(sig_q));
Const initval(State::Sx, GetSize(sig_q));
int offset = 0;
for (auto c : sig_q.chunks()) {
if (c.wire && c.wire->attributes.count(ID::init)) {
Const val = c.wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(c); i++)
initval[offset+i] = val[c.offset+i];
}
offset += GetSize(c);
}
if (!initval.is_fully_undef())
post_q->attributes[ID::init] = initval;
module->addMux(NEW_ID, sig_d, sig_adata, sig_aload, pre_d);
module->addMux(NEW_ID, post_q, sig_adata, sig_aload, sig_q);
return module->addFf(name, pre_d, post_q);
}
return module->addAldff(name, clock_sig, sig_aload, sig_d, sig_q, sig_adata, posedge);
}
// ==================================================================
struct VerificExtNets
@ -1951,21 +2156,23 @@ void verific_import(Design *design, const std::map<std::string,std::string> &par
std::set<Netlist*> nl_todo, nl_done;
VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary("work", 1);
VeriLibrary *veri_lib = veri_file::GetLibrary("work", 1);
Array *netlists = NULL;
Array veri_libs, vhdl_libs;
#ifdef VERIFIC_VHDL_SUPPORT
VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary("work", 1);
if (vhdl_lib) vhdl_libs.InsertLast(vhdl_lib);
#endif
if (veri_lib) veri_libs.InsertLast(veri_lib);
Map verific_params(STRING_HASH);
for (const auto &i : parameters)
verific_params.Insert(i.first.c_str(), i.second.c_str());
#ifdef YOSYSHQ_VERIFIC_INITSTATE
InitialAssertionRewriter rw;
rw.RegisterCallBack();
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
InitialAssertions::Rewrite("work", &verific_params);
#endif
if (top.empty()) {
netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, &verific_params);
}
@ -1986,12 +2193,13 @@ void verific_import(Design *design, const std::map<std::string,std::string> &par
}
}
#ifdef VERIFIC_VHDL_SUPPORT
if (vhdl_lib) {
VhdlDesignUnit *vhdl_unit = vhdl_lib->GetPrimUnit(top.c_str());
if (vhdl_unit)
vhdl_units.InsertLast(vhdl_unit);
}
#endif
netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &verific_params);
}
@ -2028,7 +2236,9 @@ void verific_import(Design *design, const std::map<std::string,std::string> &par
}
veri_file::Reset();
#ifdef VERIFIC_VHDL_SUPPORT
vhdl_file::Reset();
#endif
Libset::Reset();
verific_incdirs.clear();
verific_libdirs.clear();
@ -2071,7 +2281,7 @@ struct VerificPass : public Pass {
log("\n");
log("Additional -D<macro>[=<value>] options may be added after the option indicating\n");
log("the language version (and before file names) to set additional verilog defines.\n");
log("The macros SYNTHESIS and VERIFIC are defined implicitly.\n");
log("The macros YOSYS, SYNTHESIS, and VERIFIC are defined implicitly.\n");
log("\n");
log("\n");
log(" verific -formal <verilog-file>..\n");
@ -2079,11 +2289,41 @@ struct VerificPass : public Pass {
log("Like -sv, but define FORMAL instead of SYNTHESIS.\n");
log("\n");
log("\n");
#ifdef VERIFIC_VHDL_SUPPORT
log(" verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..\n");
log("\n");
log("Load the specified VHDL files into Verific.\n");
log("\n");
log("\n");
#endif
log(" verific {-f|-F} [-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv|-formal] <command-file>\n");
log("\n");
log("Load and execute the specified command file.\n");
log("Override verilog parsing mode can be set.\n");
log("The macros YOSYS, SYNTHESIS/FORMAL, and VERIFIC are defined implicitly.\n");
log("\n");
log("Command file parser supports following commands:\n");
log(" +define - defines macro\n");
log(" -u - upper case all identifier (makes Verilog parser case insensitive)\n");
log(" -v - register library name (file)\n");
log(" -y - register library name (directory)\n");
log(" +incdir - specify include dir\n");
log(" +libext - specify library extension\n");
log(" +liborder - add library in ordered list\n");
log(" +librescan - unresolved modules will be always searched starting with the first\n");
log(" library specified by -y/-v options.\n");
log(" -f/-file - nested -f option\n");
log(" -F - nested -F option\n");
log("\n");
log(" parse mode:\n");
log(" -ams\n");
log(" +systemverilogext\n");
log(" +v2k\n");
log(" +verilog1995ext\n");
log(" +verilog2001ext\n");
log(" -sverilog\n");
log("\n");
log("\n");
log(" verific [-work <libname>] {-sv|-vhdl|...} <hdl-file>\n");
log("\n");
log("Load the specified Verilog/SystemVerilog/VHDL file into the specified library.\n");
@ -2255,6 +2495,13 @@ struct VerificPass : public Pass {
log(" WARNING: Templates only available in commercial build.\n");
log("\n");
#endif
log("\n");
log("\n");
log(" verific -cfg [<name> [<value>]]\n");
log("\n");
log("Get/set Verific runtime flags.\n");
log("\n");
log("\n");
log("Use YosysHQ Tabby CAD Suite if you need Yosys+Verific.\n");
log("https://www.yosyshq.com/\n");
log("\n");
@ -2283,24 +2530,31 @@ struct VerificPass : public Pass {
Message::SetConsoleOutput(0);
Message::RegisterCallBackMsg(msg_func);
RuntimeFlags::SetVar("db_preserve_user_instances", 1);
RuntimeFlags::SetVar("db_preserve_user_nets", 1);
RuntimeFlags::SetVar("db_preserve_x", 1);
RuntimeFlags::SetVar("db_allow_external_nets", 1);
RuntimeFlags::SetVar("db_infer_wide_operators", 1);
RuntimeFlags::SetVar("db_infer_set_reset_registers", 0);
RuntimeFlags::SetVar("veri_extract_dualport_rams", 0);
RuntimeFlags::SetVar("veri_extract_multiport_rams", 1);
#ifdef VERIFIC_VHDL_SUPPORT
RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0);
RuntimeFlags::SetVar("vhdl_extract_multiport_rams", 1);
RuntimeFlags::SetVar("vhdl_support_variable_slice", 1);
RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0);
RuntimeFlags::SetVar("veri_preserve_assignments", 1);
RuntimeFlags::SetVar("vhdl_preserve_assignments", 1);
RuntimeFlags::SetVar("veri_preserve_comments",1);
//RuntimeFlags::SetVar("vhdl_preserve_comments",1);
//RuntimeFlags::SetVar("vhdl_preserve_comments", 1);
RuntimeFlags::SetVar("vhdl_preserve_drivers", 1);
#endif
RuntimeFlags::SetVar("veri_preserve_assignments", 1);
RuntimeFlags::SetVar("veri_preserve_comments", 1);
RuntimeFlags::SetVar("veri_preserve_drivers", 1);
// Workaround for VIPER #13851
RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1);
@ -2311,6 +2565,8 @@ struct VerificPass : public Pass {
// https://github.com/YosysHQ/yosys/issues/1055
RuntimeFlags::SetVar("veri_elaborate_top_level_modules_having_interface_ports", 1) ;
RuntimeFlags::SetVar("verific_produce_verbose_syntax_error_message", 1);
#ifndef DB_PRESERVE_INITIAL_VALUE
# warning Verific was built without DB_PRESERVE_INITIAL_VALUE.
#endif
@ -2407,6 +2663,65 @@ struct VerificPass : public Pass {
break;
}
if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F"))
{
unsigned verilog_mode = veri_file::VERILOG_95; // default recommended by Verific
bool is_formal = false;
const char* filename = nullptr;
Verific::veri_file::f_file_flags flags = (args[argidx] == "-f") ? veri_file::F_FILE_NONE : veri_file::F_FILE_CAPITAL;
for (argidx++; argidx < GetSize(args); argidx++) {
if (args[argidx] == "-vlog95") {
verilog_mode = veri_file::VERILOG_95;
continue;
} else if (args[argidx] == "-vlog2k") {
verilog_mode = veri_file::VERILOG_2K;
continue;
} else if (args[argidx] == "-sv2005") {
verilog_mode = veri_file::SYSTEM_VERILOG_2005;
continue;
} else if (args[argidx] == "-sv2009") {
verilog_mode = veri_file::SYSTEM_VERILOG_2009;
continue;
} else if (args[argidx] == "-sv2012" || args[argidx] == "-sv" || args[argidx] == "-formal") {
verilog_mode = veri_file::SYSTEM_VERILOG;
if (args[argidx] == "-formal") is_formal = true;
continue;
} else if (args[argidx].compare(0, 1, "-") == 0) {
cmd_error(args, argidx, "unknown option");
goto check_error;
}
if (!filename) {
filename = args[argidx].c_str();
continue;
} else {
log_cmd_error("Only one filename can be specified.\n");
}
}
if (!filename)
log_cmd_error("Filname must be specified.\n");
unsigned analysis_mode = verilog_mode; // keep default as provided by user if not defined in file
Array *file_names = veri_file::ProcessFFile(filename, flags, analysis_mode);
if (analysis_mode != verilog_mode)
log_warning("Provided verilog mode differs from one specified in file.\n");
veri_file::DefineMacro("YOSYS");
veri_file::DefineMacro("VERIFIC");
veri_file::DefineMacro(is_formal ? "FORMAL" : "SYNTHESIS");
if (!veri_file::AnalyzeMultipleFiles(file_names, verilog_mode, work.c_str(), veri_file::MFCU)) {
verific_error_msg.clear();
log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n");
}
delete file_names;
verific_import_pending = true;
goto check_error;
}
if (GetSize(args) > argidx && (args[argidx] == "-vlog95" || args[argidx] == "-vlog2k" || args[argidx] == "-sv2005" ||
args[argidx] == "-sv2009" || args[argidx] == "-sv2012" || args[argidx] == "-sv" || args[argidx] == "-formal"))
{
@ -2426,6 +2741,7 @@ struct VerificPass : public Pass {
else
log_abort();
veri_file::DefineMacro("YOSYS");
veri_file::DefineMacro("VERIFIC");
veri_file::DefineMacro(args[argidx] == "-formal" ? "FORMAL" : "SYNTHESIS");
@ -2463,6 +2779,7 @@ struct VerificPass : public Pass {
goto check_error;
}
#ifdef VERIFIC_VHDL_SUPPORT
if (GetSize(args) > argidx && args[argidx] == "-vhdl87") {
vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1987").c_str());
for (argidx++; argidx < GetSize(args); argidx++)
@ -2498,6 +2815,7 @@ struct VerificPass : public Pass {
verific_import_pending = true;
goto check_error;
}
#endif
#ifdef YOSYSHQ_VERIFIC_FORMALAPPS
if (argidx < GetSize(args) && args[argidx] == "-app")
@ -2600,10 +2918,12 @@ struct VerificPass : public Pass {
const char* module = nullptr;
bool mode_vhdl = false;
for (argidx++; argidx < GetSize(args); argidx++) {
#ifdef VERIFIC_VHDL_SUPPORT
if (args[argidx] == "-vhdl") {
mode_vhdl = true;
continue;
}
#endif
if (args[argidx] == "-verilog") {
mode_vhdl = false;
continue;
@ -2630,7 +2950,11 @@ struct VerificPass : public Pass {
log_cmd_error("Filname must be specified.\n");
if (mode_vhdl)
#ifdef VERIFIC_VHDL_SUPPORT
vhdl_file::PrettyPrint(filename, module, work.c_str());
#else
goto check_error;
#endif
else
veri_file::PrettyPrint(filename, module, work.c_str());
goto check_error;
@ -2651,7 +2975,7 @@ struct VerificPass : public Pass {
if (!(argidx+1 < GetSize(args)))
cmd_error(args, argidx+1, "No top module specified.\n");
generator->setLogger([](std::string msg) { log("%s",msg.c_str()); } );
std::string module = args[++argidx];
VeriLibrary* veri_lib = veri_file::GetLibrary(work.c_str(), 1);
VeriModule *veri_module = veri_lib ? veri_lib->GetModule(module.c_str(), 1) : nullptr;
@ -2805,19 +3129,20 @@ struct VerificPass : public Pass {
std::set<std::string> top_mod_names;
#ifdef YOSYSHQ_VERIFIC_INITSTATE
InitialAssertionRewriter rw;
rw.RegisterCallBack();
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
InitialAssertions::Rewrite(work, &parameters);
#endif
if (mode_all)
{
log("Running hier_tree::ElaborateAll().\n");
VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1);
VeriLibrary *veri_lib = veri_file::GetLibrary(work.c_str(), 1);
Array veri_libs, vhdl_libs;
#ifdef VERIFIC_VHDL_SUPPORT
VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1);
if (vhdl_lib) vhdl_libs.InsertLast(vhdl_lib);
#endif
if (veri_lib) veri_libs.InsertLast(veri_lib);
Array *netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, &parameters);
@ -2834,7 +3159,9 @@ struct VerificPass : public Pass {
cmd_error(args, argidx, "No top module specified.\n");
VeriLibrary* veri_lib = veri_file::GetLibrary(work.c_str(), 1);
#ifdef VERIFIC_VHDL_SUPPORT
VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1);
#endif
Array veri_modules, vhdl_units;
for (; argidx < GetSize(args); argidx++)
@ -2848,14 +3175,14 @@ struct VerificPass : public Pass {
veri_modules.InsertLast(veri_module);
continue;
}
#ifdef VERIFIC_VHDL_SUPPORT
VhdlDesignUnit *vhdl_unit = vhdl_lib ? vhdl_lib->GetPrimUnit(name) : nullptr;
if (vhdl_unit) {
log("Adding VHDL unit '%s' to elaboration queue.\n", name);
vhdl_units.InsertLast(vhdl_unit);
continue;
}
#endif
log_error("Can't find module/unit '%s'.\n", name);
}
@ -2915,7 +3242,9 @@ struct VerificPass : public Pass {
}
veri_file::Reset();
#ifdef VERIFIC_VHDL_SUPPORT
vhdl_file::Reset();
#endif
Libset::Reset();
verific_incdirs.clear();
verific_libdirs.clear();
@ -2923,6 +3252,65 @@ struct VerificPass : public Pass {
goto check_error;
}
if (argidx < GetSize(args) && args[argidx] == "-cfg")
{
if (argidx+1 == GetSize(args)) {
MapIter mi;
const char *k, *s;
unsigned long v;
pool<std::string> lines;
FOREACH_MAP_ITEM(RuntimeFlags::GetVarMap(), mi, &k, &v) {
lines.insert(stringf("%s %lu", k, v));
}
FOREACH_MAP_ITEM(RuntimeFlags::GetStringVarMap(), mi, &k, &s) {
if (s == nullptr)
lines.insert(stringf("%s NULL", k));
else
lines.insert(stringf("%s \"%s\"", k, s));
}
lines.sort();
for (auto &line : lines)
log("verific -cfg %s\n", line.c_str());
goto check_error;
}
if (argidx+2 == GetSize(args)) {
const char *k = args[argidx+1].c_str();
if (RuntimeFlags::HasUnsignedVar(k)) {
log("verific -cfg %s %lu\n", k, RuntimeFlags::GetVar(k));
goto check_error;
}
if (RuntimeFlags::HasStringVar(k)) {
const char *s = RuntimeFlags::GetStringVar(k);
if (s == nullptr)
log("verific -cfg %s NULL\n", k);
else
log("verific -cfg %s \"%s\"\n", k, s);
goto check_error;
}
log_cmd_error("Can't find Verific Runtime flag '%s'.\n", k);
}
if (argidx+3 == GetSize(args)) {
const auto &k = args[argidx+1], &v = args[argidx+2];
if (v == "NULL") {
RuntimeFlags::SetStringVar(k.c_str(), nullptr);
goto check_error;
}
if (v[0] == '"') {
std::string s = v.substr(1, GetSize(v)-2);
RuntimeFlags::SetStringVar(k.c_str(), v.c_str());
goto check_error;
}
char *endptr;
unsigned long n = strtol(v.c_str(), &endptr, 0);
if (*endptr == 0) {
RuntimeFlags::SetVar(k.c_str(), n);
goto check_error;
}
}
}
cmd_error(args, argidx, "Missing or unsupported mode parameter.\n");
check_error:
@ -2958,11 +3346,19 @@ struct ReadPass : public Pass {
log("the language version (and before file names) to set additional verilog defines.\n");
log("\n");
log("\n");
#ifdef VERIFIC_VHDL_SUPPORT
log(" read {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..\n");
log("\n");
log("Load the specified VHDL files. (Requires Verific.)\n");
log("\n");
log("\n");
#endif
log(" read {-f|-F} <command-file>\n");
log("\n");
log("Load and execute the specified command file. (Requires Verific.)\n");
log("Check verific command for more information about supported commands in file.\n");
log("\n");
log("\n");
log(" read -define <macro>[=<value>]..\n");
log("\n");
log("Set global Verilog/SystemVerilog defines.\n");
@ -3039,6 +3435,7 @@ struct ReadPass : public Pass {
return;
}
#ifdef VERIFIC_VHDL_SUPPORT
if (args[1] == "-vhdl87" || args[1] == "-vhdl93" || args[1] == "-vhdl2k" || args[1] == "-vhdl2008" || args[1] == "-vhdl") {
if (use_verific) {
args[0] = "verific";
@ -3048,6 +3445,16 @@ struct ReadPass : public Pass {
}
return;
}
#endif
if (args[1] == "-f" || args[1] == "-F") {
if (use_verific) {
args[0] = "verific";
Pass::call(design, args);
} else {
cmd_error(args, 1, "This version of Yosys is built without Verific support.\n");
}
return;
}
if (args[1] == "-define") {
if (use_verific) {

3
frontends/verific/verific.h
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -50,6 +50,7 @@ struct VerificClocking {
RTLIL::Cell *addDff(IdString name, SigSpec sig_d, SigSpec sig_q, Const init_value = Const());
RTLIL::Cell *addAdff(IdString name, RTLIL::SigSpec sig_arst, SigSpec sig_d, SigSpec sig_q, Const arst_value);
RTLIL::Cell *addDffsr(IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, SigSpec sig_d, SigSpec sig_q);
RTLIL::Cell *addAldff(IdString name, RTLIL::SigSpec sig_aload, RTLIL::SigSpec sig_adata, SigSpec sig_d, SigSpec sig_q);
bool property_matches_sequence(const VerificClocking &seq) const {
if (clock_net != seq.clock_net)

2
frontends/verific/verificsva.cc
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

2
frontends/verilog/const2ast.cc
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

66
frontends/verilog/preproc.cc
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -36,6 +36,7 @@
#include "verilog_frontend.h"
#include "kernel/log.h"
#include <assert.h>
#include <stack>
#include <stdarg.h>
#include <stdio.h>
#include <string.h>
@ -141,6 +142,16 @@ static std::string next_token(bool pass_newline = false)
return_char(ch);
}
}
else if (ch == '\\')
{
while ((ch = next_char()) != 0) {
if (ch < 33 || ch > 126) {
return_char(ch);
break;
}
token += ch;
}
}
else if (ch == '/')
{
if ((ch = next_char()) != 0) {
@ -334,6 +345,11 @@ define_map_t::add(const std::string &name, const std::string &txt, const arg_map
defines[name] = std::unique_ptr<define_body_t>(new define_body_t(txt, args));
}
void define_map_t::add(const std::string &name, const define_body_t &body)
{
defines[name] = std::unique_ptr<define_body_t>(new define_body_t(body));
}
void define_map_t::merge(const define_map_t &map)
{
for (const auto &pr : map.defines) {
@ -440,7 +456,17 @@ static bool read_argument(std::string &dest)
}
}
static bool try_expand_macro(define_map_t &defines, std::string &tok)
using macro_arg_stack_t = std::stack<std::pair<std::string, define_body_t>>;
static void restore_macro_arg(define_map_t &defines, macro_arg_stack_t &macro_arg_stack)
{
log_assert(!macro_arg_stack.empty());
auto &overwritten_arg = macro_arg_stack.top();
defines.add(overwritten_arg.first, overwritten_arg.second);
macro_arg_stack.pop();
}
static bool try_expand_macro(define_map_t &defines, macro_arg_stack_t &macro_arg_stack, std::string &tok)
{
if (tok == "`\"") {
std::string literal("\"");
@ -450,7 +476,7 @@ static bool try_expand_macro(define_map_t &defines, std::string &tok)
if (ntok == "`\"") {
insert_input(literal+"\"");
return true;
} else if (!try_expand_macro(defines, ntok)) {
} else if (!try_expand_macro(defines, macro_arg_stack, ntok)) {
literal += ntok;
}
}
@ -495,6 +521,10 @@ static bool try_expand_macro(define_map_t &defines, std::string &tok)
args.push_back(arg);
}
for (const auto &pr : body->args.get_vals(name, args)) {
if (const define_body_t *existing = defines.find(pr.first)) {
macro_arg_stack.push({pr.first, *existing});
insert_input("`__restore_macro_arg ");
}
defines.add(pr.first, pr.second);
}
} else {
@ -725,9 +755,18 @@ frontend_verilog_preproc(std::istream &f,
defines.merge(pre_defines);
defines.merge(global_defines_cache);
macro_arg_stack_t macro_arg_stack;
std::vector<std::string> filename_stack;
// We are inside pass_level levels of satisfied ifdefs, and then within
// fail_level levels of unsatisfied ifdefs. The unsatisfied ones are
// always within satisfied ones — even if some condition within is true,
// the parent condition failing renders it moot.
int ifdef_fail_level = 0;
int ifdef_pass_level = 0;
// For the outermost unsatisfied ifdef, true iff that ifdef already
// had a satisfied branch, and further elsif/else branches should be
// considered unsatisfied even if the condition is true.
// Meaningless if ifdef_fail_level == 0.
bool ifdef_already_satisfied = false;
output_code.clear();
@ -745,7 +784,7 @@ frontend_verilog_preproc(std::istream &f,
if (ifdef_fail_level > 0)
ifdef_fail_level--;
else if (ifdef_pass_level > 0)
ifdef_already_satisfied = --ifdef_pass_level;
ifdef_pass_level--;
else
log_error("Found %s outside of macro conditional branch!\n", tok.c_str());
continue;
@ -755,8 +794,9 @@ frontend_verilog_preproc(std::istream &f,
if (ifdef_fail_level == 0) {
if (ifdef_pass_level == 0)
log_error("Found %s outside of macro conditional branch!\n", tok.c_str());
log_assert(ifdef_already_satisfied);
ifdef_pass_level--;
ifdef_fail_level = 1;
ifdef_already_satisfied = true;
} else if (ifdef_fail_level == 1 && !ifdef_already_satisfied) {
ifdef_fail_level = 0;
ifdef_pass_level++;
@ -771,8 +811,9 @@ frontend_verilog_preproc(std::istream &f,
if (ifdef_fail_level == 0) {
if (ifdef_pass_level == 0)
log_error("Found %s outside of macro conditional branch!\n", tok.c_str());
log_assert(ifdef_already_satisfied);
ifdef_pass_level--;
ifdef_fail_level = 1;
ifdef_already_satisfied = true;
} else if (ifdef_fail_level == 1 && !ifdef_already_satisfied && defines.find(name)) {
ifdef_fail_level = 0;
ifdef_pass_level++;
@ -818,7 +859,7 @@ frontend_verilog_preproc(std::istream &f,
if (tok == "`include") {
skip_spaces();
std::string fn = next_token(true);
while (try_expand_macro(defines, fn)) {
while (try_expand_macro(defines, macro_arg_stack, fn)) {
fn = next_token();
}
while (1) {
@ -925,12 +966,21 @@ frontend_verilog_preproc(std::istream &f,
continue;
}
if (try_expand_macro(defines, tok))
if (tok == "`__restore_macro_arg") {
restore_macro_arg(defines, macro_arg_stack);
continue;
}
if (try_expand_macro(defines, macro_arg_stack, tok))
continue;
output_code.push_back(tok);
}
if (ifdef_fail_level > 0 || ifdef_pass_level > 0) {
log_error("Unterminated preprocessor conditional!\n");
}
std::string output;
for (auto &str : output_code)
output += str;

3
frontends/verilog/preproc.h
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -42,6 +42,7 @@ struct define_map_t
// Add a definition, overwriting any existing definition for name.
void add(const std::string &name, const std::string &txt, const arg_map_t *args = nullptr);
void add(const std::string &name, const define_body_t &body);
// Merge in another map of definitions (which take precedence
// over anything currently defined).

21
frontends/verilog/verilog_frontend.cc
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -61,8 +61,6 @@ static void add_package_types(dict<std::string, AST::AstNode *> &user_types, std
}
}
}
user_type_stack.clear();
user_type_stack.push_back(new UserTypeMap());
}
struct VerilogFrontend : public Frontend {
@ -484,6 +482,19 @@ struct VerilogFrontend : public Frontend {
// make package typedefs available to parser
add_package_types(pkg_user_types, design->verilog_packages);
UserTypeMap global_types_map;
for (auto def : design->verilog_globals) {
if (def->type == AST::AST_TYPEDEF) {
global_types_map[def->str] = def;
}
}
log_assert(user_type_stack.empty());
// use previous global typedefs as bottom level of user type stack
user_type_stack.push_back(std::move(global_types_map));
// add a new empty type map to allow overriding existing global definitions
user_type_stack.push_back(UserTypeMap());
frontend_verilog_yyset_lineno(1);
frontend_verilog_yyrestart(NULL);
frontend_verilog_yyparse();
@ -506,6 +517,10 @@ struct VerilogFrontend : public Frontend {
if (!flag_nopp)
delete lexin;
// only the previous and new global type maps remain
log_assert(user_type_stack.size() == 2);
user_type_stack.clear();
delete current_ast;
current_ast = NULL;

4
frontends/verilog/verilog_frontend.h
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -47,7 +47,7 @@ namespace VERILOG_FRONTEND
// names of locally typedef'ed types in a stack
typedef std::map<std::string, AST::AstNode*> UserTypeMap;
extern std::vector<UserTypeMap *> user_type_stack;
extern std::vector<UserTypeMap> user_type_stack;
// names of package typedef'ed types
extern dict<std::string, AST::AstNode*> pkg_user_types;

52
frontends/verilog/verilog_lexer.l
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -37,6 +37,8 @@
#ifdef __clang__
// bison generates code using the 'register' storage class specifier
#pragma clang diagnostic ignored "-Wdeprecated-register"
// flex generates weirdly-indented code
#pragma clang diagnostic ignored "-Wmisleading-indentation"
#endif
#include "kernel/log.h"
@ -103,7 +105,7 @@ static bool isUserType(std::string &s)
{
// check current scope then outer scopes for a name
for (auto it = user_type_stack.rbegin(); it != user_type_stack.rend(); ++it) {
if ((*it)->count(s) > 0) {
if (it->count(s) > 0) {
return true;
}
}
@ -260,6 +262,7 @@ static bool isUserType(std::string &s)
"const" { if (formal_mode) return TOK_CONST; SV_KEYWORD(TOK_CONST); }
"checker" { if (formal_mode) return TOK_CHECKER; SV_KEYWORD(TOK_CHECKER); }
"endchecker" { if (formal_mode) return TOK_ENDCHECKER; SV_KEYWORD(TOK_ENDCHECKER); }
"bind" { if (formal_mode) return TOK_BIND; SV_KEYWORD(TOK_BIND); }
"final" { SV_KEYWORD(TOK_FINAL); }
"logic" { SV_KEYWORD(TOK_LOGIC); }
"var" { SV_KEYWORD(TOK_VAR); }
@ -276,8 +279,11 @@ static bool isUserType(std::string &s)
"output" { return TOK_OUTPUT; }
"inout" { return TOK_INOUT; }
"wire" { return TOK_WIRE; }
"tri" { return TOK_WIRE; }
"wor" { return TOK_WOR; }
"trior" { return TOK_WOR; }
"wand" { return TOK_WAND; }
"triand" { return TOK_WAND; }
"reg" { return TOK_REG; }
"integer" { return TOK_INTEGER; }
"signed" { return TOK_SIGNED; }
@ -431,8 +437,13 @@ supply1 { return TOK_SUPPLY1; }
"/*"[ \t]*(synopsys|synthesis)[ \t]*translate_off[ \t]*"*/" {
static bool printed_warning = false;
if (!printed_warning) {
log_warning("Found one of those horrible `(synopsys|synthesis) translate_off' comments.\n"
"Yosys does support them but it is recommended to use `ifdef constructs instead!\n");
log_warning(
"Encountered `translate_off' comment! Such legacy hot "
"comments are supported by Yosys, but are not part of "
"any formal language specification. Using a portable "
"and standards-compliant construct such as `ifdef is "
"recommended!\n"
);
printed_warning = true;
}
BEGIN(SYNOPSYS_TRANSLATE_OFF);
@ -447,8 +458,13 @@ supply1 { return TOK_SUPPLY1; }
<SYNOPSYS_FLAGS>full_case {
static bool printed_warning = false;
if (!printed_warning) {
log_warning("Found one of those horrible `(synopsys|synthesis) full_case' comments.\n"
"Yosys does support them but it is recommended to use Verilog `full_case' attributes instead!\n");
log_warning(
"Encountered `full_case' comment! Such legacy hot "
"comments are supported by Yosys, but are not part of "
"any formal language specification. Using the Verilog "
"`full_case' attribute or the SystemVerilog `unique' "
"or `unique0' keywords is recommended!\n"
);
printed_warning = true;
}
return TOK_SYNOPSYS_FULL_CASE;
@ -456,8 +472,13 @@ supply1 { return TOK_SUPPLY1; }
<SYNOPSYS_FLAGS>parallel_case {
static bool printed_warning = false;
if (!printed_warning) {
log_warning("Found one of those horrible `(synopsys|synthesis) parallel_case' comments.\n"
"Yosys does support them but it is recommended to use Verilog `parallel_case' attributes instead!\n");
log_warning(
"Encountered `parallel_case' comment! Such legacy hot "
"comments are supported by Yosys, but are not part of "
"any formal language specification. Using the Verilog "
"`parallel_case' attribute or the SystemVerilog "
"`unique' or `priority' keywords is recommended!\n"
);
printed_warning = true;
}
return TOK_SYNOPSYS_PARALLEL_CASE;
@ -529,11 +550,18 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
".*" { return TOK_WILDCARD_CONNECT; }
"|=" { SV_KEYWORD(TOK_OR_ASSIGN); }
"&=" { SV_KEYWORD(TOK_AND_ASSIGN); }
"+=" { SV_KEYWORD(TOK_PLUS_ASSIGN); }
"|=" { SV_KEYWORD(TOK_BIT_OR_ASSIGN); }
"&=" { SV_KEYWORD(TOK_BIT_AND_ASSIGN); }
"+=" { SV_KEYWORD(TOK_ADD_ASSIGN); }
"-=" { SV_KEYWORD(TOK_SUB_ASSIGN); }
"^=" { SV_KEYWORD(TOK_XOR_ASSIGN); }
"^=" { SV_KEYWORD(TOK_BIT_XOR_ASSIGN); }
"/=" { SV_KEYWORD(TOK_DIV_ASSIGN); }
"%=" { SV_KEYWORD(TOK_MOD_ASSIGN); }
"*=" { SV_KEYWORD(TOK_MUL_ASSIGN); }
"<<=" { SV_KEYWORD(TOK_SHL_ASSIGN); }
">>=" { SV_KEYWORD(TOK_SHR_ASSIGN); }
"<<<=" { SV_KEYWORD(TOK_SSHL_ASSIGN); }
">>>=" { SV_KEYWORD(TOK_SSHR_ASSIGN); }
[-+]?[=*]> {
if (!specify_mode) REJECT;

501
frontends/verilog/verilog_parser.y
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -33,6 +33,8 @@
*
*/
%require "3.0"
%{
#include <list>
#include <stack>
@ -54,7 +56,7 @@ namespace VERILOG_FRONTEND {
dict<IdString, AstNode*> *attr_list, default_attr_list;
std::stack<dict<IdString, AstNode*> *> attr_list_stack;
dict<IdString, AstNode*> *albuf;
std::vector<UserTypeMap*> user_type_stack;
std::vector<UserTypeMap> user_type_stack;
dict<std::string, AstNode*> pkg_user_types;
std::vector<AstNode*> ast_stack;
struct AstNode *astbuf1, *astbuf2, *astbuf3;
@ -127,13 +129,22 @@ struct specify_rise_fall {
specify_triple fall;
};
static void addWiretypeNode(std::string *name, AstNode *node)
{
log_assert(node);
node->is_custom_type = true;
node->children.push_back(new AstNode(AST_WIRETYPE));
node->children.back()->str = *name;
delete name;
}
static void addTypedefNode(std::string *name, AstNode *node)
{
log_assert(node);
auto *tnode = new AstNode(AST_TYPEDEF, node);
tnode->str = *name;
auto user_types = user_type_stack.back();
(*user_types)[*name] = tnode;
auto &user_types = user_type_stack.back();
user_types[*name] = tnode;
if (current_ast_mod && current_ast_mod->type == AST_PACKAGE) {
// typedef inside a package so we need the qualified name
auto qname = current_ast_mod->str + "::" + (*name).substr(1);
@ -145,8 +156,7 @@ static void addTypedefNode(std::string *name, AstNode *node)
static void enterTypeScope()
{
auto user_types = new UserTypeMap();
user_type_stack.push_back(user_types);
user_type_stack.push_back(UserTypeMap());
}
static void exitTypeScope()
@ -157,18 +167,24 @@ static void exitTypeScope()
static bool isInLocalScope(const std::string *name)
{
// tests if a name was declared in the current block scope
auto user_types = user_type_stack.back();
return (user_types->count(*name) > 0);
auto &user_types = user_type_stack.back();
return (user_types.count(*name) > 0);
}
static AstNode *getTypeDefinitionNode(std::string type_name)
{
// return the definition nodes from the typedef statement
auto user_types = user_type_stack.back();
log_assert(user_types->count(type_name) > 0);
auto typedef_node = (*user_types)[type_name];
log_assert(typedef_node->type == AST_TYPEDEF);
return typedef_node->children[0];
// check current scope then outer scopes for a name
for (auto it = user_type_stack.rbegin(); it != user_type_stack.rend(); ++it) {
if (it->count(type_name) > 0) {
// return the definition nodes from the typedef statement
auto typedef_node = (*it)[type_name];
log_assert(typedef_node->type == AST_TYPEDEF);
return typedef_node->children[0];
}
}
// The lexer recognized the name as a TOK_USER_TYPE, but now we can't find it anymore?
log_error("typedef for user type `%s' not found", type_name.c_str());
}
static AstNode *copyTypeDefinition(std::string type_name)
@ -230,6 +246,75 @@ static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode)
node->children.push_back(rangeNode);
}
static void checkLabelsMatch(const char *element, const std::string *before, const std::string *after)
{
if (!before && after)
frontend_verilog_yyerror("%s missing where end label (%s) was given.",
element, after->c_str() + 1);
if (before && after && *before != *after)
frontend_verilog_yyerror("%s (%s) and end label (%s) don't match.",
element, before->c_str() + 1, after->c_str() + 1);
}
// This transforms a loop like
// for (genvar i = 0; i < 10; i++) begin : blk
// to
// genvar _i;
// for (_i = 0; _i < 10; _i++) begin : blk
// localparam i = _i;
// where `_i` is actually some auto-generated name.
static void rewriteGenForDeclInit(AstNode *loop)
{
// check if this generate for loop contains an inline declaration
log_assert(loop->type == AST_GENFOR);
AstNode *decl = loop->children[0];
if (decl->type == AST_ASSIGN_EQ)
return;
log_assert(decl->type == AST_GENVAR);
log_assert(loop->children.size() == 5);
// identify each component of the loop
AstNode *init = loop->children[1];
AstNode *cond = loop->children[2];
AstNode *incr = loop->children[3];
AstNode *body = loop->children[4];
log_assert(init->type == AST_ASSIGN_EQ);
log_assert(incr->type == AST_ASSIGN_EQ);
log_assert(body->type == AST_GENBLOCK);
// create a unique name for the genvar
std::string old_str = decl->str;
std::string new_str = stringf("$genfordecl$%d$%s", autoidx++, old_str.c_str());
// rename and move the genvar declaration to the containing description
decl->str = new_str;
loop->children.erase(loop->children.begin());
log_assert(current_ast_mod != nullptr);
current_ast_mod->children.push_back(decl);
// create a new localparam with old name so that the items in the loop
// can simply use the old name and shadow it as necessary
AstNode *indirect = new AstNode(AST_LOCALPARAM);
indirect->str = old_str;
AstNode *ident = new AstNode(AST_IDENTIFIER);
ident->str = new_str;
indirect->children.push_back(ident);
body->children.insert(body->children.begin(), indirect);
// only perform the renaming for the initialization, guard, and
// incrementation to enable proper shadowing of the synthetic localparam
std::function<void(AstNode*)> substitute = [&](AstNode *node) {
if (node->type == AST_IDENTIFIER && node->str == old_str)
node->str = new_str;
for (AstNode *child : node->children)
substitute(child);
};
substitute(init);
substitute(cond);
substitute(incr);
}
%}
%define api.prefix {frontend_verilog_yy}
@ -254,6 +339,7 @@ static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode)
bool boolean;
char ch;
int integer;
YOSYS_NAMESPACE_PREFIX AST::AstNodeType ast_node_type;
}
%token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE
@ -266,7 +352,7 @@ static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode)
%token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
%token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR TOK_WILDCARD_CONNECT
%token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_WAND TOK_WOR TOK_REG TOK_LOGIC
%token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_PLUS_ASSIGN TOK_ALWAYS TOK_INITIAL
%token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
%token TOK_ALWAYS_FF TOK_ALWAYS_COMB TOK_ALWAYS_LATCH
%token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
%token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC
@ -280,18 +366,23 @@ static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode)
%token TOK_RAND TOK_CONST TOK_CHECKER TOK_ENDCHECKER TOK_EVENTUALLY
%token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_UNIQUE0 TOK_PRIORITY
%token TOK_STRUCT TOK_PACKED TOK_UNSIGNED TOK_INT TOK_BYTE TOK_SHORTINT TOK_LONGINT TOK_UNION
%token TOK_OR_ASSIGN TOK_XOR_ASSIGN TOK_AND_ASSIGN TOK_SUB_ASSIGN
%token TOK_BIT_OR_ASSIGN TOK_BIT_AND_ASSIGN TOK_BIT_XOR_ASSIGN TOK_ADD_ASSIGN
%token TOK_SUB_ASSIGN TOK_DIV_ASSIGN TOK_MOD_ASSIGN TOK_MUL_ASSIGN
%token TOK_SHL_ASSIGN TOK_SHR_ASSIGN TOK_SSHL_ASSIGN TOK_SSHR_ASSIGN
%token TOK_BIND
%type <ast> range range_or_multirange non_opt_range non_opt_multirange
%type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list non_io_wire_type io_wire_type
%type <string> opt_label opt_sva_label tok_prim_wrapper hierarchical_id hierarchical_type_id integral_number
%type <string> type_name
%type <ast> opt_enum_init enum_type struct_type non_wire_data_type func_return_type
%type <ast> opt_enum_init enum_type struct_type enum_struct_type func_return_type typedef_base_type
%type <boolean> opt_property always_comb_or_latch always_or_always_ff
%type <boolean> opt_signedness_default_signed opt_signedness_default_unsigned
%type <integer> integer_atom_type
%type <integer> integer_atom_type integer_vector_type
%type <al> attr case_attr
%type <ast> struct_union
%type <ast_node_type> asgn_binop
%type <ast> genvar_identifier
%type <specify_target_ptr> specify_target
%type <specify_triple_ptr> specify_triple specify_opt_triple
@ -345,6 +436,7 @@ design:
typedef_decl design |
package design |
interface design |
bind_directive design |
%empty;
attr:
@ -448,7 +540,6 @@ module:
port_counter = 0;
mod->str = *$4;
append_attr(mod, $1);
delete $4;
} module_para_opt module_args_opt ';' module_body TOK_ENDMODULE opt_label {
if (port_stubs.size() != 0)
frontend_verilog_yyerror("Missing details for module port `%s'.",
@ -456,7 +547,10 @@ module:
SET_AST_NODE_LOC(ast_stack.back(), @2, @$);
ast_stack.pop_back();
log_assert(ast_stack.size() == 1);
checkLabelsMatch("Module name", $4, $11);
current_ast_mod = NULL;
delete $4;
delete $11;
exitTypeScope();
};
@ -494,18 +588,19 @@ optional_comma:
module_arg_opt_assignment:
'=' expr {
if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
AstNode *wire = new AstNode(AST_IDENTIFIER);
wire->str = ast_stack.back()->children.back()->str;
if (ast_stack.back()->children.back()->is_input) {
AstNode *n = ast_stack.back()->children.back();
if (n->attributes.count(ID::defaultvalue))
delete n->attributes.at(ID::defaultvalue);
n->attributes[ID::defaultvalue] = $2;
} else
if (ast_stack.back()->children.back()->is_reg || ast_stack.back()->children.back()->is_logic)
ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2))));
else
ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $2));
} else {
AstNode *wire = new AstNode(AST_IDENTIFIER);
wire->str = ast_stack.back()->children.back()->str;
if (ast_stack.back()->children.back()->is_reg || ast_stack.back()->children.back()->is_logic)
ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2))));
else
ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $2));
}
} else
frontend_verilog_yyerror("SystemVerilog interface in module port list cannot have a default value.");
} |
@ -573,7 +668,10 @@ package:
append_attr(mod, $1);
} ';' package_body TOK_ENDPACKAGE opt_label {
ast_stack.pop_back();
checkLabelsMatch("Package name", $4, $9);
current_ast_mod = NULL;
delete $4;
delete $9;
exitTypeScope();
};
@ -581,7 +679,7 @@ package_body:
package_body package_body_stmt | %empty;
package_body_stmt:
typedef_decl | localparam_decl | param_decl;
typedef_decl | localparam_decl | param_decl | task_func_decl;
interface:
TOK_INTERFACE {
@ -611,7 +709,67 @@ interface_body:
interface_body_stmt:
param_decl | localparam_decl | typedef_decl | defparam_decl | wire_decl | always_stmt | assign_stmt |
modport_stmt;
modport_stmt | bind_directive;
bind_directive:
TOK_BIND {
AstNode *bnode = new AstNode(AST_BIND);
ast_stack.back()->children.push_back(bnode);
ast_stack.push_back(bnode);
}
bind_target {
// bind_target should have added at least one child
log_assert(ast_stack.back()->children.size() >= 1);
}
TOK_ID {
// The single_cell parser in cell_list_no_array uses astbuf1 as
// a sort of template for constructing cells.
astbuf1 = new AstNode(AST_CELL);
astbuf1->children.push_back(new AstNode(AST_CELLTYPE));
astbuf1->children[0]->str = *$5;
delete $5;
}
cell_parameter_list_opt cell_list_no_array ';' {
// cell_list should have added at least one more child
log_assert(ast_stack.back()->children.size() >= 2);
delete astbuf1;
ast_stack.pop_back();
};
// bind_target matches the target of the bind (everything before
// bind_instantiation in the IEEE 1800 spec).
//
// We can't use the BNF from the spec directly because it's ambiguous:
// something like "bind foo bar_i (.*)" can either be interpreted with "foo" as
// a module or interface identifier (matching bind_target_scope in the spec) or
// by considering foo as a degenerate hierarchical identifier with no '.'
// characters, followed by no bit select (which matches bind_target_instance in
// the spec).
//
// Instead, we resolve everything as an instance name and then deal with the
// ambiguity when converting to RTLIL / in the hierarchy pass.
bind_target:
bind_target_instance opt_bind_target_instance_list;
// An optional list of target instances for a bind statement, introduced by a
// colon.
opt_bind_target_instance_list:
':' bind_target_instance_list |
%empty;
bind_target_instance_list:
bind_target_instance |
bind_target_instance_list ',' bind_target_instance;
// A single target instance for a bind statement. The top of ast_stack will be
// the bind node where we should add it.
bind_target_instance:
hierarchical_id {
auto *node = new AstNode(AST_IDENTIFIER);
node->str = *$1;
delete $1;
ast_stack.back()->children.push_back(node);
};
mintypmax_expr:
expr { delete $1; } |
@ -676,21 +834,10 @@ opt_wire_type_token:
wire_type_token | %empty;
wire_type_token:
hierarchical_type_id {
astbuf3->is_custom_type = true;
astbuf3->children.push_back(new AstNode(AST_WIRETYPE));
astbuf3->children.back()->str = *$1;
// nets
net_type {
} |
TOK_WOR {
astbuf3->is_wor = true;
} |
TOK_WAND {
astbuf3->is_wand = true;
} |
// wires
TOK_WIRE {
} |
TOK_WIRE logic_type {
net_type logic_type {
} |
// regs
TOK_REG {
@ -717,6 +864,15 @@ wire_type_token:
astbuf3->range_right = 0;
};
net_type:
TOK_WOR {
astbuf3->is_wor = true;
} |
TOK_WAND {
astbuf3->is_wand = true;
} |
TOK_WIRE;
logic_type:
TOK_LOGIC {
} |
@ -724,6 +880,9 @@ logic_type:
astbuf3->range_left = $1 - 1;
astbuf3->range_right = 0;
astbuf3->is_signed = true;
} |
hierarchical_type_id {
addWiretypeNode($1, astbuf3);
};
integer_atom_type:
@ -733,6 +892,10 @@ integer_atom_type:
TOK_LONGINT { $$ = 64; } |
TOK_BYTE { $$ = 8; } ;
integer_vector_type:
TOK_LOGIC { $$ = TOK_LOGIC; } |
TOK_REG { $$ = TOK_REG; } ;
non_opt_range:
'[' expr ':' expr ']' {
$$ = new AstNode(AST_RANGE);
@ -787,7 +950,7 @@ module_body:
module_body_stmt:
task_func_decl | specify_block | param_decl | localparam_decl | typedef_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt |
enum_decl | struct_decl |
enum_decl | struct_decl | bind_directive |
always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block;
checker_decl:
@ -861,6 +1024,7 @@ task_func_decl:
outreg->children.push_back($4);
outreg->is_signed = $4->is_signed;
$4->is_signed = false;
outreg->is_custom_type = $4->type == AST_WIRETYPE;
}
current_function_or_task->children.push_back(outreg);
current_function_or_task_port_id = 1;
@ -871,6 +1035,11 @@ task_func_decl:
};
func_return_type:
hierarchical_type_id {
$$ = new AstNode(AST_WIRETYPE);
$$->str = *$1;
delete $1;
} |
opt_type_vec opt_signedness_default_unsigned {
$$ = makeRange(0, 0, $2);
} |
@ -1141,6 +1310,8 @@ specify_item:
cell->children.back()->str = "\\DST";
delete $1;
delete limit;
delete limit2;
};
specify_opt_triple:
@ -1438,6 +1609,7 @@ param_type:
astbuf1->is_custom_type = true;
astbuf1->children.push_back(new AstNode(AST_WIRETYPE));
astbuf1->children.back()->str = *$1;
delete $1;
};
param_decl:
@ -1462,7 +1634,26 @@ param_decl_list:
single_param_decl | param_decl_list ',' single_param_decl;
single_param_decl:
TOK_ID '=' expr {
single_param_decl_ident '=' expr {
AstNode *decl = ast_stack.back()->children.back();
log_assert(decl->type == AST_PARAMETER || decl->type == AST_LOCALPARAM);
delete decl->children[0];
decl->children[0] = $3;
} |
single_param_decl_ident {
AstNode *decl = ast_stack.back()->children.back();
if (decl->type != AST_PARAMETER) {
log_assert(decl->type == AST_LOCALPARAM);
frontend_verilog_yyerror("localparam initialization is missing!");
}
if (!sv_mode)
frontend_verilog_yyerror("Parameter defaults can only be omitted in SystemVerilog mode!");
delete decl->children[0];
decl->children.erase(decl->children.begin());
};
single_param_decl_ident:
TOK_ID {
AstNode *node;
if (astbuf1 == nullptr) {
if (!sv_mode)
@ -1473,10 +1664,9 @@ single_param_decl:
node = astbuf1->clone();
}
node->str = *$1;
delete node->children[0];
node->children[0] = $3;
ast_stack.back()->children.push_back(node);
delete $1;
SET_AST_NODE_LOC(node, @1, @1);
};
defparam_decl:
@ -1509,17 +1699,18 @@ enum_type: TOK_ENUM {
// create the template for the names
astbuf1 = new AstNode(AST_ENUM_ITEM);
astbuf1->children.push_back(AstNode::mkconst_int(0, true));
} enum_base_type '{' enum_name_list '}' { // create template for the enum vars
auto tnode = astbuf1->clone();
delete astbuf1;
astbuf1 = tnode;
tnode->type = AST_WIRE;
tnode->attributes[ID::enum_type] = AstNode::mkconst_str(astbuf2->str);
// drop constant but keep any range
delete tnode->children[0];
tnode->children.erase(tnode->children.begin());
$$ = astbuf1; }
;
} enum_base_type '{' enum_name_list optional_comma '}' {
// create template for the enum vars
auto tnode = astbuf1->clone();
delete astbuf1;
astbuf1 = tnode;
tnode->type = AST_WIRE;
tnode->attributes[ID::enum_type] = AstNode::mkconst_str(astbuf2->str);
// drop constant but keep any range
delete tnode->children[0];
tnode->children.erase(tnode->children.begin());
$$ = astbuf1;
};
enum_base_type: type_atom type_signing
| type_vec type_signing range { if ($3) astbuf1->children.push_back($3); }
@ -1658,10 +1849,12 @@ member_type_token:
delete astbuf1;
astbuf1 = template_node;
}
| struct_union {
| {
delete astbuf1;
} struct_union {
// stash state on ast_stack
ast_stack.push_back(astbuf2);
astbuf2 = $1;
astbuf2 = $2;
} struct_body {
astbuf1 = astbuf2;
// recover state
@ -1867,7 +2060,7 @@ type_name: TOK_ID // first time seen
;
typedef_decl:
TOK_TYPEDEF non_io_wire_type range type_name range_or_multirange ';' {
TOK_TYPEDEF typedef_base_type range type_name range_or_multirange ';' {
astbuf1 = $2;
astbuf2 = checkRange(astbuf1, $3);
if (astbuf2)
@ -1880,10 +2073,33 @@ typedef_decl:
rewriteAsMemoryNode(astbuf1, $5);
}
addTypedefNode($4, astbuf1); }
| TOK_TYPEDEF non_wire_data_type type_name ';' { addTypedefNode($3, $2); }
| TOK_TYPEDEF enum_struct_type type_name ';' { addTypedefNode($3, $2); }
;
non_wire_data_type:
typedef_base_type:
hierarchical_type_id {
$$ = new AstNode(AST_WIRE);
$$->is_logic = true;
addWiretypeNode($1, $$);
} |
integer_vector_type opt_signedness_default_unsigned {
$$ = new AstNode(AST_WIRE);
if ($1 == TOK_REG) {
$$->is_reg = true;
} else {
$$->is_logic = true;
}
$$->is_signed = $2;
} |
integer_atom_type opt_signedness_default_signed {
$$ = new AstNode(AST_WIRE);
$$->is_logic = true;
$$->is_signed = $2;
$$->range_left = $1 - 1;
$$->range_right = 0;
};
enum_struct_type:
enum_type
| struct_type
;
@ -1920,6 +2136,9 @@ cell_list:
cell_list ',' single_cell;
single_cell:
single_cell_no_array | single_cell_arraylist;
single_cell_no_array:
TOK_ID {
astbuf2 = astbuf1->clone();
if (astbuf2->type != AST_PRIMITIVE)
@ -1928,7 +2147,9 @@ single_cell:
ast_stack.back()->children.push_back(astbuf2);
} '(' cell_port_list ')' {
SET_AST_NODE_LOC(astbuf2, @1, @$);
} |
}
single_cell_arraylist:
TOK_ID non_opt_range {
astbuf2 = astbuf1->clone();
if (astbuf2->type != AST_PRIMITIVE)
@ -1939,6 +2160,10 @@ single_cell:
SET_AST_NODE_LOC(astbuf2, @1, @$);
};
cell_list_no_array:
single_cell_no_array |
cell_list_no_array ',' single_cell_no_array;
prim_list:
single_prim |
prim_list ',' single_prim;
@ -2046,6 +2271,7 @@ cell_port:
if (!sv_mode)
frontend_verilog_yyerror("Wildcard port connections are only supported in SystemVerilog mode.");
astbuf2->attributes[ID::wildcard_port_conns] = AstNode::mkconst_int(1, false);
free_attr($1);
};
always_comb_or_latch:
@ -2417,45 +2643,81 @@ simple_behavioral_stmt:
SET_AST_NODE_LOC(node, @2, @5);
append_attr(node, $1);
} |
attr lvalue TOK_XOR_ASSIGN delay expr {
AstNode *xor_node = new AstNode(AST_BIT_XOR, $2->clone(), $5);
AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, xor_node);
SET_AST_NODE_LOC(xor_node, @2, @5);
attr lvalue asgn_binop delay expr {
AstNode *expr_node = $5;
if ($3 == AST_SHIFT_LEFT || $3 == AST_SHIFT_RIGHT ||
$3 == AST_SHIFT_SLEFT || $3 == AST_SHIFT_SRIGHT) {
expr_node = new AstNode(AST_TO_UNSIGNED, expr_node);
SET_AST_NODE_LOC(expr_node, @5, @5);
}
AstNode *op_node = new AstNode($3, $2->clone(), expr_node);
AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, op_node);
SET_AST_NODE_LOC(op_node, @2, @5);
SET_AST_NODE_LOC(node, @2, @5);
ast_stack.back()->children.push_back(node);
append_attr(node, $1);
};
asgn_binop:
TOK_BIT_OR_ASSIGN { $$ = AST_BIT_OR; } |
TOK_BIT_AND_ASSIGN { $$ = AST_BIT_AND; } |
TOK_BIT_XOR_ASSIGN { $$ = AST_BIT_XOR; } |
TOK_ADD_ASSIGN { $$ = AST_ADD; } |
TOK_SUB_ASSIGN { $$ = AST_SUB; } |
TOK_DIV_ASSIGN { $$ = AST_DIV; } |
TOK_MOD_ASSIGN { $$ = AST_MOD; } |
TOK_MUL_ASSIGN { $$ = AST_MUL; } |
TOK_SHL_ASSIGN { $$ = AST_SHIFT_LEFT; } |
TOK_SHR_ASSIGN { $$ = AST_SHIFT_RIGHT; } |
TOK_SSHL_ASSIGN { $$ = AST_SHIFT_SLEFT; } |
TOK_SSHR_ASSIGN { $$ = AST_SHIFT_SRIGHT; } ;
for_initialization:
TOK_ID '=' expr {
AstNode *ident = new AstNode(AST_IDENTIFIER);
ident->str = *$1;
AstNode *node = new AstNode(AST_ASSIGN_EQ, ident, $3);
ast_stack.back()->children.push_back(node);
SET_AST_NODE_LOC(node, @1, @3);
delete $1;
} |
attr lvalue TOK_OR_ASSIGN delay expr {
AstNode *or_node = new AstNode(AST_BIT_OR, $2->clone(), $5);
SET_AST_NODE_LOC(or_node, @2, @5);
AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, or_node);
SET_AST_NODE_LOC(node, @2, @5);
ast_stack.back()->children.push_back(node);
append_attr(node, $1);
non_io_wire_type range TOK_ID {
frontend_verilog_yyerror("For loop variable declaration is missing initialization!");
} |
attr lvalue TOK_PLUS_ASSIGN delay expr {
AstNode *add_node = new AstNode(AST_ADD, $2->clone(), $5);
AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, add_node);
SET_AST_NODE_LOC(node, @2, @5);
SET_AST_NODE_LOC(add_node, @2, @5);
ast_stack.back()->children.push_back(node);
append_attr(node, $1);
} |
attr lvalue TOK_SUB_ASSIGN delay expr {
AstNode *sub_node = new AstNode(AST_SUB, $2->clone(), $5);
AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, sub_node);
SET_AST_NODE_LOC(node, @2, @5);
SET_AST_NODE_LOC(sub_node, @2, @5);
ast_stack.back()->children.push_back(node);
append_attr(node, $1);
} |
attr lvalue TOK_AND_ASSIGN delay expr {
AstNode *and_node = new AstNode(AST_BIT_AND, $2->clone(), $5);
AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, and_node);
SET_AST_NODE_LOC(node, @2, @5);
SET_AST_NODE_LOC(and_node, @2, @5);
ast_stack.back()->children.push_back(node);
append_attr(node, $1);
non_io_wire_type range TOK_ID '=' expr {
if (!sv_mode)
frontend_verilog_yyerror("For loop inline variable declaration is only supported in SystemVerilog mode!");
// loop variable declaration
AstNode *wire = $1;
AstNode *range = checkRange(wire, $2);
if (range != nullptr)
wire->children.push_back(range);
SET_AST_NODE_LOC(wire, @1, @3);
SET_AST_NODE_LOC(range, @2, @2);
AstNode *ident = new AstNode(AST_IDENTIFIER);
ident->str = *$3;
wire->str = *$3;
delete $3;
AstNode *loop = ast_stack.back();
AstNode *parent = ast_stack.at(ast_stack.size() - 2);
log_assert(parent->children.back() == loop);
// loop variable initialization
AstNode *asgn = new AstNode(AST_ASSIGN_EQ, ident, $5);
loop->children.push_back(asgn);
SET_AST_NODE_LOC(asgn, @3, @5);
SET_AST_NODE_LOC(ident, @3, @3);
// inject a wrapping block to declare the loop variable and
// contain the current loop
AstNode *wrapper = new AstNode(AST_BLOCK);
wrapper->str = "$fordecl_block$" + std::to_string(autoidx++);
wrapper->children.push_back(wire);
wrapper->children.push_back(loop);
parent->children.back() = wrapper; // replaces `loop`
};
// this production creates the obligatory if-else shift/reduce conflict
@ -2497,8 +2759,7 @@ behavioral_stmt:
node->str = *$4;
} behavioral_stmt_list TOK_END opt_label {
exitTypeScope();
if ($4 != NULL && $8 != NULL && *$4 != *$8)
frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $4->c_str()+1, $8->c_str()+1);
checkLabelsMatch("Begin label", $4, $8);
AstNode *node = ast_stack.back();
// In SystemVerilog, unnamed blocks with block item declarations
// create an implicit hierarchy scope
@ -2519,7 +2780,7 @@ behavioral_stmt:
ast_stack.back()->children.push_back(node);
ast_stack.push_back(node);
append_attr(node, $1);
} simple_behavioral_stmt ';' expr {
} for_initialization ';' expr {
ast_stack.back()->children.push_back($7);
} ';' simple_behavioral_stmt ')' {
AstNode *block = new AstNode(AST_BLOCK);
@ -2718,6 +2979,7 @@ rvalue:
hierarchical_id '[' expr ']' '.' rvalue {
$$ = new AstNode(AST_PREFIX, $3, $6);
$$->str = *$1;
SET_AST_NODE_LOC($$, @1, @6);
delete $1;
} |
hierarchical_id range {
@ -2783,16 +3045,50 @@ gen_stmt_or_module_body_stmt:
free_attr($1);
};
genvar_identifier:
TOK_ID {
$$ = new AstNode(AST_IDENTIFIER);
$$->str = *$1;
delete $1;
};
genvar_initialization:
TOK_GENVAR genvar_identifier {
frontend_verilog_yyerror("Generate for loop variable declaration is missing initialization!");
} |
TOK_GENVAR genvar_identifier '=' expr {
if (!sv_mode)
frontend_verilog_yyerror("Generate for loop inline variable declaration is only supported in SystemVerilog mode!");
AstNode *node = new AstNode(AST_GENVAR);
node->is_reg = true;
node->is_signed = true;
node->range_left = 31;
node->range_right = 0;
node->str = $2->str;
node->children.push_back(checkRange(node, nullptr));
ast_stack.back()->children.push_back(node);
SET_AST_NODE_LOC(node, @1, @4);
node = new AstNode(AST_ASSIGN_EQ, $2, $4);
ast_stack.back()->children.push_back(node);
SET_AST_NODE_LOC(node, @1, @4);
} |
genvar_identifier '=' expr {
AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, $3);
ast_stack.back()->children.push_back(node);
SET_AST_NODE_LOC(node, @1, @3);
};
// this production creates the obligatory if-else shift/reduce conflict
gen_stmt:
TOK_FOR '(' {
AstNode *node = new AstNode(AST_GENFOR);
ast_stack.back()->children.push_back(node);
ast_stack.push_back(node);
} simple_behavioral_stmt ';' expr {
} genvar_initialization ';' expr {
ast_stack.back()->children.push_back($6);
} ';' simple_behavioral_stmt ')' gen_stmt_block {
SET_AST_NODE_LOC(ast_stack.back(), @1, @11);
rewriteGenForDeclInit(ast_stack.back());
ast_stack.pop_back();
} |
TOK_IF '(' expr ')' {
@ -2834,8 +3130,7 @@ gen_block:
ast_stack.push_back(node);
} module_gen_body TOK_END opt_label {
exitTypeScope();
if ($3 != NULL && $7 != NULL && *$3 != *$7)
frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $3->c_str()+1, $7->c_str()+1);
checkLabelsMatch("Begin label", $3, $7);
delete $3;
delete $7;
SET_AST_NODE_LOC(ast_stack.back(), @1, @7);

120
guidelines/Checklists Normal file
View File

@ -0,0 +1,120 @@
Checklist for adding internal cell types
========================================
Things to do right away:
- Add to kernel/celltypes.h (incl. eval() handling for non-mem cells)
- Add to InternalCellChecker::check() in kernel/rtlil.cc
- Add to techlibs/common/simlib.v
- Add to techlibs/common/techmap.v
Things to do after finalizing the cell interface:
- Add support to kernel/satgen.h for the new cell type
- Add to manual/CHAPTER_CellLib.tex (or just add a fixme to the bottom)
- Maybe add support to the Verilog backend for dumping such cells as expression
Checklist for creating Yosys releases
=====================================
Update the CHANGELOG file:
cd ~yosys
gitk &
vi CHANGELOG
Update and check documentation:
cd ~yosys
make update-manual
make manual
- sanity check the figures in the appnotes and presentation
- if there are any odd things -> investigate
- make cosmetic changes to the .tex files if necessary
cd ~yosys
vi README guidelines/*
- is the information provided in those file still up to date
Then with default config setting:
cd ~yosys
make vgtest
cd ~yosys
./yosys -p 'proc; show' tests/simple/fiedler-cooley.v
./yosys -p 'proc; opt; show' tests/simple/fiedler-cooley.v
./yosys -p 'synth; show' tests/simple/fiedler-cooley.v
./yosys -p 'synth_xilinx -top up3down5; show' tests/simple/fiedler-cooley.v
cd ~yosys/examples/cmos
bash testbench.sh
cd ~yosys/examples/basys3
bash run.sh
Test building plugins with various of the standard passes:
yosys-config --build test.so equiv_simple.cc
- also check the code examples in guidelines/GettingStarted
And if a version of the verific library is currently available:
cd ~yosys
cat frontends/verific/build_amd64.txt
- follow instructions
cd frontends/verific
../../yosys test_navre.ys
Finally run all tests with "make config-{clang,gcc,gcc-4.8}":
cd ~yosys
make clean
make test
make ystests
make vloghtb
make install
cd ~yosys-bigsim
make clean
make full
cd ~vloghammer
make purge gen_issues gen_samples
make SYN_LIST="yosys" SIM_LIST="icarus yosim verilator" REPORT_FULL=1 world
chromium-browser report.html
Release:
- set YOSYS_VER to x.y.z in Makefile
- remove "bumpversion" target from Makefile
- update version string in CHANGELOG
git commit -am "Yosys x.y.z"
- push tag to github
- post changelog on github
- post short release note on reddit
Updating the website:
cd ~yosys
make manual
make install
- update pdf files on the website
cd ~yosys-web
make update_cmd
make update_show
git commit -am update
make push

5
CodeOfConduct → guidelines/CodeOfConduct
View File

@ -55,9 +55,8 @@ further defined and clarified by project maintainers.
Enforcement
Instances of abusive, harassing, or otherwise unacceptable behavior may be
reported by contacting the project team at clifford@clifford.at (and/or
cliffordvienna@gmail.com if you think your mail to the other address got
stuck in the spam filter). All complaints will be reviewed and investigated and
reported by contacting the project team at contact@yosyshq.com and/or
claire@clairexen.net. All complaints will be reviewed and investigated and
will result in a response that is deemed necessary and appropriate to the
circumstances. The project team is obligated to maintain confidentiality with
regard to the reporter of an incident. Further details of specific enforcement

35
guidelines/CodingStyle Normal file
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@ -0,0 +1,35 @@
Coding Style
============
Formatting of code
------------------
- Yosys code is using tabs for indentation. Tabs are 8 characters.
- A continuation of a statement in the following line is indented by
two additional tabs.
- Lines are as long as you want them to be. A good rule of thumb is
to break lines at about column 150.
- Opening braces can be put on the same or next line as the statement
opening the block (if, switch, for, while, do). Put the opening brace
on its own line for larger blocks, especially blocks that contains
blank lines.
- Otherwise stick to the Linux Kernel Coding Style:
https://www.kernel.org/doc/Documentation/CodingStyle
C++ Language
-------------
Yosys is written in C++11. At the moment only constructs supported by
gcc 4.8 are allowed in Yosys code. This will change in future releases.
In general Yosys uses "int" instead of "size_t". To avoid compiler
warnings for implicit type casts, always use "GetSize(foobar)" instead
of "foobar.size()". (GetSize() is defined in kernel/yosys.h)
Use range-based for loops whenever applicable.

309
CodingReadme → guidelines/GettingStarted
View File

@ -1,10 +1,3 @@
This file contains some very brief documentation on things like programming APIs.
Also consult the Yosys manual and the section about programming in the presentation.
(Both can be downloaded as PDF from the yosys webpage.)
--snip-- only the lines below this mark are included in the yosys manual --snip--
Getting Started
===============
@ -253,304 +246,4 @@ Notes on the existing codebase
For historical reasons not all parts of Yosys adhere to the current coding
style. When adding code to existing parts of the system, adhere to this guide
for the new code instead of trying to mimic the style of the surrounding code.
Coding Style
============
Formatting of code
------------------
- Yosys code is using tabs for indentation. Tabs are 8 characters.
- A continuation of a statement in the following line is indented by
two additional tabs.
- Lines are as long as you want them to be. A good rule of thumb is
to break lines at about column 150.
- Opening braces can be put on the same or next line as the statement
opening the block (if, switch, for, while, do). Put the opening brace
on its own line for larger blocks, especially blocks that contains
blank lines.
- Otherwise stick to the Linux Kernel Coding Style:
https://www.kernel.org/doc/Documentation/CodingStyle
C++ Language
-------------
Yosys is written in C++11. At the moment only constructs supported by
gcc 4.8 are allowed in Yosys code. This will change in future releases.
In general Yosys uses "int" instead of "size_t". To avoid compiler
warnings for implicit type casts, always use "GetSize(foobar)" instead
of "foobar.size()". (GetSize() is defined in kernel/yosys.h)
Use range-based for loops whenever applicable.
--snap-- only the lines above this mark are included in the yosys manual --snap--
Creating the Visual Studio Template Project
===========================================
1. Create an empty Visual C++ Win32 Console App project
Microsoft Visual Studio Express 2013 for Windows Desktop
Open New Project Wizard (File -> New Project..)
Project Name: YosysVS
Solution Name: YosysVS
[X] Create directory for solution
[ ] Add to source control
[X] Console applications
[X] Empty Project
[ ] SDL checks
2. Open YosysVS Project Properties
Select Configuration: All Configurations
C/C++ -> General -> Additional Include Directories
Add: ..\yosys
C/C++ -> Preprocessor -> Preprocessor Definitions
Add: _YOSYS_;_CRT_SECURE_NO_WARNINGS
3. Resulting file system tree:
YosysVS/
YosysVS/YosysVS
YosysVS/YosysVS/YosysVS.vcxproj
YosysVS/YosysVS/YosysVS.vcxproj.filters
YosysVS/YosysVS.sdf
YosysVS/YosysVS.sln
YosysVS/YosysVS.v12.suo
4. Zip YosysVS as YosysVS-Tpl-v1.zip
Checklist for adding internal cell types
========================================
Things to do right away:
- Add to kernel/celltypes.h (incl. eval() handling for non-mem cells)
- Add to InternalCellChecker::check() in kernel/rtlil.cc
- Add to techlibs/common/simlib.v
- Add to techlibs/common/techmap.v
Things to do after finalizing the cell interface:
- Add support to kernel/satgen.h for the new cell type
- Add to manual/CHAPTER_CellLib.tex (or just add a fixme to the bottom)
- Maybe add support to the Verilog backend for dumping such cells as expression
Checklist for creating Yosys releases
=====================================
Update the CHANGELOG file:
cd ~yosys
gitk &
vi CHANGELOG
Update and check documentation:
cd ~yosys
make update-manual
make manual
- sanity check the figures in the appnotes and presentation
- if there are any odd things -> investigate
- make cosmetic changes to the .tex files if necessary
cd ~yosys
vi README CodingReadme
- is the information provided in those file still up to date
Then with default config setting:
cd ~yosys
make vgtest
cd ~yosys
./yosys -p 'proc; show' tests/simple/fiedler-cooley.v
./yosys -p 'proc; opt; show' tests/simple/fiedler-cooley.v
./yosys -p 'synth; show' tests/simple/fiedler-cooley.v
./yosys -p 'synth_xilinx -top up3down5; show' tests/simple/fiedler-cooley.v
cd ~yosys/examples/cmos
bash testbench.sh
cd ~yosys/examples/basys3
bash run.sh
Test building plugins with various of the standard passes:
yosys-config --build test.so equiv_simple.cc
- also check the code examples in CodingReadme
And if a version of the verific library is currently available:
cd ~yosys
cat frontends/verific/build_amd64.txt
- follow instructions
cd frontends/verific
../../yosys test_navre.ys
Finally run all tests with "make config-{clang,gcc,gcc-4.8}":
cd ~yosys
make clean
make test
make ystests
make vloghtb
make install
cd ~yosys-bigsim
make clean
make full
cd ~vloghammer
make purge gen_issues gen_samples
make SYN_LIST="yosys" SIM_LIST="icarus yosim verilator" REPORT_FULL=1 world
chromium-browser report.html
Release:
- set YOSYS_VER to x.y.z in Makefile
- remove "bumpversion" target from Makefile
- update version string in CHANGELOG
git commit -am "Yosys x.y.z"
- push tag to github
- post changelog on github
- post short release note on reddit
Updating the website:
cd ~yosys
make manual
make install
- update pdf files on the website
cd ~yosys-web
make update_cmd
make update_show
git commit -am update
make push
Cross-Building for Windows with MXE
===================================
Check http://mxe.cc/#requirements and install all missing requirements.
As root (or other user with write access to /usr/local/src):
cd /usr/local/src
git clone https://github.com/mxe/mxe.git
cd mxe
make -j$(nproc) MXE_PLUGIN_DIRS="plugins/tcl.tk" \
MXE_TARGETS="i686-w64-mingw32.static" \
gcc tcl readline
Then as regular user in some directory where you build stuff:
git clone https://github.com/cliffordwolf/yosys.git yosys-win32
cd yosys-win32
make config-mxe
make -j$(nproc) mxebin
How to add unit test
====================
Unit test brings some advantages, briefly, we can list some of them (reference
[1](https://en.wikipedia.org/wiki/Unit_testing)):
* Tests reduce bugs in new features;
* Tests reduce bugs in existing features;
* Tests are good documentation;
* Tests reduce the cost of change;
* Tests allow refactoring;
With those advantages in mind, it was required to choose a framework which fits
well with C/C++ code. Hence, it was chosen (google test)
[https://github.com/google/googletest], because it is largely used and it is
relatively easy learn.
Install and configure google test (manually)
--------------------------------------------
In this section, you will see a brief description of how to install google
test. However, it is strongly recommended that you take a look to the official
repository (https://github.com/google/googletest) and refers to that if you
have any problem to install it. Follow the steps below:
* Install: cmake and pthread
* Clone google test project from: https://github.com/google/googletest and
enter in the project directory
* Inside project directory, type:
```
cmake -DBUILD_SHARED_LIBS=ON .
make
```
* After compilation, copy all "*.so" inside directory "googlemock" and
"googlemock/gtest" to "/usr/lib/"
* Done! Now you can compile your tests.
If you have any problem, go to the official repository to find help.
Ps.: Some distros already have googletest packed. If your distro supports it,
you can use it instead of compile.
Create new unit test
--------------------
If you want to add new unit tests for Yosys, just follow the steps below:
* Go to directory "yosys/test/unit/"
* In this directory you can find something similar Yosys's directory structure.
To create your unit test file you have to follow this pattern:
fileNameToImplementUnitTest + Test.cc. E.g.: if you want to implement the
unit test for kernel/celledges.cc, you will need to create a file like this:
tests/unit/kernel/celledgesTest.cc;
* Implement your unit test
Run unit test
-------------
To compile and run all unit tests, just go to yosys root directory and type:
```
make unit-test
```
If you want to remove all unit test files, type:
```
make clean-unit-test
```
for the new code instead of trying to mimic the style of the surrounding code.

69
guidelines/UnitTests Normal file
View File

@ -0,0 +1,69 @@
How to add unit test
====================
Unit test brings some advantages, briefly, we can list some of them (reference
[1](https://en.wikipedia.org/wiki/Unit_testing)):
* Tests reduce bugs in new features;
* Tests reduce bugs in existing features;
* Tests are good documentation;
* Tests reduce the cost of change;
* Tests allow refactoring;
With those advantages in mind, it was required to choose a framework which fits
well with C/C++ code. Hence, it was chosen (google test)
[https://github.com/google/googletest], because it is largely used and it is
relatively easy learn.
Install and configure google test (manually)
--------------------------------------------
In this section, you will see a brief description of how to install google
test. However, it is strongly recommended that you take a look to the official
repository (https://github.com/google/googletest) and refers to that if you
have any problem to install it. Follow the steps below:
* Install: cmake and pthread
* Clone google test project from: https://github.com/google/googletest and
enter in the project directory
* Inside project directory, type:
```
cmake -DBUILD_SHARED_LIBS=ON .
make
```
* After compilation, copy all "*.so" inside directory "googlemock" and
"googlemock/gtest" to "/usr/lib/"
* Done! Now you can compile your tests.
If you have any problem, go to the official repository to find help.
Ps.: Some distros already have googletest packed. If your distro supports it,
you can use it instead of compile.
Create new unit test
--------------------
If you want to add new unit tests for Yosys, just follow the steps below:
* Go to directory "yosys/test/unit/"
* In this directory you can find something similar Yosys's directory structure.
To create your unit test file you have to follow this pattern:
fileNameToImplementUnitTest + Test.cc. E.g.: if you want to implement the
unit test for kernel/celledges.cc, you will need to create a file like this:
tests/unit/kernel/celledgesTest.cc;
* Implement your unit test
Run unit test
-------------
To compile and run all unit tests, just go to yosys root directory and type:
```
make unit-test
```
If you want to remove all unit test files, type:
```
make clean-unit-test
```

83
guidelines/Windows Normal file
View File

@ -0,0 +1,83 @@
Creating the Visual Studio Template Project
===========================================
1. Create an empty Visual C++ Win32 Console App project
Microsoft Visual Studio Express 2013 for Windows Desktop
Open New Project Wizard (File -> New Project..)
Project Name: YosysVS
Solution Name: YosysVS
[X] Create directory for solution
[ ] Add to source control
[X] Console applications
[X] Empty Project
[ ] SDL checks
2. Open YosysVS Project Properties
Select Configuration: All Configurations
C/C++ -> General -> Additional Include Directories
Add: ..\yosys
C/C++ -> Preprocessor -> Preprocessor Definitions
Add: _YOSYS_;_CRT_SECURE_NO_WARNINGS
3. Resulting file system tree:
YosysVS/
YosysVS/YosysVS
YosysVS/YosysVS/YosysVS.vcxproj
YosysVS/YosysVS/YosysVS.vcxproj.filters
YosysVS/YosysVS.sdf
YosysVS/YosysVS.sln
YosysVS/YosysVS.v12.suo
4. Zip YosysVS as YosysVS-Tpl-v1.zip
Compiling with Visual Studio
============================
Visual Studio builds are not directly supported by build scripts, but they are still possible.
1. Easy way
- Go to https://github.com/YosysHQ/yosys/actions/workflows/vs.yml?query=branch%3Amaster
- Click on the most recent completed run
- In Artifacts region find vcxsrc and click on it to download
- Unpack downloaded ZIP file
- Open YosysVS.sln with Visual Studio
2. Using WSL or MSYS2
- Make sure to have make, python3 and git available
- Git clone yosys repository
- Execute ```make vcxsrc YOSYS_VER=latest```
- File yosys-win32-vcxsrc-latest.zip will be created
- Transfer that file to location visible by Windows application
- Unpack ZIP
- Open YosysVS.sln with Visual Studio
Cross-Building for Windows with MXE
===================================
Check http://mxe.cc/#requirements and install all missing requirements.
As root (or other user with write access to /usr/local/src):
cd /usr/local/src
git clone https://github.com/mxe/mxe.git
cd mxe
make -j$(nproc) MXE_PLUGIN_DIRS="plugins/tcl.tk" \
MXE_TARGETS="i686-w64-mingw32.static" \
gcc tcl readline
Then as regular user in some directory where you build stuff:
git clone https://github.com/YosysHQ/yosys.git yosys-win32
cd yosys-win32
make config-mxe
make -j$(nproc) mxebin

29
kernel/binding.cc Normal file
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@ -0,0 +1,29 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "binding.h"
YOSYS_NAMESPACE_BEGIN
RTLIL::Binding::Binding(RTLIL::IdString target_type,
RTLIL::IdString target_name)
: target_type(target_type), target_name(target_name)
{}
YOSYS_NAMESPACE_END

60
kernel/binding.h Normal file
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@ -0,0 +1,60 @@
/* -*- c++ -*-
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#ifndef BINDING_H
#define BINDING_H
#include "kernel/rtlil.h"
YOSYS_NAMESPACE_BEGIN
struct RTLIL::Binding
{
// Represents a bind construct.
//
// The target of the binding is represented by target_type and
// target_name (see comments above the fields).
Binding(RTLIL::IdString target_type,
RTLIL::IdString target_name);
virtual ~Binding() {}
// Return a string describing the binding
virtual std::string describe() const = 0;
protected:
// May be empty. If not, it's the name of the module or interface to
// bind to.
RTLIL::IdString target_type;
// If target_type is nonempty (the usual case), this is a hierarchical
// reference to the bind target. If target_type is empty, we have to
// wait until the hierarchy pass to figure out whether this was the name
// of a module/interface type or an instance.
RTLIL::IdString target_name;
// An attribute name which contains an ID that's unique across binding
// instances (used to ensure we don't apply a binding twice to a module)
RTLIL::IdString attr_name;
};
YOSYS_NAMESPACE_END
#endif

2
kernel/bitpattern.h
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@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

53
kernel/calc.cc
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -609,5 +609,56 @@ RTLIL::Const RTLIL::const_neg(const RTLIL::Const &arg1, const RTLIL::Const&, boo
return RTLIL::const_sub(zero, arg1_ext, true, signed1, result_len);
}
RTLIL::Const RTLIL::const_bmux(const RTLIL::Const &arg1, const RTLIL::Const &arg2)
{
std::vector<RTLIL::State> t = arg1.bits;
for (int i = GetSize(arg2)-1; i >= 0; i--)
{
RTLIL::State sel = arg2.bits.at(i);
std::vector<RTLIL::State> new_t;
if (sel == State::S0)
new_t = std::vector<RTLIL::State>(t.begin(), t.begin() + GetSize(t)/2);
else if (sel == State::S1)
new_t = std::vector<RTLIL::State>(t.begin() + GetSize(t)/2, t.end());
else
for (int j = 0; j < GetSize(t)/2; j++)
new_t.push_back(t[j] == t[j + GetSize(t)/2] ? t[j] : RTLIL::Sx);
t.swap(new_t);
}
return t;
}
RTLIL::Const RTLIL::const_demux(const RTLIL::Const &arg1, const RTLIL::Const &arg2)
{
int width = GetSize(arg1);
int s_width = GetSize(arg2);
std::vector<RTLIL::State> res;
for (int i = 0; i < (1 << s_width); i++)
{
bool ne = false;
bool x = false;
for (int j = 0; j < s_width; j++) {
bool bit = i & 1 << j;
if (arg2[j] == (bit ? RTLIL::S0 : RTLIL::S1))
ne = true;
else if (arg2[j] != RTLIL::S0 && arg2[j] != RTLIL::S1)
x = true;
}
if (ne) {
for (int j = 0; j < width; j++)
res.push_back(State::S0);
} else if (x) {
for (int j = 0; j < width; j++)
res.push_back(arg1.bits[j] == State::S0 ? State::S0 : State::Sx);
} else {
for (int j = 0; j < width; j++)
res.push_back(arg1.bits[j]);
}
}
return res;
}
YOSYS_NAMESPACE_END

2
kernel/cellaigs.cc
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@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

2
kernel/cellaigs.h
View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

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