riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Cleanup

This commit is contained in:
Miodrag Milanovic 2022-01-31 13:45:28 +01:00
parent eabd0ff115
commit 1b5ff92e62
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
passes/sat/sim.cc
View File

@ -768,7 +768,6 @@ struct SimInstance
retVal = true;
}
}
//log("signal: %s fst: %s sim: %s\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
}
for (auto child : children)
retVal |= child.second->checkSignals(time);
@ -1048,6 +1047,7 @@ struct SimWorker : SimShared
fst->reconstructAllAtTimes(edges);
bool initial = false;
int cycle = 0;
log("Co-simulation from %zu%s to %zu%s\n", startCount, fst->getTimescaleString(), stopCount, fst->getTimescaleString());
for(auto &time : edges) {
log("Co-simulating cycle %d [%zu%s].\n", cycle+1, time, fst->getTimescaleString());
for(auto &item : inputs) {