mirror of https://github.com/YosysHQ/yosys.git
memory_dff: Fix needlessly duplicating enable bits.
When the register being merged into the EN signal happens to be a $sdff, the current code creates a new $mux for every bit, even if they happen to be identical (as is usually the case), preventing proper grouping further down the flow. Fix this by adding a simple cache. Fixes #2409.
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@ -46,8 +46,15 @@ struct MemoryDffWorker
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{
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sigmap.apply(sig);
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dict<SigBit, SigBit> cache;
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for (auto &bit : sig)
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{
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if (cache.count(bit)) {
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bit = cache[bit];
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continue;
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}
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if (bit.wire == NULL)
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continue;
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@ -103,6 +110,7 @@ struct MemoryDffWorker
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d = module->Mux(NEW_ID, rbit, d, cell->getPort(ID::SRST));
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}
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cache[bit] = d;
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bit = d;
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clk = this_clk;
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clk_polarity = this_clk_polarity;
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@ -0,0 +1,24 @@
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read_verilog <<EOT
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module t (...);
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input CLK;
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input [10:0] A;
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input WE;
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input C;
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input [7:0] DI;
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output reg [7:0] DO;
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reg [7:0] mem[2047:0];
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always @(posedge CLK) begin
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if (C)
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if (WE)
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mem[A] <= DI;
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DO <= mem[A];
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end
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endmodule
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EOT
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synth_ecp5
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select -assert-count 1 t:DP16KD
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