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techmap: Add _TECHMAP_CELLNAME_ special parameter. 

This parameter will resolve to the name of the cell being mapped.  The
first user of this parameter will be synth_intel_alm's Quartus output,
which requires a unique (and preferably descriptive) name passed as
a cell parameter for the memory cells.
This commit is contained in:
Marcelina Kościelnicka 2020-07-21 15:00:54 +02:00
parent 57af8499df
commit dc07ae9677
4 changed files with 50 additions and 1 deletions
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3
CHANGELOG
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@ -39,7 +39,7 @@ Yosys 0.9 .. Yosys 0.9-dev
- Improvements in pmgen: slices, choices, define, generate
- Added "xilinx_srl" for Xilinx shift register extraction
- Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
- Added "_TECHMAP_WIREINIT_*_" attribute and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
- Added "_TECHMAP_WIREINIT_*_" parameter and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
- Added "-match-init" option to "dff2dffs" pass
- Added "techmap_autopurge" support to techmap
- Added "add -mod <modname[s]>"
@ -69,6 +69,7 @@ Yosys 0.9 .. Yosys 0.9-dev
- Added $divfloor and $modfloor cells
- Added $adffe, $dffsre, $sdff, $sdffe, $sdffce, $adlatch cells
- Added "dfflegalize" pass
- Added "_TECHMAP_CELLNAME_" parameter for "techmap" pass
Yosys 0.8 .. Yosys 0.9
----------------------

1
kernel/constids.inc
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@ -172,6 +172,7 @@ X(T)
X(TABLE)
X(techmap_autopurge)
X(_TECHMAP_BITS_CONNMAP_)
X(_TECHMAP_CELLNAME_)
X(_TECHMAP_CELLTYPE_)
X(techmap_celltype)
X(_TECHMAP_FAIL_)

6
passes/techmap/techmap.cc
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@ -643,6 +643,8 @@ struct TechmapWorker
if (tpl->avail_parameters.count(ID::_TECHMAP_CELLTYPE_) != 0)
parameters.emplace(ID::_TECHMAP_CELLTYPE_, RTLIL::unescape_id(cell->type));
if (tpl->avail_parameters.count(ID::_TECHMAP_CELLNAME_) != 0)
parameters.emplace(ID::_TECHMAP_CELLNAME_, RTLIL::unescape_id(cell->name));
for (auto &conn : cell->connections()) {
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first))) != 0) {
@ -1111,6 +1113,10 @@ struct TechmapPass : public Pass {
log(" When a parameter with this name exists, it will be set to the type name\n");
log(" of the cell that matches the module.\n");
log("\n");
log(" _TECHMAP_CELLNAME_\n");
log(" When a parameter with this name exists, it will be set to the name\n");
log(" of the cell that matches the module.\n");
log("\n");
log(" _TECHMAP_CONSTMSK_<port-name>_\n");
log(" _TECHMAP_CONSTVAL_<port-name>_\n");
log(" When this pair of parameters is available in a module for a port, then\n");

41
tests/techmap/cellname.ys Normal file
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@ -0,0 +1,41 @@
read_verilog << EOT
module sub (input i, output o);
parameter _TECHMAP_CELLNAME_ = "";
namedsub #(.name(_TECHMAP_CELLNAME_)) _TECHMAP_REPLACE_ (i, o);
endmodule
EOT
design -stash map
read_verilog << EOT
(* blackbox *)
module sub (input i, output o);
endmodule
(* blackbox *)
module namedsub (input i, output o);
parameter name = "";
endmodule
module top(input [3:0] i, output [3:0] o);
sub s1 (i[0], o[0]);
sub subsubsub (i[1], o[1]);
sub s2 (i[2], o[2]);
sub xxx (i[3], o[3]);
endmodule
EOT
techmap -map %map
select -assert-count 4 t:namedsub
select -assert-count 0 t:sub
select -assert-count 1 t:namedsub r:name=s1 %i
select -assert-count 1 t:namedsub r:name=subsubsub %i
select -assert-count 1 t:namedsub r:name=s2 %i
select -assert-count 1 t:namedsub r:name=xxx %i