mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #3232 from YosysHQ/micko/fst2tb
Added fst2tb pass for generating testbench
This commit is contained in:
Miodrag Milanović
GitHub
commit
25d6fdfea7
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@ -1327,6 +1327,210 @@ struct SimWorker : SimShared
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register_output_step(10*cycle);
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write_output_files();
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}
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std::string define_signal(Wire *wire)
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{
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std::stringstream f;
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if (wire->width==1)
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f << stringf("%s", RTLIL::unescape_id(wire->name).c_str());
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else
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if (wire->upto)
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f << stringf("[%d:%d] %s", wire->start_offset, wire->width - 1 + wire->start_offset, RTLIL::unescape_id(wire->name).c_str());
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else
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f << stringf("[%d:%d] %s", wire->width - 1 + wire->start_offset, wire->start_offset, RTLIL::unescape_id(wire->name).c_str());
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return f.str();
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}
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std::string signal_list(std::map<Wire*,fstHandle> &signals)
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{
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std::stringstream f;
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for(auto item=signals.begin();item!=signals.end();item++)
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f << stringf("%c%s", (item==signals.begin() ? ' ' : ','), RTLIL::unescape_id(item->first->name).c_str());
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return f.str();
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}
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void generate_tb(Module *topmod, std::string tb_filename, int numcycles)
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{
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fst = new FstData(sim_filename);
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if (scope.empty())
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log_error("Scope must be defined for co-simulation.\n");
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if ((clock.size()+clockn.size())==0)
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log_error("Clock signal must be specified.\n");
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std::vector<fstHandle> fst_clock;
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std::map<Wire*,fstHandle> clocks;
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for (auto portname : clock)
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{
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Wire *w = topmod->wire(portname);
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if (!w)
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log_error("Can't find port %s on module %s.\n", log_id(portname), log_id(top->module));
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if (!w->port_input)
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log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module));
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fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
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if (id==0)
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log_error("Can't find port %s.%s in FST.\n", scope.c_str(), log_id(portname));
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fst_clock.push_back(id);
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clocks[w] = id;
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}
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for (auto portname : clockn)
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{
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Wire *w = topmod->wire(portname);
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if (!w)
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log_error("Can't find port %s on module %s.\n", log_id(portname), log_id(top->module));
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if (!w->port_input)
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log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module));
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fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
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if (id==0)
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log_error("Can't find port %s.%s in FST.\n", scope.c_str(), log_id(portname));
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fst_clock.push_back(id);
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clocks[w] = id;
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}
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SigMap sigmap(topmod);
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std::map<Wire*,fstHandle> inputs;
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std::map<Wire*,fstHandle> outputs;
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for (auto wire : topmod->wires()) {
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fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
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if (id==0 && (wire->port_input || wire->port_output))
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log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name)).c_str());
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if (wire->port_input)
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if (clocks.find(wire)==clocks.end())
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inputs[wire] = id;
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if (wire->port_output)
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outputs[wire] = id;
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}
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uint64_t startCount = 0;
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uint64_t stopCount = 0;
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if (start_time==0) {
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if (start_time < fst->getStartTime())
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log_warning("Start time is before simulation file start time\n");
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startCount = fst->getStartTime();
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} else if (start_time==-1)
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startCount = fst->getEndTime();
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else {
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startCount = start_time / fst->getTimescale();
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if (startCount > fst->getEndTime()) {
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startCount = fst->getEndTime();
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log_warning("Start time is after simulation file end time\n");
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}
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}
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if (stop_time==0) {
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if (stop_time < fst->getStartTime())
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log_warning("Stop time is before simulation file start time\n");
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stopCount = fst->getStartTime();
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} else if (stop_time==-1)
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stopCount = fst->getEndTime();
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else {
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stopCount = stop_time / fst->getTimescale();
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if (stopCount > fst->getEndTime()) {
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stopCount = fst->getEndTime();
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log_warning("Stop time is after simulation file end time\n");
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}
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}
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if (stopCount<startCount) {
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log_error("Stop time is before start time\n");
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}
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int cycle = 0;
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log("Generate testbench data from %lu%s to %lu%s", (unsigned long)startCount, fst->getTimescaleString(), (unsigned long)stopCount, fst->getTimescaleString());
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if (cycles_set)
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log(" for %d clock cycle(s)",numcycles);
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log("\n");
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std::stringstream f;
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f << stringf("`timescale 1%s/1%s\n", fst->getTimescaleString(),fst->getTimescaleString());
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f << stringf("module %s();\n",tb_filename.c_str());
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int clk_len = 0;
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int inputs_len = 0;
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int outputs_len = 0;
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for(auto &item : clocks) {
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clk_len += item.first->width;
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f << "\treg " << define_signal(item.first) << ";\n";
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}
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for(auto &item : inputs) {
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inputs_len += item.first->width;
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f << "\treg " << define_signal(item.first) << ";\n";
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}
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for(auto &item : outputs) {
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outputs_len += item.first->width;
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f << "\twire " << define_signal(item.first) << ";\n";
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}
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int data_len = clk_len + inputs_len + outputs_len + 32;
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f << "\n";
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f << stringf("\t%s uut(",RTLIL::unescape_id(topmod->name).c_str());
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for(auto item=clocks.begin();item!=clocks.end();item++)
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f << stringf("%c.%s(%s)", (item==clocks.begin() ? ' ' : ','), RTLIL::unescape_id(item->first->name).c_str(), RTLIL::unescape_id(item->first->name).c_str());
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for(auto &item : inputs)
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f << stringf(",.%s(%s)", RTLIL::unescape_id(item.first->name).c_str(), RTLIL::unescape_id(item.first->name).c_str());
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for(auto &item : outputs)
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f << stringf(",.%s(%s)", RTLIL::unescape_id(item.first->name).c_str(), RTLIL::unescape_id(item.first->name).c_str());
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f << ");\n";
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f << "\n";
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f << "\tinteger i;\n";
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uint64_t prev_time = startCount;
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log("Writing data to `%s`\n", (tb_filename+".txt").c_str());
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std::ofstream data_file(tb_filename+".txt");
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try {
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fst->reconstructAllAtTimes(fst_clock, startCount, stopCount, [&](uint64_t time) {
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for(auto &item : clocks)
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data_file << stringf("%s",fst->valueOf(item.second).c_str());
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for(auto &item : inputs)
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data_file << stringf("%s",fst->valueOf(item.second).c_str());
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for(auto &item : outputs)
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data_file << stringf("%s",fst->valueOf(item.second).c_str());
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data_file << stringf("%s\n",Const(time-prev_time).as_string().c_str());
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cycle++;
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prev_time = time;
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// Limit to number of cycles if provided
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if (cycles_set && cycle > numcycles *2)
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throw fst_end_of_data_exception();
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if (time==stopCount)
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throw fst_end_of_data_exception();
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});
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} catch(fst_end_of_data_exception) {
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// end of data detected
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}
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f << stringf("\treg [0:%d] data [0:%d];\n", data_len-1, cycle-1);
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f << "\tinitial begin;\n";
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f << stringf("\t\t$dumpfile(\"%s\");\n",tb_filename.c_str());
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f << stringf("\t\t$dumpvars(0,%s);\n",tb_filename.c_str());
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f << stringf("\t\t$readmemb(\"%s.txt\", data);\n",tb_filename.c_str());
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f << stringf("\t\t#(data[0][%d:%d]);\n", data_len-32, data_len-1);
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f << stringf("\t\t{%s } = data[0][%d:%d];\n", signal_list(clocks).c_str(), 0, clk_len-1);
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f << stringf("\t\t{%s } <= data[0][%d:%d];\n", signal_list(inputs).c_str(), clk_len, clk_len+inputs_len-1);
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f << stringf("\t\tfor (i = 1; i < %d; i++) begin\n",cycle);
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f << stringf("\t\t\t#(data[i][%d:%d]);\n", data_len-32, data_len-1);
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f << stringf("\t\t\t{%s } = data[i][%d:%d];\n", signal_list(clocks).c_str(), 0, clk_len-1);
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f << stringf("\t\t\t{%s } <= data[i][%d:%d];\n", signal_list(inputs).c_str(), clk_len, clk_len+inputs_len-1);
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f << stringf("\t\t\tif ({%s } != data[i-1][%d:%d]) begin\n", signal_list(outputs).c_str(), clk_len+inputs_len, clk_len+inputs_len+outputs_len-1);
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f << "\t\t\t\t$error(\"Signal difference detected\\n\");\n";
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f << "\t\t\tend\n";
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f << "\t\tend\n";
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f << "\t\t$finish;\n";
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f << "\tend\n";
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f << "endmodule\n";
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log("Writing testbench to `%s`\n", (tb_filename+".v").c_str());
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std::ofstream tb_file(tb_filename+".v");
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tb_file << f.str();
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delete fst;
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}
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};
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struct VCDWriter : public OutputWriter
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@ -1825,4 +2029,119 @@ struct SimPass : public Pass {
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}
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} SimPass;
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struct Fst2TbPass : public Pass {
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Fst2TbPass() : Pass("fst2tb", "generate testbench out of fst file") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" fst2tb [options] [top-level]\n");
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log("\n");
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log("This command generates testbench for the circuit using the given top-level module\n");
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log("and simulus signal from FST file\n");
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log("\n");
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log(" -tb <name>\n");
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log(" generated testbench name.\n");
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log(" files <name>.v and <name>.txt are created as result.\n");
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log("\n");
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log(" -r <filename>\n");
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log(" read simulation FST file\n");
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log("\n");
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log(" -clock <portname>\n");
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log(" name of top-level clock input\n");
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log("\n");
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log(" -clockn <portname>\n");
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log(" name of top-level clock input (inverse polarity)\n");
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log("\n");
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log(" -scope <name>\n");
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log(" scope of simulation top model\n");
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log("\n");
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log(" -start <time>\n");
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log(" start co-simulation in arbitary time (default 0)\n");
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log("\n");
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log(" -stop <time>\n");
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log(" stop co-simulation in arbitary time (default END)\n");
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log("\n");
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log(" -n <integer>\n");
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log(" number of clock cycles to simulate (default: 20)\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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SimWorker worker;
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int numcycles = 20;
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bool stop_set = false;
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std::string tb_filename;
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log_header(design, "Executing FST2FB pass.\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-clock" && argidx+1 < args.size()) {
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worker.clock.insert(RTLIL::escape_id(args[++argidx]));
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continue;
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}
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if (args[argidx] == "-clockn" && argidx+1 < args.size()) {
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worker.clockn.insert(RTLIL::escape_id(args[++argidx]));
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continue;
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}
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if (args[argidx] == "-r" && argidx+1 < args.size()) {
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std::string sim_filename = args[++argidx];
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rewrite_filename(sim_filename);
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worker.sim_filename = sim_filename;
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continue;
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}
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if (args[argidx] == "-n" && argidx+1 < args.size()) {
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numcycles = atoi(args[++argidx].c_str());
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worker.cycles_set = true;
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continue;
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}
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if (args[argidx] == "-scope" && argidx+1 < args.size()) {
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worker.scope = args[++argidx];
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continue;
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}
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if (args[argidx] == "-start" && argidx+1 < args.size()) {
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worker.start_time = stringToTime(args[++argidx]);
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continue;
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}
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if (args[argidx] == "-stop" && argidx+1 < args.size()) {
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worker.stop_time = stringToTime(args[++argidx]);
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stop_set = true;
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continue;
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}
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if (args[argidx] == "-tb" && argidx+1 < args.size()) {
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tb_filename = args[++argidx];
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (stop_set && worker.cycles_set)
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log_error("'stop' and 'n' can only be used exclusively'\n");
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Module *top_mod = nullptr;
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if (design->full_selection()) {
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top_mod = design->top_module();
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if (!top_mod)
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log_cmd_error("Design has no top module, use the 'hierarchy' command to specify one.\n");
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} else {
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auto mods = design->selected_whole_modules();
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if (GetSize(mods) != 1)
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log_cmd_error("Only one top module must be selected.\n");
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top_mod = mods.front();
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}
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if (tb_filename.empty())
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log_cmd_error("Testbench name must be defined.\n");
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if (worker.sim_filename.empty())
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log_cmd_error("Stimulus FST file must be defined.\n");
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worker.generate_tb(top_mod, tb_filename, numcycles);
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}
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} Fst2TbPass;
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PRIVATE_NAMESPACE_END
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