mirror of https://github.com/YosysHQ/yosys.git
flatten: rewrite memid in memwr actions.
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@ -122,6 +122,9 @@ struct FlattenWorker
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for (auto &tpl_proc_it : tpl->processes) {
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RTLIL::Process *new_proc = module->addProcess(map_name(cell, tpl_proc_it.second), tpl_proc_it.second);
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map_attributes(cell, new_proc, tpl_proc_it.second->name);
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for (auto new_proc_sync : new_proc->syncs)
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for (auto &memwr_action : new_proc_sync->mem_write_actions)
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memwr_action.memid = memory_map.at(memwr_action.memid).str();
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auto rewriter = [&](RTLIL::SigSpec &sig) { map_sigspec(wire_map, sig); };
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new_proc->rewrite_sigspecs(rewriter);
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design->select(module, new_proc);
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