mirror of https://github.com/YosysHQ/yosys.git
Ensure \A_SIGNED is never used with $shiftx
It has no effect on the output ($shiftx doesn't perform any sign extension whatsoever), so an attempt to use it should be caught early.
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@ -1035,7 +1035,11 @@ namespace {
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}
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if (cell->type.in(ID($shift), ID($shiftx))) {
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param_bool(ID::A_SIGNED);
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if (cell->type == ID($shiftx)) {
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param_bool(ID::A_SIGNED, /*expected=*/false);
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} else {
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param_bool(ID::A_SIGNED);
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}
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param_bool(ID::B_SIGNED);
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port(ID::A, param(ID::A_WIDTH));
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port(ID::B, param(ID::B_WIDTH));
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@ -264,6 +264,10 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
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cell->setPort(ID::Y, wire);
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}
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if (cell_type.in(ID($shiftx))) {
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cell->parameters[ID::A_SIGNED] = false;
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}
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if (cell_type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
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cell->parameters[ID::B_SIGNED] = false;
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}
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