mirror of https://github.com/YosysHQ/yosys.git
parent
3d2aef0bde
commit
d245e2bae5
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@ -76,22 +76,33 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did
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}
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else
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{
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bool all_fully_def = true;
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for (auto cs : sw->cases)
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{
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if (max_depth != 0)
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proc_clean_case(cs, did_something, count, max_depth-1);
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int size = 0;
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for (auto cmp : cs->compare)
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bool is_parallel_case = sw->get_bool_attribute(ID::parallel_case);
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bool is_full_case = sw->get_bool_attribute(ID::full_case);
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// Empty case removal. The rules are:
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//
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// - for full_case: only remove cases if *all* cases are empty
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// - for parallel_case but not full_case: remove any empty case
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// - for non-parallel and non-full case: remove the final case if it's empty
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if (is_full_case)
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{
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bool all_empty = true;
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for (auto cs : sw->cases)
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if (!cs->empty())
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all_empty = false;
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if (all_empty)
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{
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size += cmp.size();
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if (!cmp.is_fully_def())
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all_fully_def = false;
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for (auto cs : sw->cases)
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delete cs;
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sw->cases.clear();
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}
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if (sw->signal.size() != size)
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all_fully_def = false;
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}
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if (all_fully_def)
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else if (is_parallel_case)
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{
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for (auto cs = sw->cases.begin(); cs != sw->cases.end();)
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{
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