mirror of https://github.com/YosysHQ/yosys.git
memory_dff: Recognize soft transparency logic.
This commit is contained in:
Marcelina Kościelnicka
parent
616ace2d92
commit
9fdedf4d1c
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@ -19,7 +19,9 @@
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/modtools.h"
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#include "kernel/ffinit.h"
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#include "kernel/qcsat.h"
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#include "kernel/mem.h"
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#include "kernel/ff.h"
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#include "kernel/ffmerge.h"
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@ -27,27 +29,317 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct MuxData {
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int base_idx;
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int size;
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bool is_b;
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SigSpec sig_s;
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std::vector<SigSpec> sig_other;
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};
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struct PortData {
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bool relevant;
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std::vector<bool> uncollidable_mask;
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std::vector<bool> transparency_mask;
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std::vector<bool> collision_x_mask;
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bool final_transparency;
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bool final_collision_x;
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};
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// A helper with some caching for transparency-related SAT queries.
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// Bound to a single memory read port in the process of being converted
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// from async to sync..
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struct MemQueryCache
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{
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QuickConeSat &qcsat;
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// The memory.
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Mem &mem;
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// The port, still async at this point.
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MemRd &port;
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// The virtual FF that will end up merged into this port.
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FfData &ff;
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// An ezSAT variable that is true when we actually care about the data
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// read from memory (ie. the FF has enable on and is not in reset).
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int port_ren;
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// Some caches.
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dict<std::pair<int, SigBit>, bool> cache_can_collide_rdwr;
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dict<std::tuple<int, int, SigBit, SigBit>, bool> cache_can_collide_together;
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dict<std::tuple<int, SigBit, SigBit, bool>, bool> cache_is_w2rbyp;
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dict<std::tuple<SigBit, bool>, bool> cache_impossible_with_ren;
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MemQueryCache(QuickConeSat &qcsat, Mem &mem, MemRd &port, FfData &ff) : qcsat(qcsat), mem(mem), port(port), ff(ff) {
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// port_ren is an upper bound on when we care about the value fetched
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// from memory this cycle.
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int ren = ezSAT::CONST_TRUE;
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if (ff.has_en) {
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ren = qcsat.importSigBit(ff.sig_en);
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if (!ff.pol_en)
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ren = qcsat.ez->NOT(ren);
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}
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if (ff.has_srst) {
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int nrst = qcsat.importSigBit(ff.sig_srst);
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if (ff.pol_srst)
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nrst = qcsat.ez->NOT(nrst);
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ren = qcsat.ez->AND(ren, nrst);
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}
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port_ren = ren;
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}
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// Returns ezSAT variable that is true iff the two addresses are the same.
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int addr_eq(SigSpec raddr, SigSpec waddr) {
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int abits = std::max(GetSize(raddr), GetSize(waddr));
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raddr.extend_u0(abits);
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waddr.extend_u0(abits);
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return qcsat.ez->vec_eq(qcsat.importSig(raddr), qcsat.importSig(waddr));
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}
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// Returns true if a given write port bit can be active at the same time
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// as this read port and at the same address.
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bool can_collide_rdwr(int widx, SigBit wen) {
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std::pair<int, SigBit> key(widx, wen);
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auto it = cache_can_collide_rdwr.find(key);
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if (it != cache_can_collide_rdwr.end())
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return it->second;
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auto &wport = mem.wr_ports[widx];
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int aeq = addr_eq(port.addr, wport.addr);
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int wen_sat = qcsat.importSigBit(wen);
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qcsat.prepare();
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bool res = qcsat.ez->solve(aeq, wen_sat, port_ren);
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cache_can_collide_rdwr[key] = res;
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return res;
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}
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// Returns true if both given write port bits can be active at the same
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// time as this read port and at the same address (three-way collision).
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bool can_collide_together(int widx1, int widx2, int bitidx) {
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auto &wport1 = mem.wr_ports[widx1];
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auto &wport2 = mem.wr_ports[widx2];
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SigBit wen1 = wport1.en[bitidx];
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SigBit wen2 = wport2.en[bitidx];
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std::tuple<int, int, SigBit, SigBit> key(widx1, widx2, wen1, wen2);
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auto it = cache_can_collide_together.find(key);
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if (it != cache_can_collide_together.end())
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return it->second;
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int aeq1 = addr_eq(port.addr, wport1.addr);
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int aeq2 = addr_eq(port.addr, wport2.addr);
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int wen1_sat = qcsat.importSigBit(wen1);
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int wen2_sat = qcsat.importSigBit(wen2);
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qcsat.prepare();
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bool res = qcsat.ez->solve(wen1_sat, wen2_sat, aeq1, aeq2, port_ren);
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cache_can_collide_together[key] = res;
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return res;
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}
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// Returns true if the given mux selection signal is a valid data-bypass
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// signal in soft transparency logic for a given write port bit.
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bool is_w2rbyp(int widx, SigBit wen, SigBit sel, bool neg_sel) {
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std::tuple<int, SigBit, SigBit, bool> key(widx, wen, sel, neg_sel);
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auto it = cache_is_w2rbyp.find(key);
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if (it != cache_is_w2rbyp.end())
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return it->second;
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auto &wport = mem.wr_ports[widx];
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int aeq = addr_eq(port.addr, wport.addr);
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int wen_sat = qcsat.importSigBit(wen);
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int sel_expected = qcsat.ez->AND(aeq, wen_sat);
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int sel_sat = qcsat.importSigBit(sel);
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if (neg_sel)
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sel_sat = qcsat.ez->NOT(sel_sat);
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qcsat.prepare();
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bool res = !qcsat.ez->solve(port_ren, qcsat.ez->XOR(sel_expected, sel_sat));
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cache_is_w2rbyp[key] = res;
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return res;
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}
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// Returns true if the given mux selection signal can never be true
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// when this port is active.
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bool impossible_with_ren(SigBit sel, bool neg_sel) {
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std::tuple<SigBit, bool> key(sel, neg_sel);
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auto it = cache_impossible_with_ren.find(key);
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if (it != cache_impossible_with_ren.end())
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return it->second;
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int sel_sat = qcsat.importSigBit(sel);
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if (neg_sel)
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sel_sat = qcsat.ez->NOT(sel_sat);
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qcsat.prepare();
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bool res = !qcsat.ez->solve(port_ren, sel_sat);
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cache_impossible_with_ren[key] = res;
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return res;
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}
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// Helper for data_eq: walks up a multiplexer when the value of its
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// sel signal is constant under the assumption that this read port
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// is active and a given other mux sel signal is true.
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bool walk_up_mux_cond(SigBit sel, bool neg_sel, SigBit &bit) {
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auto &drivers = qcsat.modwalker.signal_drivers[qcsat.modwalker.sigmap(bit)];
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if (GetSize(drivers) != 1)
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return false;
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auto driver = *drivers.begin();
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if (!driver.cell->type.in(ID($mux), ID($pmux)))
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return false;
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log_assert(driver.port == ID::Y);
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SigSpec sig_s = driver.cell->getPort(ID::S);
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int sel_sat = qcsat.importSigBit(sel);
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if (neg_sel)
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sel_sat = qcsat.ez->NOT(sel_sat);
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bool all_0 = true;
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int width = driver.cell->parameters.at(ID::WIDTH).as_int();
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for (int i = 0; i < GetSize(sig_s); i++) {
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int sbit = qcsat.importSigBit(sig_s[i]);
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qcsat.prepare();
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if (!qcsat.ez->solve(port_ren, sel_sat, qcsat.ez->NOT(sbit))) {
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bit = driver.cell->getPort(ID::B)[i * width + driver.offset];
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return true;
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}
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if (qcsat.ez->solve(port_ren, sel_sat, sbit))
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all_0 = false;
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}
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if (all_0) {
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bit = driver.cell->getPort(ID::A)[driver.offset];
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return true;
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}
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return false;
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}
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// Returns true if a given data signal is equivalent to another, under
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// the assumption that this read port is active and a given mux sel signal
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// is true. Used to match transparency logic data with write port data.
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// The walk_up_mux_cond part is necessary because write ports in yosys
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// tend to be connected to things like (wen ? wdata : 'x).
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bool data_eq(SigBit sel, bool neg_sel, SigBit dbit, SigBit odbit) {
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if (qcsat.modwalker.sigmap(dbit) == qcsat.modwalker.sigmap(odbit))
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return true;
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while (walk_up_mux_cond(sel, neg_sel, dbit));
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while (walk_up_mux_cond(sel, neg_sel, odbit));
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return qcsat.modwalker.sigmap(dbit) == qcsat.modwalker.sigmap(odbit);
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}
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};
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struct MemoryDffWorker
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{
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Module *module;
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SigMap sigmap;
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ModWalker modwalker;
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FfInitVals initvals;
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FfMergeHelper merger;
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MemoryDffWorker(Module *module) : module(module), sigmap(module)
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MemoryDffWorker(Module *module) : module(module), modwalker(module->design)
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{
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initvals.set(&sigmap, module);
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modwalker.setup(module);
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initvals.set(&modwalker.sigmap, module);
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merger.set(&initvals, module);
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}
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void handle_rd_port(Mem &mem, int idx)
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// Starting from the output of an async read port, as long as the data
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// signal's only user is a mux data signal, passes through the mux
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// and remembers information about it. Conceptually works on every
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// bit separately, but coalesces the result when possible.
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SigSpec walk_muxes(SigSpec data, std::vector<MuxData> &res) {
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bool did_something;
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do {
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did_something = false;
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int prev_idx = -1;
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Cell *prev_cell = nullptr;
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bool prev_is_b = false;
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for (int i = 0; i < GetSize(data); i++) {
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SigBit bit = modwalker.sigmap(data[i]);
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auto &consumers = modwalker.signal_consumers[bit];
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if (GetSize(consumers) != 1 || modwalker.signal_outputs.count(bit))
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continue;
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auto consumer = *consumers.begin();
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bool is_b;
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if (consumer.cell->type == ID($mux)) {
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if (consumer.port == ID::A) {
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is_b = false;
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} else if (consumer.port == ID::B) {
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is_b = true;
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} else {
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continue;
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}
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} else if (consumer.cell->type == ID($pmux)) {
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if (consumer.port == ID::A) {
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is_b = false;
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} else {
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continue;
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}
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} else {
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continue;
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}
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SigSpec y = consumer.cell->getPort(ID::Y);
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int mux_width = GetSize(y);
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SigBit ybit = y.extract(consumer.offset);
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if (prev_cell != consumer.cell || prev_idx+1 != i || prev_is_b != is_b) {
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MuxData md;
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md.base_idx = i;
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md.size = 0;
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md.is_b = is_b;
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md.sig_s = consumer.cell->getPort(ID::S);
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md.sig_other.resize(GetSize(md.sig_s));
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prev_cell = consumer.cell;
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prev_is_b = is_b;
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res.push_back(md);
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}
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auto &md = res.back();
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md.size++;
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for (int j = 0; j < GetSize(md.sig_s); j++) {
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SigBit obit = consumer.cell->getPort(is_b ? ID::A : ID::B).extract(j * mux_width + consumer.offset);
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md.sig_other[j].append(obit);
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}
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prev_idx = i;
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data[i] = ybit;
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did_something = true;
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}
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} while (did_something);
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return data;
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}
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// Merges FF and possibly soft transparency logic into an asynchronous
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// read port, making it into a synchronous one.
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//
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// There are three moving parts involved here:
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//
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// - the async port, which we start from, whose data port is input to...
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// - an arbitrary chain of $mux and $pmux cells implementing soft transparency
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// logic (ie. bypassing write port's data iff the write port is active and
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// writing to the same address as this read port), which in turn feeds...
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// - a final FF
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//
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// The async port and the mux chain are not allowed to have any users that
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// are not part of the above.
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//
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// The algorithm is:
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//
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// 1. Walk through the muxes.
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// 2. Recognize the final FF.
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// 3. Knowing the FF's clock and read enable, make a list of write ports
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// that we'll run transparency analysis on.
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// 4. For every mux bit, recognize it as one of:
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// - a transparency bypass mux for some port
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// - a bypass mux that feeds 'x instead (this will result in collision
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// don't care behavior being recognized)
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// - a mux that never selects the other value when read port is active,
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// and can thus be skipped (this is necessary because this could
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// be a transparency bypass mux for never-colliding port that other
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// passes failed to optimize)
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// - a mux whose other input is 'x, and can thus be skipped
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// 5. When recognizing transparency bypasses, take care to preserve priority
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// behavior — when two bypasses are sequential muxes on the chain, they
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// effectively have priority over one another, and the transform can
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// only be performed when either a) their corresponding write ports
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// also have priority, or b) there can never be a three-way collision
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// between the two write ports and the read port.
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// 6. Check consistency of per-bit transparency masks, merge them into
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// per-port transparency masks
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// 7. If everything went fine in the previous steps, actually perform
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// the merge.
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void handle_rd_port(Mem &mem, QuickConeSat &qcsat, int idx)
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{
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auto &port = mem.rd_ports[idx];
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log("Checking read port `%s'[%d] in module `%s': ", mem.memid.c_str(), idx, module->name.c_str());
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std::vector<MuxData> muxdata;
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SigSpec data = walk_muxes(port.data, muxdata);
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FfData ff;
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pool<std::pair<Cell *, int>> bits;
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if (!merger.find_output_ff(port.data, ff, bits)) {
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if (!merger.find_output_ff(data, ff, bits)) {
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log("no output FF found.\n");
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return;
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}
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@ -60,6 +352,144 @@ struct MemoryDffWorker
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log("output FF has both set and reset, not supported.\n");
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return;
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}
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// Construct cache.
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MemQueryCache cache(qcsat, mem, port, ff);
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// Prepare information structure about all ports, recognize port bits
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// that can never collide at all and don't need to be checked.
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std::vector<PortData> portdata;
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for (int i = 0; i < GetSize(mem.wr_ports); i++) {
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PortData pd;
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auto &wport = mem.wr_ports[i];
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pd.relevant = true;
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if (!wport.clk_enable)
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pd.relevant = false;
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if (wport.clk != ff.sig_clk)
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pd.relevant = false;
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if (wport.clk_polarity != ff.pol_clk)
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pd.relevant = false;
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// In theory, we *could* support mismatched width
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// ports here. However, it's not worth it — wide
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// ports are recognized *after* memory_dff in
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// a normal flow.
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if (wport.wide_log2 != port.wide_log2)
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pd.relevant = false;
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pd.uncollidable_mask.resize(GetSize(port.data));
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pd.transparency_mask.resize(GetSize(port.data));
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pd.collision_x_mask.resize(GetSize(port.data));
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if (pd.relevant) {
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// If we got this far, this port is potentially
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// transparent and/or has undefined collision
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// behavior. Now, for every bit, check if it can
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// ever collide.
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for (int j = 0; j < ff.width; j++) {
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if (!cache.can_collide_rdwr(i, wport.en[j])) {
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pd.uncollidable_mask[j] = true;
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pd.collision_x_mask[j] = true;
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}
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}
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}
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portdata.push_back(pd);
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}
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// Now inspect the mux chain.
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for (auto &md : muxdata) {
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// We only mark transparent bits after processing a complete
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// mux, so that the transparency priority validation check
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// below sees transparency information as of previous mux.
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std::vector<std::pair<PortData&, int>> trans_queue;
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for (int sel_idx = 0; sel_idx < GetSize(md.sig_s); sel_idx++) {
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SigBit sbit = md.sig_s[sel_idx];
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SigSpec &odata = md.sig_other[sel_idx];
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for (int bitidx = md.base_idx; bitidx < md.base_idx+md.size; bitidx++) {
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SigBit odbit = odata[bitidx-md.base_idx];
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bool recognized = false;
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for (int pi = 0; pi < GetSize(mem.wr_ports); pi++) {
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auto &pd = portdata[pi];
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auto &wport = mem.wr_ports[pi];
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if (!pd.relevant)
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continue;
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if (pd.uncollidable_mask[bitidx])
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continue;
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bool match = cache.is_w2rbyp(pi, wport.en[bitidx], sbit, md.is_b);
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if (!match)
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continue;
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// If we got here, we recognized this mux sel
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// as valid bypass sel for a given port bit.
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if (odbit == State::Sx) {
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// 'x, mark collision don't care.
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pd.collision_x_mask[bitidx] = true;
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pd.transparency_mask[bitidx] = false;
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} else if (cache.data_eq(sbit, md.is_b, wport.data[bitidx], odbit)) {
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// Correct data value, mark transparency,
|
||||
// but only after verifying that priority
|
||||
// is fine.
|
||||
for (int k = 0; k < GetSize(mem.wr_ports); k++) {
|
||||
if (portdata[k].transparency_mask[bitidx]) {
|
||||
if (wport.priority_mask[k])
|
||||
continue;
|
||||
if (!cache.can_collide_together(pi, k, bitidx))
|
||||
continue;
|
||||
log("FF found, but transparency logic priority doesn't match write priority.\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
recognized = true;
|
||||
trans_queue.push_back({pd, bitidx});
|
||||
break;
|
||||
} else {
|
||||
log("FF found, but with a mux data input that doesn't seem to correspond to transparency logic.\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
if (!recognized) {
|
||||
// If we haven't positively identified this as
|
||||
// a bypass: it's still skippable if the
|
||||
// data is 'x, or if the sel cannot actually be
|
||||
// active.
|
||||
if (odbit == State::Sx)
|
||||
continue;
|
||||
if (cache.impossible_with_ren(sbit, md.is_b))
|
||||
continue;
|
||||
log("FF found, but with a mux select that doesn't seem to correspond to transparency logic.\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
// Done with this mux, now actually apply the transparencies.
|
||||
for (auto it : trans_queue) {
|
||||
it.first.transparency_mask[it.second] = true;
|
||||
it.first.collision_x_mask[it.second] = false;
|
||||
}
|
||||
}
|
||||
|
||||
// Final merging and validation of per-bit masks.
|
||||
for (int pi = 0; pi < GetSize(mem.wr_ports); pi++) {
|
||||
auto &pd = portdata[pi];
|
||||
if (!pd.relevant)
|
||||
continue;
|
||||
bool trans = false;
|
||||
bool non_trans = false;
|
||||
for (int i = 0; i < ff.width; i++) {
|
||||
if (pd.collision_x_mask[i])
|
||||
continue;
|
||||
if (pd.transparency_mask[i])
|
||||
trans = true;
|
||||
else
|
||||
non_trans = true;
|
||||
}
|
||||
if (trans && non_trans) {
|
||||
log("FF found, but soft transparency logic is inconsistent for port %d.\n", pi);
|
||||
return;
|
||||
}
|
||||
pd.final_transparency = trans;
|
||||
pd.final_collision_x = !trans && !non_trans;
|
||||
}
|
||||
|
||||
// OK, it worked.
|
||||
log("merging output FF to cell.\n");
|
||||
|
||||
merger.remove_output_ff(bits);
|
||||
if (ff.has_en && !ff.pol_en)
|
||||
ff.sig_en = module->LogicNot(NEW_ID, ff.sig_en);
|
||||
|
|
@ -89,8 +519,21 @@ struct MemoryDffWorker
|
|||
}
|
||||
port.init_value = ff.val_init;
|
||||
port.data = ff.sig_q;
|
||||
for (int pi = 0; pi < GetSize(mem.wr_ports); pi++) {
|
||||
auto &pd = portdata[pi];
|
||||
if (!pd.relevant)
|
||||
continue;
|
||||
if (pd.final_collision_x) {
|
||||
log(" Write port %d: don't care on collision.\n", pi);
|
||||
port.collision_x_mask[pi] = true;
|
||||
} else if (pd.final_transparency) {
|
||||
log(" Write port %d: transparent.\n", pi);
|
||||
port.transparency_mask[pi] = true;
|
||||
} else {
|
||||
log(" Write port %d: non-transparent.\n", pi);
|
||||
}
|
||||
}
|
||||
mem.emit();
|
||||
log("merged output FF to cell.\n");
|
||||
}
|
||||
|
||||
void handle_rd_port_addr(Mem &mem, int idx)
|
||||
|
|
@ -146,9 +589,10 @@ struct MemoryDffWorker
|
|||
{
|
||||
std::vector<Mem> memories = Mem::get_selected_memories(module);
|
||||
for (auto &mem : memories) {
|
||||
QuickConeSat qcsat(modwalker);
|
||||
for (int i = 0; i < GetSize(mem.rd_ports); i++) {
|
||||
if (!mem.rd_ports[i].clk_enable)
|
||||
handle_rd_port(mem, i);
|
||||
handle_rd_port(mem, qcsat, i);
|
||||
}
|
||||
}
|
||||
for (auto &mem : memories) {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,21 @@
|
|||
// expect-wr-ports 1
|
||||
// expect-rd-ports 1
|
||||
// expect-rd-clk \clk
|
||||
// expect-rd-en \re
|
||||
|
||||
module top(input clk, we, re, input [7:0] ra, wa, wd, output reg [7:0] rd);
|
||||
|
||||
reg [7:0] mem[0:255];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (we)
|
||||
mem[wa] <= wd;
|
||||
|
||||
if (re) begin
|
||||
rd <= mem[ra];
|
||||
if (we && ra == wa)
|
||||
rd <= wd;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
// expect-wr-ports 1
|
||||
// expect-rd-ports 1
|
||||
// expect-rd-clk \clk
|
||||
// expect-rd-en \re
|
||||
|
||||
module top(input clk, we, re, input [7:0] addr, wd, output reg [7:0] rd);
|
||||
|
||||
reg [7:0] mem[0:255];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (we)
|
||||
mem[addr] <= wd;
|
||||
|
||||
if (re) begin
|
||||
rd <= mem[addr];
|
||||
if (we)
|
||||
rd <= wd;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,862 @@
|
|||
# Good case 1: single port.
|
||||
|
||||
read_verilog << EOT
|
||||
|
||||
module top(
|
||||
input [3:0] addr,
|
||||
input [3:0] wd,
|
||||
input we,
|
||||
input clk,
|
||||
output reg [3:0] rd,
|
||||
);
|
||||
|
||||
reg [3:0] mem[0:15];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (we) begin
|
||||
mem[addr] <= wd;
|
||||
rd <= wd;
|
||||
end else begin
|
||||
rd <= mem[addr];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
opt_dff
|
||||
opt_clean
|
||||
memory_dff
|
||||
memory_collect
|
||||
select -assert-count 1 t:$mem_v2
|
||||
select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=1'b1 r:RD_COLLISION_X_MASK=1'b0 %i %i
|
||||
|
||||
design -reset
|
||||
|
||||
# Good case 2: single port, exclusive.
|
||||
|
||||
read_verilog << EOT
|
||||
|
||||
module top(
|
||||
input [3:0] addr,
|
||||
input [3:0] wd,
|
||||
input we,
|
||||
input clk,
|
||||
output reg [3:0] rd,
|
||||
);
|
||||
|
||||
reg [3:0] mem[0:15];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (we) begin
|
||||
mem[addr] <= wd;
|
||||
end else begin
|
||||
rd <= mem[addr];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
opt_dff
|
||||
opt_clean
|
||||
memory_dff
|
||||
memory_collect
|
||||
select -assert-count 1 t:$mem_v2
|
||||
select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=1'b0 r:RD_COLLISION_X_MASK=1'b1 %i %i
|
||||
|
||||
design -reset
|
||||
|
||||
# Good case 3: proper bypass muxes.
|
||||
|
||||
read_verilog << EOT
|
||||
|
||||
module top(
|
||||
input [3:0] ra,
|
||||
input [3:0] wa1,
|
||||
input [3:0] wa2,
|
||||
input [3:0] wd1,
|
||||
input [3:0] wd2,
|
||||
input we1, we2,
|
||||
input re,
|
||||
input clk,
|
||||
output reg [3:0] rd,
|
||||
);
|
||||
|
||||
reg [3:0] mem[0:15];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (we1)
|
||||
mem[wa1] <= wd1;
|
||||
if (we2)
|
||||
mem[wa2] <= wd2;
|
||||
if (re) begin
|
||||
rd <= mem[ra];
|
||||
if (we1 && wa1 == ra)
|
||||
rd <= wd1;
|
||||
if (we2 && wa2 == ra)
|
||||
rd <= wd2;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
opt_dff
|
||||
opt_clean
|
||||
memory_dff
|
||||
memory_collect
|
||||
select -assert-count 1 t:$mem_v2
|
||||
select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=2'b11 r:RD_COLLISION_X_MASK=2'b00 %i %i
|
||||
|
||||
design -reset
|
||||
|
||||
# Good case 4: proper bypass mux, but only one.
|
||||
|
||||
read_verilog << EOT
|
||||
|
||||
module top(
|
||||
input [3:0] ra,
|
||||
input [3:0] wa1,
|
||||
input [3:0] wa2,
|
||||
input [3:0] wd1,
|
||||
input [3:0] wd2,
|
||||
input we1, we2,
|
||||
input re,
|
||||
input clk,
|
||||
output reg [3:0] rd,
|
||||
);
|
||||
|
||||
reg [3:0] mem[0:15];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (we1)
|
||||
mem[wa1] <= wd1;
|
||||
if (we2)
|
||||
mem[wa2] <= wd2;
|
||||
if (re) begin
|
||||
rd <= mem[ra];
|
||||
if (we1 && wa1 == ra)
|
||||
rd <= wd1;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
opt_dff
|
||||
opt_clean
|
||||
memory_dff
|
||||
memory_collect
|
||||
select -assert-count 1 t:$mem_v2
|
||||
select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=2'b01 r:RD_COLLISION_X_MASK=2'b00 %i %i
|
||||
|
||||
design -reset
|
||||
|
||||
# Good case 5: proper bypass mux, but the other one.
|
||||
|
||||
read_verilog << EOT
|
||||
|
||||
module top(
|
||||
input [3:0] ra,
|
||||
input [3:0] wa1,
|
||||
input [3:0] wa2,
|
||||
input [3:0] wd1,
|
||||
input [3:0] wd2,
|
||||
input we1, we2,
|
||||
input re,
|
||||
input clk,
|
||||
output reg [3:0] rd,
|
||||
);
|
||||
|
||||
reg [3:0] mem[0:15];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (we1)
|
||||
mem[wa1] <= wd1;
|
||||
if (we2)
|
||||
mem[wa2] <= wd2;
|
||||
if (re) begin
|
||||
rd <= mem[ra];
|
||||
if (we2 && wa2 == ra)
|
||||
rd <= wd2;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
opt_dff
|
||||
opt_clean
|
||||
memory_dff
|
||||
memory_collect
|
||||
select -assert-count 1 t:$mem_v2
|
||||
select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=2'b10 r:RD_COLLISION_X_MASK=2'b00 %i %i
|
||||
|
||||
design -reset
|
||||
|
||||
# Good case 6: 'x mux.
|
||||
|
||||
read_verilog << EOT
|
||||
|
||||
module top(
|
||||
input [3:0] ra,
|
||||
input [3:0] wa1,
|
||||
input [3:0] wa2,
|
||||
input [3:0] wd1,
|
||||
input [3:0] wd2,
|
||||
input we1, we2,
|
||||
input re,
|
||||
input clk,
|
||||
output reg [3:0] rd,
|
||||
);
|
||||
|
||||
reg [3:0] mem[0:15];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (we1)
|
||||
mem[wa1] <= wd1;
|
||||
if (we2)
|
||||
mem[wa2] <= wd2;
|
||||
if (re) begin
|
||||
rd <= mem[ra];
|
||||
if (we1 && wa1 == ra)
|
||||
rd <= 4'hx;
|
||||
if (we2 && wa2 == ra)
|
||||
rd <= wd2;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
opt_dff
|
||||
opt_clean
|
||||
memory_dff
|
||||
memory_collect
|
||||
select -assert-count 1 t:$mem_v2
|
||||
select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=2'b10 r:RD_COLLISION_X_MASK=2'b01 %i %i
|
||||
|
||||
design -reset
|
||||
|
||||
# Good case 7: uncollidable addresses.
|
||||
|
||||
read_verilog << EOT
|
||||
|
||||
module top(
|
||||
input [3:0] addr,
|
||||
input [3:0] wd1,
|
||||
input [3:0] wd2,
|
||||
input we1, we2,
|
||||
input re,
|
||||
input clk,
|
||||
output reg [3:0] rd,
|
||||
);
|
||||
|
||||
reg [3:0] mem[0:15];
|
||||
|
||||
wire [3:0] wa1 = addr;
|
||||
wire [3:0] wa2 = addr + 1;
|
||||
wire [3:0] ra = addr + 2;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (we1)
|
||||
mem[wa1] <= wd1;
|
||||
if (we2)
|
||||
mem[wa2] <= wd2;
|
||||
if (re) begin
|
||||
rd <= mem[ra];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
opt_dff
|
||||
opt_clean
|
||||
memory_dff
|
||||
memory_collect
|
||||
select -assert-count 1 t:$mem_v2
|
||||
select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=2'b00 r:RD_COLLISION_X_MASK=2'b11 %i %i
|
||||
|
||||
design -reset
|
||||
|
||||
# Good case 8: uncollidable addresses, but still have soft transparency logic.
|
||||
|
||||
read_verilog << EOT
|
||||
|
||||
module top(
|
||||
input [3:0] addr,
|
||||
input [3:0] wd1,
|
||||
input [3:0] wd2,
|
||||
input we1, we2,
|
||||
input re,
|
||||
input clk,
|
||||
output reg [3:0] rd,
|
||||
);
|
||||
|
||||
reg [3:0] mem[0:15];
|
||||
|
||||
wire [3:0] wa1 = addr;
|
||||
wire [3:0] wa2 = addr + 1;
|
||||
wire [3:0] ra = addr + 2;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (we1)
|
||||
mem[wa1] <= wd1;
|
||||
if (we2)
|
||||
mem[wa2] <= wd2;
|
||||
if (re) begin
|
||||
rd <= mem[ra];
|
||||
if (we1 && wa1 == ra)
|
||||
rd <= wd1;
|
||||
if (we2 && wa2 == ra)
|
||||
rd <= wd2;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
opt_dff
|
||||
opt_clean
|
||||
memory_dff
|
||||
memory_collect
|
||||
select -assert-count 1 t:$mem_v2
|
||||
select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=2'b00 r:RD_COLLISION_X_MASK=2'b11 %i %i
|
||||
|
||||
design -reset
|
||||
|
||||
# Bad case 1: broken bypass signal.
|
||||
|
||||
read_verilog << EOT
|
||||
|
||||
module top(
|
||||
input [3:0] ra,
|
||||
input [3:0] wa1,
|
||||
input [3:0] wa2,
|
||||
input [3:0] wd1,
|
||||
input [3:0] wd2,
|
||||
input we1, we2,
|
||||
input re,
|
||||
input clk,
|
||||
output reg [3:0] rd,
|
||||
);
|
||||
|
||||
reg [3:0] mem[0:15];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (we1)
|
||||
mem[wa1] <= wd1;
|
||||
if (we2)
|
||||
mem[wa2] <= wd2;
|
||||
if (re) begin
|
||||
rd <= mem[ra];
|
||||
if (we1 && wa1 == ra)
|
||||
rd <= wd1;
|
||||
if (we2 && wa2 == ra && we1)
|
||||
rd <= wd2;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
opt_dff
|
||||
opt_clean
|
||||
logger -expect log "FF found, but with a mux select that doesn't seem to correspond to transparency logic" 1
|
||||
memory_dff
|
||||
logger -check-expected
|
||||
memory_collect
|
||||
select -assert-count 1 t:$mem_v2
|
||||
select -assert-count 1 t:$mem_v2 r:RD_CLK_ENABLE=1'b0 %i
|
||||
|
||||
design -reset
|
||||
|
||||
# Bad case 2: bad data signal.
|
||||
|
||||
read_verilog << EOT
|
||||
|
||||
module top(
|
||||
input [3:0] ra,
|
||||
input [3:0] wa1,
|
||||
input [3:0] wa2,
|
||||
input [3:0] wd1,
|
||||
input [3:0] wd2,
|
||||
input we1, we2,
|
||||
input re,
|
||||
input clk,
|
||||
output reg [3:0] rd,
|
||||
);
|
||||
|
||||
reg [3:0] mem[0:15];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (we1)
|
||||
mem[wa1] <= wd1;
|
||||
if (we2)
|
||||
mem[wa2] <= wd2;
|
||||
if (re) begin
|
||||
rd <= mem[ra];
|
||||
if (we1 && wa1 == ra)
|
||||
rd <= wd1;
|
||||
if (we2 && wa2 == ra)
|
||||
rd <= wd1;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
opt_dff
|
||||
opt_clean
|
||||
logger -expect log "FF found, but with a mux data input that doesn't seem to correspond to transparency logic" 1
|
||||
memory_dff
|
||||
logger -check-expected
|
||||
memory_collect
|
||||
select -assert-count 1 t:$mem_v2
|
||||
select -assert-count 1 t:$mem_v2 r:RD_CLK_ENABLE=1'b0 %i
|
||||
|
||||
design -reset
|
||||
|
||||
# Bad case 3: priority mismatch.
|
||||
|
||||
read_verilog << EOT
|
||||
|
||||
module top(
|
||||
input [3:0] ra,
|
||||
input [3:0] wa1,
|
||||
input [3:0] wa2,
|
||||
input [3:0] wd1,
|
||||
input [3:0] wd2,
|
||||
input we1, we2,
|
||||
input re,
|
||||
input clk,
|
||||
output reg [3:0] rd,
|
||||
);
|
||||
|
||||
reg [3:0] mem[0:15];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (we1)
|
||||
mem[wa1] <= wd1;
|
||||
if (we2)
|
||||
mem[wa2] <= wd2;
|
||||
if (re) begin
|
||||
rd <= mem[ra];
|
||||
if (we2 && wa2 == ra)
|
||||
rd <= wd2;
|
||||
if (we1 && wa1 == ra)
|
||||
rd <= wd1;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
opt_dff
|
||||
opt_clean
|
||||
logger -expect log "FF found, but transparency logic priority doesn't match write priority." 1
|
||||
memory_dff
|
||||
logger -check-expected
|
||||
memory_collect
|
||||
select -assert-count 1 t:$mem_v2
|
||||
select -assert-count 1 t:$mem_v2 r:RD_CLK_ENABLE=1'b0 %i
|
||||
|
||||
design -reset
|
||||
|
||||
# Good case 10: priority mismatch, but since the second value is 'x, it's still OK.
|
||||
|
||||
read_verilog << EOT
|
||||
|
||||
module top(
|
||||
input [3:0] ra,
|
||||
input [3:0] wa1,
|
||||
input [3:0] wa2,
|
||||
input [3:0] wd1,
|
||||
input [3:0] wd2,
|
||||
input we1, we2,
|
||||
input re,
|
||||
input clk,
|
||||
output reg [3:0] rd,
|
||||
);
|
||||
|
||||
reg [3:0] mem[0:15];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (we1)
|
||||
mem[wa1] <= wd1;
|
||||
if (we2)
|
||||
mem[wa2] <= wd2;
|
||||
if (re) begin
|
||||
rd <= mem[ra];
|
||||
if (we2 && wa2 == ra)
|
||||
rd <= wd2;
|
||||
if (we1 && wa1 == ra)
|
||||
rd <= 4'hx;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
opt_dff
|
||||
opt_clean
|
||||
memory_dff
|
||||
memory_collect
|
||||
select -assert-count 1 t:$mem_v2
|
||||
select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=2'b10 r:RD_COLLISION_X_MASK=2'b01 %i %i
|
||||
|
||||
design -reset
|
||||
|
||||
# Good case 11: priority mismatch, but since three-way collision cannot happen, it's still OK.
|
||||
|
||||
read_verilog << EOT
|
||||
|
||||
module top(
|
||||
input [3:0] addr,
|
||||
input [1:0] mode,
|
||||
input [3:0] wd1,
|
||||
input [3:0] wd2,
|
||||
input we1, we2,
|
||||
input re,
|
||||
input clk,
|
||||
output reg [3:0] rd,
|
||||
);
|
||||
|
||||
reg [3:0] wa1, wa2, ra;
|
||||
|
||||
always @* begin
|
||||
case (mode)
|
||||
0: begin
|
||||
wa1 = addr+1;
|
||||
wa2 = addr;
|
||||
ra = addr;
|
||||
end
|
||||
1: begin
|
||||
wa1 = addr;
|
||||
wa2 = addr+1;
|
||||
ra = addr;
|
||||
end
|
||||
2: begin
|
||||
wa1 = addr;
|
||||
wa2 = addr;
|
||||
ra = addr+1;
|
||||
end
|
||||
3: begin
|
||||
wa1 = addr;
|
||||
wa2 = addr+1;
|
||||
ra = addr+2;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
reg [3:0] mem[0:15];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (we1)
|
||||
mem[wa1] <= wd1;
|
||||
if (we2)
|
||||
mem[wa2] <= wd2;
|
||||
if (re) begin
|
||||
rd <= mem[ra];
|
||||
if (we2 && wa2 == ra)
|
||||
rd <= wd2;
|
||||
if (we1 && wa1 == ra)
|
||||
rd <= wd1;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
opt_dff
|
||||
opt_clean
|
||||
memory_dff
|
||||
memory_collect
|
||||
select -assert-count 1 t:$mem_v2
|
||||
select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=2'b11 r:RD_COLLISION_X_MASK=2'b00 %i %i
|
||||
|
||||
design -reset
|
||||
|
||||
# Bad case 4: half of the port is transparent.
|
||||
|
||||
read_verilog << EOT
|
||||
|
||||
module top(
|
||||
input [3:0] ra,
|
||||
input [3:0] wa1,
|
||||
input [3:0] wa2,
|
||||
input [3:0] wd1,
|
||||
input [3:0] wd2,
|
||||
input we1, we2,
|
||||
input re,
|
||||
input clk,
|
||||
output reg [3:0] rd,
|
||||
);
|
||||
|
||||
reg [3:0] mem[0:15];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (we1)
|
||||
mem[wa1] <= wd1;
|
||||
if (we2)
|
||||
mem[wa2] <= wd2;
|
||||
if (re) begin
|
||||
rd <= mem[ra];
|
||||
if (we1 && wa1 == ra)
|
||||
rd <= wd1;
|
||||
if (we2 && wa2 == ra)
|
||||
rd[3:2] <= wd2[3:2];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
opt_dff
|
||||
opt_clean
|
||||
logger -expect log "FF found, but soft transparency logic is inconsistent for port 1." 1
|
||||
memory_dff
|
||||
logger -check-expected
|
||||
memory_collect
|
||||
select -assert-count 1 t:$mem_v2
|
||||
select -assert-count 1 t:$mem_v2 r:RD_CLK_ENABLE=1'b0 %i
|
||||
|
||||
design -reset
|
||||
|
||||
# Good case 12: like above, but the other bits aren't changed by the port anyway.
|
||||
|
||||
read_verilog << EOT
|
||||
|
||||
module top(
|
||||
input [3:0] ra,
|
||||
input [3:0] wa1,
|
||||
input [3:0] wa2,
|
||||
input [3:0] wd1,
|
||||
input [3:0] wd2,
|
||||
input we1, we2,
|
||||
input re,
|
||||
input clk,
|
||||
output reg [3:0] rd,
|
||||
);
|
||||
|
||||
reg [3:0] mem[0:15];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (we1)
|
||||
mem[wa1] <= wd1;
|
||||
if (we2)
|
||||
mem[wa2][3:2] <= wd2[3:2];
|
||||
if (re) begin
|
||||
rd <= mem[ra];
|
||||
if (we1 && wa1 == ra)
|
||||
rd <= wd1;
|
||||
if (we2 && wa2 == ra)
|
||||
rd[3:2] <= wd2[3:2];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
opt_dff
|
||||
opt_clean
|
||||
memory_dff
|
||||
memory_collect
|
||||
select -assert-count 1 t:$mem_v2
|
||||
select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=2'b11 r:RD_COLLISION_X_MASK=2'b00 %i %i
|
||||
|
||||
design -reset
|
||||
|
||||
# Good case 13: wide read, narrow write.
|
||||
|
||||
read_verilog << EOT
|
||||
|
||||
module top(
|
||||
input [7:0] addr,
|
||||
input [7:0] wd,
|
||||
input we,
|
||||
input re,
|
||||
input clk,
|
||||
output reg [31:0] rd,
|
||||
);
|
||||
|
||||
reg [7:0] mem[0:255];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (we)
|
||||
mem[addr] <= wd;
|
||||
if (re) begin
|
||||
rd[7:0] <= mem[{addr[7:2], 2'b00}];
|
||||
rd[15:8] <= mem[{addr[7:2], 2'b01}];
|
||||
rd[23:16] <= mem[{addr[7:2], 2'b10}];
|
||||
rd[31:24] <= mem[{addr[7:2], 2'b11}];
|
||||
case ({we, addr[1:0]})
|
||||
3'b100: rd[7:0] <= wd;
|
||||
3'b101: rd[15:8] <= wd;
|
||||
3'b110: rd[23:16] <= wd;
|
||||
3'b111: rd[31:24] <= wd;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
opt_dff
|
||||
opt_clean
|
||||
dump
|
||||
memory_dff
|
||||
memory_collect
|
||||
select -assert-count 1 t:$mem_v2
|
||||
select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=4'b1111 r:RD_COLLISION_X_MASK=4'b0000 %i %i
|
||||
|
||||
design -reset
|
||||
|
||||
# Good case 14: narrow read, wide write.
|
||||
|
||||
read_verilog << EOT
|
||||
|
||||
module top(
|
||||
input [7:0] addr,
|
||||
input [31:0] wd,
|
||||
input we,
|
||||
input re,
|
||||
input clk,
|
||||
output reg [7:0] rd,
|
||||
);
|
||||
|
||||
reg [7:0] mem[0:255];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (we) begin
|
||||
mem[{addr[7:2], 2'b00}] <= wd[7:0];
|
||||
mem[{addr[7:2], 2'b01}] <= wd[15:8];
|
||||
mem[{addr[7:2], 2'b10}] <= wd[23:16];
|
||||
mem[{addr[7:2], 2'b11}] <= wd[31:24];
|
||||
end
|
||||
if (re) begin
|
||||
rd <= mem[addr];
|
||||
case ({we, addr[1:0]})
|
||||
3'b100: rd <= wd[7:0];
|
||||
3'b101: rd <= wd[15:8];
|
||||
3'b110: rd <= wd[23:16];
|
||||
3'b111: rd <= wd[31:24];
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
opt_dff
|
||||
opt_clean
|
||||
dump
|
||||
memory_dff
|
||||
memory_collect
|
||||
select -assert-count 1 t:$mem_v2
|
||||
select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=4'b1111 r:RD_COLLISION_X_MASK=4'b0000 %i %i
|
||||
|
||||
design -reset
|
||||
|
||||
# Good case 15: wide read, wide write.
|
||||
|
||||
read_verilog << EOT
|
||||
|
||||
module top(
|
||||
input [7:0] addr,
|
||||
input [31:0] wd,
|
||||
input we,
|
||||
input re,
|
||||
input clk,
|
||||
output reg [31:0] rd,
|
||||
);
|
||||
|
||||
reg [7:0] mem[0:255];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (we) begin
|
||||
mem[{addr[7:2], 2'b00}] <= wd[7:0];
|
||||
mem[{addr[7:2], 2'b01}] <= wd[15:8];
|
||||
mem[{addr[7:2], 2'b10}] <= wd[23:16];
|
||||
mem[{addr[7:2], 2'b11}] <= wd[31:24];
|
||||
end
|
||||
if (re) begin
|
||||
rd[7:0] <= mem[{addr[7:2], 2'b00}];
|
||||
rd[15:8] <= mem[{addr[7:2], 2'b01}];
|
||||
rd[23:16] <= mem[{addr[7:2], 2'b10}];
|
||||
rd[31:24] <= mem[{addr[7:2], 2'b11}];
|
||||
if (we)
|
||||
rd <= wd;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
opt_dff
|
||||
opt_clean
|
||||
dump
|
||||
memory_dff
|
||||
select -assert-count 4 t:$memrd_v2
|
||||
select -assert-count 1 t:$memrd_v2 r:TRANSPARENCY_MASK=4'b0001 r:COLLISION_X_MASK=4'b1110 %i %i
|
||||
select -assert-count 1 t:$memrd_v2 r:TRANSPARENCY_MASK=4'b0010 r:COLLISION_X_MASK=4'b1101 %i %i
|
||||
select -assert-count 1 t:$memrd_v2 r:TRANSPARENCY_MASK=4'b0100 r:COLLISION_X_MASK=4'b1011 %i %i
|
||||
select -assert-count 1 t:$memrd_v2 r:TRANSPARENCY_MASK=4'b1000 r:COLLISION_X_MASK=4'b0111 %i %i
|
||||
|
||||
design -reset
|
||||
Loading…
Reference in New Issue