mirror of https://github.com/YosysHQ/yosys.git
Add new opt_mem_priority pass.
This commit is contained in:
Marcelina Kościelnicka
parent
30927df881
commit
616ace2d92
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@ -36,9 +36,10 @@ struct MemoryPass : public Pass {
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log("This pass calls all the other memory_* passes in a useful order:\n");
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log("\n");
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log(" opt_mem\n");
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log(" opt_mem_priority\n");
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log(" opt_mem_feedback\n");
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log(" memory_dff (skipped if called with -nordff or -memx)\n");
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log(" opt_clean\n");
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log(" opt_mem_feedback\n");
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log(" memory_share\n");
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log(" memory_memx (when called with -memx)\n");
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log(" opt_clean\n");
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@ -84,10 +85,11 @@ struct MemoryPass : public Pass {
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extra_args(args, argidx, design);
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Pass::call(design, "opt_mem");
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Pass::call(design, "opt_mem_priority");
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Pass::call(design, "opt_mem_feedback");
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if (!flag_nordff)
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Pass::call(design, "memory_dff");
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Pass::call(design, "opt_clean");
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Pass::call(design, "opt_mem_feedback");
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Pass::call(design, "memory_share");
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if (flag_memx)
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Pass::call(design, "memory_memx");
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@ -3,6 +3,7 @@ OBJS += passes/opt/opt.o
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OBJS += passes/opt/opt_merge.o
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OBJS += passes/opt/opt_mem.o
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OBJS += passes/opt/opt_mem_feedback.o
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OBJS += passes/opt/opt_mem_priority.o
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OBJS += passes/opt/opt_muxtree.o
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OBJS += passes/opt/opt_reduce.o
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OBJS += passes/opt/opt_dff.o
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@ -0,0 +1,109 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2021 Marcelina Kościelnicka <mwk@0x04.net>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/modtools.h"
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#include "kernel/qcsat.h"
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#include "kernel/mem.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct OptMemPriorityPass : public Pass {
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OptMemPriorityPass() : Pass("opt_mem_priority", "remove priority relations between write ports that can never collide") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" opt_mem_priority [selection]\n");
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log("\n");
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log("This pass detects cases where one memory write port has priority over another\n");
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log("even though they can never collide with each other — ie. there can never be\n");
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log("a situation where a given memory bit is written by both ports at the same\n");
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log("time, for example because of always-different addresses, or mutually exclusive\n");
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log("enable signals. In such cases, the priority relation is removed.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override {
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log_header(design, "Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).\n");
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extra_args(args, 1, design);
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ModWalker modwalker(design);
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int total_count = 0;
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for (auto module : design->selected_modules()) {
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modwalker.setup(module);
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for (auto &mem : Mem::get_selected_memories(module)) {
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bool mem_changed = false;
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QuickConeSat qcsat(modwalker);
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for (int i = 0; i < GetSize(mem.wr_ports); i++) {
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auto &wport1 = mem.wr_ports[i];
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for (int j = 0; j < GetSize(mem.wr_ports); j++) {
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auto &wport2 = mem.wr_ports[j];
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if (!wport1.priority_mask[j])
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continue;
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// No mixed width support — we could do it, but
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// that would complicate code and wouldn't help
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// anything since we run this pass before
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// wide ports are created in normal flow.
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if (wport1.wide_log2 != wport2.wide_log2)
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continue;
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// Two ports with priority, let's go.
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pool<std::pair<SigBit, SigBit>> checked;
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SigSpec addr1 = wport1.addr;
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SigSpec addr2 = wport2.addr;
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int abits = std::max(GetSize(addr1), GetSize(addr2));
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addr1.extend_u0(abits);
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addr2.extend_u0(abits);
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int addr_eq = qcsat.ez->vec_eq(qcsat.importSig(addr1), qcsat.importSig(addr2));
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bool ok = true;
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for (int k = 0; k < GetSize(wport1.data); k++) {
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SigBit wen1 = wport1.en[k];
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SigBit wen2 = wport2.en[k];
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if (checked.count({wen1, wen2}))
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continue;
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int wen1_sat = qcsat.importSigBit(wen1);
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int wen2_sat = qcsat.importSigBit(wen2);
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qcsat.prepare();
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if (qcsat.ez->solve(wen1_sat, wen2_sat, addr_eq)) {
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ok = false;
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break;
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}
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checked.insert({wen1, wen2});
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}
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if (ok) {
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total_count++;
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mem_changed = true;
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wport1.priority_mask[j] = false;
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}
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}
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}
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if (mem_changed)
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mem.emit();
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}
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}
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if (total_count)
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design->scratchpad_set_bool("opt.did_something", true);
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log("Performed a total of %d transformations.\n", total_count);
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}
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} OptMemPriorityPass;
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PRIVATE_NAMESPACE_END
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@ -0,0 +1,205 @@
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# Bad case: independent write ports.
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read_verilog << EOT
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module top(
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input [3:0] wa1, wa2, ra, wd1, wd2,
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input clk, we1, we2,
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output [3:0] rd);
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reg [3:0] mem[0:15];
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assign rd = mem[ra];
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always @(posedge clk) begin
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if (we1)
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mem[wa1] <= wd1;
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if (we2)
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mem[wa2] <= wd2;
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end
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endmodule
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EOT
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hierarchy -auto-top
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proc
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opt
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memory -nomap
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select -assert-count 1 t:$mem_v2
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select -assert-count 1 t:$mem_v2 r:WR_PRIORITY_MASK=4'b0100 %i
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design -reset
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# Good case: write ports with definitely different addresses.
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read_verilog << EOT
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module top(
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input [3:0] wa, ra, wd1, wd2,
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input clk, we1, we2,
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output [3:0] rd);
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reg [3:0] mem[0:15];
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assign rd = mem[ra];
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always @(posedge clk) begin
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if (we1)
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mem[wa] <= wd1;
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if (we2)
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mem[wa ^ 1] <= wd2;
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end
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endmodule
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EOT
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hierarchy -auto-top
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proc
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opt
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memory -nomap
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select -assert-count 1 t:$mem_v2
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select -assert-count 1 t:$mem_v2 r:WR_PRIORITY_MASK=4'b0000 %i
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design -reset
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# Bad case 2: the above, but broken.
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read_verilog << EOT
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module top(
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input [3:0] wa, ra, wd1, wd2,
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input clk, we1, we2,
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output [3:0] rd);
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reg [3:0] mem[0:15];
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assign rd = mem[ra];
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always @(posedge clk) begin
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if (we1)
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mem[wa] <= wd1;
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if (we2)
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mem[wa | 1] <= wd2;
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end
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endmodule
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EOT
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hierarchy -auto-top
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proc
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opt
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memory -nomap
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select -assert-count 1 t:$mem_v2
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select -assert-count 1 t:$mem_v2 r:WR_PRIORITY_MASK=4'b0100 %i
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design -reset
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# Good case 2: write ports with disjoint bit enables.
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read_verilog << EOT
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module top(
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input [3:0] wa1, wa2, ra,
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input [1:0] wd1, wd2,
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input clk, we1, we2,
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output [3:0] rd);
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reg [3:0] mem[0:15];
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assign rd = mem[ra];
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always @(posedge clk) begin
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if (we1)
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mem[wa1][1:0] <= wd1;
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if (we2)
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mem[wa2][3:2] <= wd2;
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end
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endmodule
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EOT
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hierarchy -auto-top
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proc
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opt
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memory -nomap
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select -assert-count 1 t:$mem_v2
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select -assert-count 1 t:$mem_v2 r:WR_PRIORITY_MASK=4'b0000 %i
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design -reset
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# Good case 3: write ports with soft priority logic already
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read_verilog << EOT
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module top(
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input [3:0] wa1, wa2, ra, wd1, wd2,
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input clk, we1, we2,
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output [3:0] rd);
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reg [3:0] mem[0:15];
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assign rd = mem[ra];
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always @(posedge clk) begin
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if (we1)
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mem[wa1] <= wd1;
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if (we2 && wa1 != wa2)
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mem[wa2] <= wd2;
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end
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endmodule
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EOT
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hierarchy -auto-top
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proc
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opt
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memory -nomap
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select -assert-count 1 t:$mem_v2
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select -assert-count 1 t:$mem_v2 r:WR_PRIORITY_MASK=4'b0000 %i
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design -reset
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# Good case 4: two wide write ports
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read_verilog << EOT
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module top(
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input [5:0] wa1, wa2,
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input [7:0] ra,
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input [31:0] wd1, wd2,
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input clk, we1, we2,
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output [7:0] rd);
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reg [7:0] mem[0:255];
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assign rd = mem[ra];
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always @(posedge clk) begin
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if (we1) begin
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mem[{wa1, 2'b00}] <= wd1[7:0];
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mem[{wa1, 2'b01}] <= wd1[15:8];
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mem[{wa1, 2'b10}] <= wd1[23:16];
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mem[{wa1, 2'b11}] <= wd1[31:24];
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end
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if (we2) begin
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mem[{wa2, 2'b00}] <= wd2[7:0];
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mem[{wa2, 2'b01}] <= wd2[15:8];
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mem[{wa2, 2'b10}] <= wd2[23:16];
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mem[{wa2, 2'b11}] <= wd2[31:24];
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end
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end
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endmodule
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EOT
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hierarchy -auto-top
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proc
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opt
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memory -nomap
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select -assert-count 1 t:$mem_v2
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select -assert-count 1 t:$mem_v2 r:WR_PRIORITY_MASK=64'h0804020100000000 %i
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