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dfflegalize: Refactor, add aldff support.

This commit is contained in:
Marcelina Kościelnicka 2021-10-27 10:14:07 +02:00
parent bdf153d06c
commit 0a0df8d38c
12 changed files with 1158 additions and 1074 deletions
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192
kernel/ff.cc
View File

@ -303,6 +303,190 @@ FfData FfData::slice(const std::vector<int> &bits) {
return res;
}
void FfData::add_dummy_ce() {
if (has_ce)
return;
has_ce = true;
pol_ce = true;
sig_ce = State::S1;
ce_over_srst = false;
}
void FfData::add_dummy_srst() {
if (has_srst)
return;
has_srst = true;
pol_srst = true;
sig_srst = State::S0;
val_srst = Const(State::Sx, width);
ce_over_srst = false;
}
void FfData::add_dummy_arst() {
if (has_arst)
return;
has_arst = true;
pol_arst = true;
sig_arst = State::S0;
val_arst = Const(State::Sx, width);
}
void FfData::add_dummy_aload() {
if (has_aload)
return;
has_aload = true;
pol_aload = true;
sig_aload = State::S0;
sig_ad = Const(State::Sx, width);
}
void FfData::add_dummy_sr() {
if (has_sr)
return;
has_sr = true;
pol_clr = true;
pol_set = true;
sig_clr = Const(State::S0, width);
sig_set = Const(State::S0, width);
}
void FfData::add_dummy_clk() {
if (has_clk)
return;
has_clk = true;
pol_clk = true;
sig_clk = State::S0;
sig_d = Const(State::Sx, width);
}
void FfData::arst_to_aload() {
log_assert(has_arst);
log_assert(!has_aload);
pol_aload = pol_arst;
sig_aload = sig_arst;
sig_ad = val_arst;
has_aload = true;
has_arst = false;
}
void FfData::arst_to_sr() {
log_assert(has_arst);
log_assert(!has_sr);
pol_clr = pol_arst;
pol_set = pol_arst;
sig_clr = Const(pol_arst ? State::S0 : State::S1, width);
sig_set = Const(pol_arst ? State::S0 : State::S1, width);
has_sr = true;
has_arst = false;
for (int i = 0; i < width; i++) {
if (val_arst[i] == State::S1)
sig_set[i] = sig_arst;
else
sig_clr[i] = sig_arst;
}
}
void FfData::aload_to_sr() {
log_assert(has_aload);
log_assert(!has_sr);
has_sr = true;
has_aload = false;
if (!is_fine) {
pol_clr = false;
pol_set = true;
if (pol_aload) {
sig_clr = module->Mux(NEW_ID, Const(State::S1, width), sig_ad, sig_aload);
sig_set = module->Mux(NEW_ID, Const(State::S0, width), sig_ad, sig_aload);
} else {
sig_clr = module->Mux(NEW_ID, sig_ad, Const(State::S1, width), sig_aload);
sig_set = module->Mux(NEW_ID, sig_ad, Const(State::S0, width), sig_aload);
}
} else {
pol_clr = pol_aload;
pol_set = pol_aload;
if (pol_aload) {
sig_clr = module->AndnotGate(NEW_ID, sig_aload, sig_ad);
sig_set = module->AndGate(NEW_ID, sig_aload, sig_ad);
} else {
sig_clr = module->OrGate(NEW_ID, sig_aload, sig_ad);
sig_set = module->OrnotGate(NEW_ID, sig_aload, sig_ad);
}
}
}
void FfData::convert_ce_over_srst(bool val) {
if (!has_ce || !has_srst || ce_over_srst == val)
return;
if (val) {
// sdffe to sdffce
if (!is_fine) {
if (pol_ce) {
if (pol_srst) {
sig_ce = module->Or(NEW_ID, sig_ce, sig_srst);
} else {
SigSpec tmp = module->Not(NEW_ID, sig_srst);
sig_ce = module->Or(NEW_ID, sig_ce, tmp);
}
} else {
if (pol_srst) {
SigSpec tmp = module->Not(NEW_ID, sig_srst);
sig_ce = module->And(NEW_ID, sig_ce, tmp);
} else {
sig_ce = module->And(NEW_ID, sig_ce, sig_srst);
}
}
} else {
if (pol_ce) {
if (pol_srst) {
sig_ce = module->OrGate(NEW_ID, sig_ce, sig_srst);
} else {
sig_ce = module->OrnotGate(NEW_ID, sig_ce, sig_srst);
}
} else {
if (pol_srst) {
sig_ce = module->AndnotGate(NEW_ID, sig_ce, sig_srst);
} else {
sig_ce = module->AndGate(NEW_ID, sig_ce, sig_srst);
}
}
}
} else {
// sdffce to sdffe
if (!is_fine) {
if (pol_srst) {
if (pol_ce) {
sig_srst = cell->module->And(NEW_ID, sig_srst, sig_ce);
} else {
SigSpec tmp = module->Not(NEW_ID, sig_ce);
sig_srst = cell->module->And(NEW_ID, sig_srst, tmp);
}
} else {
if (pol_ce) {
SigSpec tmp = module->Not(NEW_ID, sig_ce);
sig_srst = cell->module->Or(NEW_ID, sig_srst, tmp);
} else {
sig_srst = cell->module->Or(NEW_ID, sig_srst, sig_ce);
}
}
} else {
if (pol_srst) {
if (pol_ce) {
sig_srst = cell->module->AndGate(NEW_ID, sig_srst, sig_ce);
} else {
sig_srst = cell->module->AndnotGate(NEW_ID, sig_srst, sig_ce);
}
} else {
if (pol_ce) {
sig_srst = cell->module->OrnotGate(NEW_ID, sig_srst, sig_ce);
} else {
sig_srst = cell->module->OrGate(NEW_ID, sig_srst, sig_ce);
}
}
}
}
ce_over_srst = val;
}
void FfData::unmap_ce() {
if (!has_ce)
return;
@ -351,11 +535,7 @@ Cell *FfData::emit() {
if (!has_aload && !has_clk && !has_gclk && !has_sr) {
if (has_arst) {
// Convert this case to a D latch.
has_aload = true;
has_arst = false;
sig_ad = val_arst;
sig_aload = sig_arst;
pol_aload = pol_arst;
arst_to_aload();
} else {
// No control inputs left. Turn into a const driver.
module->connect(sig_q, val_init);
@ -506,7 +686,7 @@ void FfData::flip_bits(const pool<int> &bits) {
}
if (has_sr && cell) {
log_warning("Flipping D/Q/init and inserting priority fixup to legalize %s.%s [%s].", log_id(module->name), log_id(cell->name), log_id(cell->type));
log_warning("Flipping D/Q/init and inserting priority fixup to legalize %s.%s [%s].\n", log_id(module->name), log_id(cell->name), log_id(cell->type));
}
if (is_fine) {

17
kernel/ff.h
View File

@ -170,8 +170,23 @@ struct FfData {
// Returns a FF identical to this one, but only keeping bit indices from the argument.
FfData slice(const std::vector<int> &bits);
void unmap_ce();
void add_dummy_ce();
void add_dummy_srst();
void add_dummy_arst();
void add_dummy_aload();
void add_dummy_sr();
void add_dummy_clk();
void arst_to_aload();
void arst_to_sr();
void aload_to_sr();
// Given a FF with both has_ce and has_srst, sets ce_over_srst to the given value and
// fixes up control signals appropriately to preserve semantics.
void convert_ce_over_srst(bool val);
void unmap_ce();
void unmap_srst();
void unmap_ce_srst() {

1904
passes/techmap/dfflegalize.cc
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File diff suppressed because it is too large Load Diff

26
tests/techmap/dfflegalize_adff_init.ys
View File

@ -144,9 +144,9 @@ design -load orig
dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_DLATCH_P_ 1
select -assert-count 2 adff0/t:$_NOT_
select -assert-count 16 adff1/t:$_NOT_
select -assert-count 13 adff1/t:$_NOT_
select -assert-count 3 adffe0/t:$_NOT_
select -assert-count 22 adffe1/t:$_NOT_
select -assert-count 18 adffe1/t:$_NOT_
select -assert-count 0 adff0/t:$_MUX_
select -assert-count 3 adff1/t:$_MUX_
select -assert-count 0 adffe0/t:$_MUX_
@ -164,9 +164,9 @@ select -assert-none t:$_DFFE_PP0P_ t:$_DLATCH_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t
design -load orig
dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_DLATCH_P_ 1
select -assert-count 16 adff0/t:$_NOT_
select -assert-count 13 adff0/t:$_NOT_
select -assert-count 8 adff1/t:$_NOT_
select -assert-count 22 adffe0/t:$_NOT_
select -assert-count 18 adffe0/t:$_NOT_
select -assert-count 11 adffe1/t:$_NOT_
select -assert-count 3 adff0/t:$_MUX_
select -assert-count 0 adff1/t:$_MUX_
@ -185,31 +185,27 @@ select -assert-none t:$_DFFE_PP0P_ t:$_DLATCH_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t
design -load orig
dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_DLATCH_P_ 1
select -assert-count 16 adff0/t:$_NOT_
select -assert-count 10 adff0/t:$_NOT_
select -assert-count 2 adff1/t:$_NOT_
select -assert-count 22 adffe0/t:$_NOT_
select -assert-count 14 adffe0/t:$_NOT_
select -assert-count 3 adffe1/t:$_NOT_
select -assert-count 3 adff0/t:$_MUX_
select -assert-count 0 adff1/t:$_MUX_
select -assert-count 4 adffe0/t:$_MUX_
select -assert-count 0 adffe1/t:$_MUX_
select -assert-count 6 adff0/t:$_DFFE_PP1P_
select -assert-count 9 adff0/t:$_DFFE_PP1P_
select -assert-count 3 adff1/t:$_DFFE_PP1P_
select -assert-count 8 adffe0/t:$_DFFE_PP1P_
select -assert-count 12 adffe0/t:$_DFFE_PP1P_
select -assert-count 4 adffe1/t:$_DFFE_PP1P_
select -assert-count 3 adff0/t:$_DLATCH_P_
select -assert-count 0 adff1/t:$_DLATCH_P_
select -assert-count 4 adffe0/t:$_DLATCH_P_
select -assert-count 0 adffe1/t:$_DLATCH_P_
select -assert-none t:$_DFFE_PP1P_ t:$_DLATCH_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
select -assert-none t:$_DFFE_PP1P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
design -load orig
dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_DLATCH_P_ 1
select -assert-count 8 adff0/t:$_NOT_
select -assert-count 16 adff1/t:$_NOT_
select -assert-count 13 adff1/t:$_NOT_
select -assert-count 11 adffe0/t:$_NOT_
select -assert-count 22 adffe1/t:$_NOT_
select -assert-count 18 adffe1/t:$_NOT_
select -assert-count 0 adff0/t:$_MUX_
select -assert-count 3 adff1/t:$_MUX_
select -assert-count 0 adffe0/t:$_MUX_

4
tests/techmap/dfflegalize_adlatch_init.ys
View File

@ -45,7 +45,7 @@ select -assert-none t:$_DLATCH_PP0_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
design -load orig
dfflegalize -cell $_DLATCH_PP0_ 1
select -assert-count 16 adlatch0/t:$_NOT_
select -assert-count 13 adlatch0/t:$_NOT_
select -assert-count 8 adlatch1/t:$_NOT_
select -assert-count 3 adlatch0/t:$_MUX_
select -assert-count 0 adlatch1/t:$_MUX_
@ -68,7 +68,7 @@ design -load orig
dfflegalize -cell $_DLATCH_PP1_ 1
select -assert-count 8 adlatch0/t:$_NOT_
select -assert-count 16 adlatch1/t:$_NOT_
select -assert-count 13 adlatch1/t:$_NOT_
select -assert-count 0 adlatch0/t:$_MUX_
select -assert-count 3 adlatch1/t:$_MUX_
select -assert-count 3 adlatch0/t:$_DLATCH_PP1_

17
tests/techmap/dfflegalize_dff.ys
View File

@ -237,25 +237,18 @@ select -assert-count 2 sdff0/t:$_NOT_
select -assert-count 8 sdff1/t:$_NOT_
select -assert-count 2 sdffe0/t:$_NOT_
select -assert-count 10 sdffe1/t:$_NOT_
select -assert-count 2 sdffce0/t:$_NOT_
select -assert-count 10 sdffce1/t:$_NOT_
select -assert-count 1 sdffce0/t:$_NOT_
select -assert-count 1 sdffce1/t:$_NOT_
select -assert-count 0 dff/t:$_MUX_
select -assert-count 3 dffe/t:$_MUX_
select -assert-count 0 sdff0/t:$_MUX_
select -assert-count 0 sdff1/t:$_MUX_
select -assert-count 4 sdffe0/t:$_MUX_
select -assert-count 4 sdffe1/t:$_MUX_
select -assert-count 4 sdffce0/t:$_MUX_
select -assert-count 4 sdffce1/t:$_MUX_
select -assert-count 0 t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffce0/* sdffce1/* %u %n %i
select -assert-count 2 sdffce0/t:$_AND_
select -assert-count 2 sdffce1/t:$_AND_
select -assert-count 1 sdffce0/t:$_ORNOT_
select -assert-count 1 sdffce1/t:$_ORNOT_
select -assert-count 1 sdffce0/t:$_ANDNOT_
select -assert-count 1 sdffce1/t:$_ANDNOT_
select -assert-count 8 sdffce0/t:$_MUX_
select -assert-count 8 sdffce1/t:$_MUX_
select -assert-count 27 t:$_SDFF_PP0_
select -assert-none t:$_SDFF_PP0_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i
select -assert-none t:$_SDFF_PP0_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
# Convert everything to SDFFEs.

40
tests/techmap/dfflegalize_dff_init.ys
View File

@ -476,7 +476,7 @@ select -assert-count 2 sdff0/t:$_NOT_
select -assert-count 1 sdff1/t:$_NOT_
select -assert-count 2 sdffe0/t:$_NOT_
select -assert-count 1 sdffe1/t:$_NOT_
select -assert-count 2 sdffce0/t:$_NOT_
select -assert-count 1 sdffce0/t:$_NOT_
select -assert-count 1 sdffce1/t:$_NOT_
select -assert-count 0 dff/t:$_MUX_
select -assert-count 3 dffe/t:$_MUX_
@ -484,14 +484,10 @@ select -assert-count 0 sdff0/t:$_MUX_
select -assert-count 3 sdff1/t:$_MUX_
select -assert-count 4 sdffe0/t:$_MUX_
select -assert-count 8 sdffe1/t:$_MUX_
select -assert-count 4 sdffce0/t:$_MUX_
select -assert-count 8 sdffce0/t:$_MUX_
select -assert-count 8 sdffce1/t:$_MUX_
select -assert-count 0 t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffce0/* %n %i
select -assert-count 2 sdffce0/t:$_AND_
select -assert-count 1 sdffce0/t:$_ORNOT_
select -assert-count 1 sdffce0/t:$_ANDNOT_
select -assert-count 27 t:$_SDFF_PP0_
select -assert-none t:$_SDFF_PP0_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i
select -assert-none t:$_SDFF_PP0_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
design -load orig
dfflegalize -cell $_SDFF_PP0_ 1
@ -503,7 +499,7 @@ select -assert-count 8 sdff1/t:$_NOT_
select -assert-count 9 sdffe0/t:$_NOT_
select -assert-count 10 sdffe1/t:$_NOT_
select -assert-count 9 sdffce0/t:$_NOT_
select -assert-count 10 sdffce1/t:$_NOT_
select -assert-count 9 sdffce1/t:$_NOT_
select -assert-count 0 dff/t:$_MUX_
select -assert-count 3 dffe/t:$_MUX_
select -assert-count 3 sdff0/t:$_MUX_
@ -511,13 +507,9 @@ select -assert-count 0 sdff1/t:$_MUX_
select -assert-count 8 sdffe0/t:$_MUX_
select -assert-count 4 sdffe1/t:$_MUX_
select -assert-count 8 sdffce0/t:$_MUX_
select -assert-count 4 sdffce1/t:$_MUX_
select -assert-count 0 t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffce1/* %n %i
select -assert-count 2 sdffce1/t:$_AND_
select -assert-count 1 sdffce1/t:$_ORNOT_
select -assert-count 1 sdffce1/t:$_ANDNOT_
select -assert-count 8 sdffce1/t:$_MUX_
select -assert-count 27 t:$_SDFF_PP0_
select -assert-none t:$_SDFF_PP0_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i
select -assert-none t:$_SDFF_PP0_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
design -load orig
dfflegalize -cell $_SDFF_PP1_ 0
@ -529,7 +521,7 @@ select -assert-count 2 sdff1/t:$_NOT_
select -assert-count 1 sdffe0/t:$_NOT_
select -assert-count 2 sdffe1/t:$_NOT_
select -assert-count 1 sdffce0/t:$_NOT_
select -assert-count 2 sdffce1/t:$_NOT_
select -assert-count 1 sdffce1/t:$_NOT_
select -assert-count 0 dff/t:$_MUX_
select -assert-count 3 dffe/t:$_MUX_
select -assert-count 3 sdff0/t:$_MUX_
@ -537,13 +529,9 @@ select -assert-count 0 sdff1/t:$_MUX_
select -assert-count 8 sdffe0/t:$_MUX_
select -assert-count 4 sdffe1/t:$_MUX_
select -assert-count 8 sdffce0/t:$_MUX_
select -assert-count 4 sdffce1/t:$_MUX_
select -assert-count 0 t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffce1/* %n %i
select -assert-count 2 sdffce1/t:$_AND_
select -assert-count 1 sdffce1/t:$_ORNOT_
select -assert-count 1 sdffce1/t:$_ANDNOT_
select -assert-count 8 sdffce1/t:$_MUX_
select -assert-count 27 t:$_SDFF_PP1_
select -assert-none t:$_SDFF_PP1_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i
select -assert-none t:$_SDFF_PP1_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
design -load orig
dfflegalize -cell $_SDFF_PP1_ 1
@ -554,7 +542,7 @@ select -assert-count 8 sdff0/t:$_NOT_
select -assert-count 7 sdff1/t:$_NOT_
select -assert-count 10 sdffe0/t:$_NOT_
select -assert-count 9 sdffe1/t:$_NOT_
select -assert-count 10 sdffce0/t:$_NOT_
select -assert-count 9 sdffce0/t:$_NOT_
select -assert-count 9 sdffce1/t:$_NOT_
select -assert-count 0 dff/t:$_MUX_
select -assert-count 3 dffe/t:$_MUX_
@ -562,14 +550,10 @@ select -assert-count 0 sdff0/t:$_MUX_
select -assert-count 3 sdff1/t:$_MUX_
select -assert-count 4 sdffe0/t:$_MUX_
select -assert-count 8 sdffe1/t:$_MUX_
select -assert-count 4 sdffce0/t:$_MUX_
select -assert-count 8 sdffce0/t:$_MUX_
select -assert-count 8 sdffce1/t:$_MUX_
select -assert-count 0 t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffce0/* %n %i
select -assert-count 2 sdffce0/t:$_AND_
select -assert-count 1 sdffce0/t:$_ORNOT_
select -assert-count 1 sdffce0/t:$_ANDNOT_
select -assert-count 27 t:$_SDFF_PP1_
select -assert-none t:$_SDFF_PP1_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i
select -assert-none t:$_SDFF_PP1_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
# Convert everything to SDFFEs.

8
tests/techmap/dfflegalize_dlatch_const.ys
View File

@ -24,14 +24,14 @@ equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
design -load orig
dfflegalize -cell $_DFF_PP0_ 01
select -assert-count 12 t:$_NOT_
select -assert-count 8 t:$_NOT_
select -assert-count 8 t:$_DFF_PP0_
select -assert-none t:$_DFF_PP0_ t:$_NOT_ %% %n t:* %i
design -load orig
dfflegalize -cell $_DFF_PP?_ 0
select -assert-count 12 t:$_NOT_
select -assert-count 8 t:$_NOT_
select -assert-count 4 t:$_DFF_PP0_
select -assert-count 4 t:$_DFF_PP1_
select -assert-none t:$_DFF_PP0_ t:$_DFF_PP1_ t:$_NOT_ %% %n t:* %i
@ -41,13 +41,13 @@ select -assert-none t:$_DFF_PP0_ t:$_DFF_PP1_ t:$_NOT_ %% %n t:* %i
design -load orig
dfflegalize -cell $_DFFSRE_PPPP_ 0
select -assert-count 12 t:$_NOT_
select -assert-count 8 t:$_NOT_
select -assert-count 8 t:$_DFFSRE_PPPP_
select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ %% %n t:* %i
design -load orig
dfflegalize -cell $_DFFSRE_PPPP_ 1
select -assert-count 12 t:$_NOT_
select -assert-count 8 t:$_NOT_
select -assert-count 8 t:$_DFFSRE_PPPP_
select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ %% %n t:* %i

8
tests/techmap/dfflegalize_dlatchsr_init.ys
View File

@ -66,8 +66,8 @@ select -assert-none t:$_DLATCH_PP0_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_O
design -load orig
dfflegalize -cell $_DLATCH_PP1_ 0
select -assert-count 22 dlatchsr0/t:$_NOT_
select -assert-count 26 dlatchsr1/t:$_NOT_
select -assert-count 18 dlatchsr0/t:$_NOT_
select -assert-count 22 dlatchsr1/t:$_NOT_
select -assert-count 4 dlatchsr0/t:$_MUX_
select -assert-count 4 dlatchsr1/t:$_MUX_
select -assert-count 12 dlatchsr0/t:$_DLATCH_PP1_
@ -81,8 +81,8 @@ select -assert-none t:$_DLATCH_PP1_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_O
design -load orig
dfflegalize -cell $_DLATCH_PP1_ 1
select -assert-count 22 dlatchsr0/t:$_NOT_
select -assert-count 26 dlatchsr1/t:$_NOT_
select -assert-count 18 dlatchsr0/t:$_NOT_
select -assert-count 22 dlatchsr1/t:$_NOT_
select -assert-count 4 dlatchsr0/t:$_MUX_
select -assert-count 4 dlatchsr1/t:$_MUX_
select -assert-count 12 dlatchsr0/t:$_DLATCH_PP1_

4
tests/techmap/dfflegalize_minsrst.ys
View File

@ -23,9 +23,9 @@ design -load postopt
select -assert-count 5 t:$_SDFF_PP0_
select -assert-count 1 t:$_SDFF_PP1_
select -assert-count 3 t:$_SDFFE_PP0P_
select -assert-count 1 t:$_SDFFE_PP0P_
select -assert-count 1 t:$_SDFFE_PP1P_
select -assert-count 1 t:$_SDFFCE_PP0P_
select -assert-count 3 t:$_SDFFCE_PP0P_
select -assert-count 1 t:$_SDFFCE_PP1P_
select -assert-count 8 t:$_MUX_
select -assert-count 0 n:ff0 %ci %ci t:$_MUX_ %i

2
tests/techmap/dfflegalize_sr.ys
View File

@ -39,7 +39,7 @@ select -assert-none t:$_DLATCH_PP0_ t:$_NOT_ %% %n t:* %i
design -load orig
dfflegalize -cell $_DLATCH_PP1_ x
select -assert-count 8 t:$_NOT_
select -assert-count 5 t:$_NOT_
select -assert-count 3 t:$_DLATCH_PP1_
select -assert-none t:$_DLATCH_PP1_ t:$_NOT_ %% %n t:* %i

10
tests/techmap/dfflegalize_sr_init.ys
View File

@ -12,7 +12,7 @@ $_SR_PN_ ff1 (.R(R), .S(S), .Q(Q[1]));
$_SR_NP_ ff2 (.R(R), .S(S), .Q(Q[2]));
endmodule
module top(input C, E, R, D, output [5:0] Q);
module top(input R, S, output [5:0] Q);
sr0 sr0_(.S(S), .R(R), .Q(Q[2:0]));
sr1 sr1_(.S(S), .R(R), .Q(Q[5:3]));
endmodule
@ -103,8 +103,8 @@ select -assert-none t:$_DLATCH_PP0_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/*
design -load orig
dfflegalize -cell $_DLATCH_PP1_ 0
select -assert-count 11 sr0/t:$_NOT_
select -assert-count 8 sr1/t:$_NOT_
select -assert-count 8 sr0/t:$_NOT_
select -assert-count 5 sr1/t:$_NOT_
select -assert-count 3 sr0/t:$_DLATCH_PP1_
select -assert-count 3 sr1/t:$_DLATCH_PP1_
select -assert-count 1 sr0/t:$_ANDNOT_
@ -118,8 +118,8 @@ select -assert-none t:$_DLATCH_PP1_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/*
design -load orig
dfflegalize -cell $_DLATCH_PP1_ 1
select -assert-count 8 sr0/t:$_NOT_
select -assert-count 11 sr1/t:$_NOT_
select -assert-count 5 sr0/t:$_NOT_
select -assert-count 8 sr1/t:$_NOT_
select -assert-count 3 sr0/t:$_DLATCH_PP1_
select -assert-count 3 sr1/t:$_DLATCH_PP1_
select -assert-count 0 sr0/t:$_ANDNOT_