mirror of https://github.com/YosysHQ/yosys.git
memory_collect: Use Mem helpers.
This commit is contained in:
Marcelina Kościelnicka
parent
248b193d6d
commit
e9978aaf15
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@ -18,231 +18,11 @@
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/mem.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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bool memcells_cmp(Cell *a, Cell *b)
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{
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if (a->type == ID($memrd) && b->type == ID($memrd))
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return a->name < b->name;
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if (a->type == ID($memrd) || b->type == ID($memrd))
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return (a->type == ID($memrd)) < (b->type == ID($memrd));
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return a->parameters.at(ID::PRIORITY).as_int() < b->parameters.at(ID::PRIORITY).as_int();
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}
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Cell *handle_memory(Module *module, RTLIL::Memory *memory)
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{
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log("Collecting $memrd, $memwr and $meminit for memory `%s' in module `%s':\n",
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memory->name.c_str(), module->name.c_str());
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Const init_data(State::Sx, memory->size * memory->width);
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SigMap sigmap(module);
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int wr_ports = 0;
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SigSpec sig_wr_clk;
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SigSpec sig_wr_clk_enable;
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SigSpec sig_wr_clk_polarity;
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SigSpec sig_wr_addr;
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SigSpec sig_wr_data;
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SigSpec sig_wr_en;
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int rd_ports = 0;
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SigSpec sig_rd_clk;
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SigSpec sig_rd_clk_enable;
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SigSpec sig_rd_clk_polarity;
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SigSpec sig_rd_transparent;
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SigSpec sig_rd_addr;
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SigSpec sig_rd_data;
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SigSpec sig_rd_en;
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int addr_bits = 0;
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std::vector<Cell*> memcells;
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for (auto cell : module->cells())
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if (cell->type.in(ID($memrd), ID($memwr), ID($meminit)) && memory->name == cell->parameters[ID::MEMID].decode_string()) {
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SigSpec addr = sigmap(cell->getPort(ID::ADDR));
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for (int i = 0; i < GetSize(addr); i++)
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if (addr[i] != State::S0)
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addr_bits = std::max(addr_bits, i+1);
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memcells.push_back(cell);
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}
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if (memory->start_offset == 0 && addr_bits < 30 && (1 << addr_bits) < memory->size)
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memory->size = 1 << addr_bits;
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if (memory->start_offset >= 0)
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addr_bits = std::min(addr_bits, ceil_log2(memory->size + memory->start_offset));
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addr_bits = std::max(addr_bits, 1);
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if (memcells.empty()) {
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log(" no cells found. removing memory.\n");
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return nullptr;
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}
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std::sort(memcells.begin(), memcells.end(), memcells_cmp);
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for (auto cell : memcells)
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{
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log(" %s (%s)\n", log_id(cell), log_id(cell->type));
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if (cell->type == ID($meminit))
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{
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SigSpec addr = sigmap(cell->getPort(ID::ADDR));
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SigSpec data = sigmap(cell->getPort(ID::DATA));
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if (!addr.is_fully_const())
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log_error("Non-constant address %s in memory initialization %s.\n", log_signal(addr), log_id(cell));
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if (!data.is_fully_const())
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log_error("Non-constant data %s in memory initialization %s.\n", log_signal(data), log_id(cell));
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int offset = (addr.as_int() - memory->start_offset) * memory->width;
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if (offset < 0 || offset + GetSize(data) > GetSize(init_data))
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log_warning("Address %s in memory initialization %s is out-of-bounds.\n", log_signal(addr), log_id(cell));
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for (int i = 0; i < GetSize(data); i++)
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if (0 <= i+offset && i+offset < GetSize(init_data))
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init_data.bits[i+offset] = data[i].data;
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continue;
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}
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if (cell->type == ID($memwr))
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{
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SigSpec clk = sigmap(cell->getPort(ID::CLK));
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SigSpec clk_enable = SigSpec(cell->parameters[ID::CLK_ENABLE]);
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SigSpec clk_polarity = SigSpec(cell->parameters[ID::CLK_POLARITY]);
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SigSpec addr = sigmap(cell->getPort(ID::ADDR));
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SigSpec data = sigmap(cell->getPort(ID::DATA));
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SigSpec en = sigmap(cell->getPort(ID::EN));
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if (!en.is_fully_zero())
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{
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clk.extend_u0(1, false);
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clk_enable.extend_u0(1, false);
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clk_polarity.extend_u0(1, false);
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addr.extend_u0(addr_bits, false);
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data.extend_u0(memory->width, false);
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en.extend_u0(memory->width, false);
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sig_wr_clk.append(clk);
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sig_wr_clk_enable.append(clk_enable);
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sig_wr_clk_polarity.append(clk_polarity);
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sig_wr_addr.append(addr);
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sig_wr_data.append(data);
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sig_wr_en.append(en);
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wr_ports++;
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}
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continue;
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}
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if (cell->type == ID($memrd))
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{
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SigSpec clk = sigmap(cell->getPort(ID::CLK));
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SigSpec clk_enable = SigSpec(cell->parameters[ID::CLK_ENABLE]);
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SigSpec clk_polarity = SigSpec(cell->parameters[ID::CLK_POLARITY]);
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SigSpec transparent = SigSpec(cell->parameters[ID::TRANSPARENT]);
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SigSpec addr = sigmap(cell->getPort(ID::ADDR));
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SigSpec data = sigmap(cell->getPort(ID::DATA));
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SigSpec en = sigmap(cell->getPort(ID::EN));
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if (!en.is_fully_zero())
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{
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clk.extend_u0(1, false);
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clk_enable.extend_u0(1, false);
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clk_polarity.extend_u0(1, false);
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transparent.extend_u0(1, false);
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addr.extend_u0(addr_bits, false);
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data.extend_u0(memory->width, false);
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sig_rd_clk.append(clk);
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sig_rd_clk_enable.append(clk_enable);
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sig_rd_clk_polarity.append(clk_polarity);
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sig_rd_transparent.append(transparent);
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sig_rd_addr.append(addr);
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sig_rd_data.append(data);
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sig_rd_en.append(en);
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rd_ports++;
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}
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continue;
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}
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}
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std::stringstream sstr;
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sstr << "$mem$" << memory->name.str() << "$" << (autoidx++);
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Cell *mem = module->addCell(sstr.str(), ID($mem));
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mem->parameters[ID::MEMID] = Const(memory->name.str());
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mem->parameters[ID::WIDTH] = Const(memory->width);
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mem->parameters[ID::OFFSET] = Const(memory->start_offset);
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mem->parameters[ID::SIZE] = Const(memory->size);
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mem->parameters[ID::ABITS] = Const(addr_bits);
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mem->parameters[ID::INIT] = init_data;
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log_assert(sig_wr_clk.size() == wr_ports);
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log_assert(sig_wr_clk_enable.size() == wr_ports && sig_wr_clk_enable.is_fully_const());
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log_assert(sig_wr_clk_polarity.size() == wr_ports && sig_wr_clk_polarity.is_fully_const());
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log_assert(sig_wr_addr.size() == wr_ports * addr_bits);
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log_assert(sig_wr_data.size() == wr_ports * memory->width);
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log_assert(sig_wr_en.size() == wr_ports * memory->width);
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mem->parameters[ID::WR_PORTS] = Const(wr_ports);
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mem->parameters[ID::WR_CLK_ENABLE] = wr_ports ? sig_wr_clk_enable.as_const() : State::S0;
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mem->parameters[ID::WR_CLK_POLARITY] = wr_ports ? sig_wr_clk_polarity.as_const() : State::S0;
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mem->setPort(ID::WR_CLK, sig_wr_clk);
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mem->setPort(ID::WR_ADDR, sig_wr_addr);
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mem->setPort(ID::WR_DATA, sig_wr_data);
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mem->setPort(ID::WR_EN, sig_wr_en);
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log_assert(sig_rd_clk.size() == rd_ports);
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log_assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const());
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log_assert(sig_rd_clk_polarity.size() == rd_ports && sig_rd_clk_polarity.is_fully_const());
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log_assert(sig_rd_addr.size() == rd_ports * addr_bits);
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log_assert(sig_rd_data.size() == rd_ports * memory->width);
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mem->parameters[ID::RD_PORTS] = Const(rd_ports);
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mem->parameters[ID::RD_CLK_ENABLE] = rd_ports ? sig_rd_clk_enable.as_const() : State::S0;
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mem->parameters[ID::RD_CLK_POLARITY] = rd_ports ? sig_rd_clk_polarity.as_const() : State::S0;
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mem->parameters[ID::RD_TRANSPARENT] = rd_ports ? sig_rd_transparent.as_const() : State::S0;
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mem->setPort(ID::RD_CLK, sig_rd_clk);
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mem->setPort(ID::RD_ADDR, sig_rd_addr);
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mem->setPort(ID::RD_DATA, sig_rd_data);
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mem->setPort(ID::RD_EN, sig_rd_en);
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// Copy attributes from RTLIL memory to $mem
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for (auto attr : memory->attributes)
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mem->attributes[attr.first] = attr.second;
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for (auto c : memcells)
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module->remove(c);
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return mem;
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}
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static void handle_module(Design *design, Module *module)
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{
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std::vector<pair<Cell*, IdString>> finqueue;
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for (auto &mem_it : module->memories)
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if (design->selected(module, mem_it.second)) {
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Cell *c = handle_memory(module, mem_it.second);
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finqueue.push_back(pair<Cell*, IdString>(c, mem_it.first));
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}
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for (auto &it : finqueue) {
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delete module->memories.at(it.second);
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module->memories.erase(it.second);
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if (it.first)
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module->rename(it.first, it.second);
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}
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}
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struct MemoryCollectPass : public Pass {
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MemoryCollectPass() : Pass("memory_collect", "creating multi-port memory cells") { }
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void help() override
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@ -258,8 +38,14 @@ struct MemoryCollectPass : public Pass {
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void execute(std::vector<std::string> args, RTLIL::Design *design) override {
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log_header(design, "Executing MEMORY_COLLECT pass (generating $mem cells).\n");
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extra_args(args, 1, design);
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for (auto module : design->selected_modules())
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handle_module(design, module);
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for (auto module : design->selected_modules()) {
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for (auto &mem : Mem::get_selected_memories(module)) {
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if (!mem.packed) {
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mem.packed = true;
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mem.emit();
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}
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}
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}
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}
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} MemoryCollectPass;
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