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opt_share: Fix X and CO signal width for shifted $alu in opt_share. 

These need to be the same length as actual Y, not visible part of Y.

Fixes #2538.
This commit is contained in:
Marcelina Kościelnicka 2021-01-14 09:58:33 +01:00
parent 7cd044bbc4
commit 01626e6746
2 changed files with 22 additions and 2 deletions
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4
passes/opt/opt_share.cc
View File

@ -244,8 +244,8 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
}
if (shared_op->type.in(ID($alu))) {
shared_op->setPort(ID::X, module->addWire(NEW_ID, GetSize(new_sig_out)));
shared_op->setPort(ID::CO, module->addWire(NEW_ID, GetSize(new_sig_out)));
shared_op->setPort(ID::X, module->addWire(NEW_ID, GetSize(new_out)));
shared_op->setPort(ID::CO, module->addWire(NEW_ID, GetSize(new_out)));
}
bool is_fine = shared_op->type.in(FINE_BITWISE_OPS);

20
tests/opt/opt_share_bug2538.ys Normal file
View File

@ -0,0 +1,20 @@
read_verilog <<EOT
module top(...);
input [3:0] A;
input S;
output [1:0] Y;
wire [3:0] A1 = A + 1;
wire [3:0] A2 = A + 2;
assign Y = S ? A1[3:2] : A2[3:2];
endmodule
EOT
proc
alumacc
equiv_opt -assert opt_share