mirror of https://github.com/YosysHQ/yosys.git
abc: Refactor to use FfInitVals.
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336b8c7786
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522f367db3
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@ -44,6 +44,7 @@
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/celltypes.h"
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#include "kernel/ffinit.h"
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#include "kernel/cost.h"
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#include "kernel/log.h"
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#include <stdlib.h>
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@ -111,7 +112,7 @@ SigMap assign_map;
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RTLIL::Module *module;
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std::vector<gate_t> signal_list;
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std::map<RTLIL::SigBit, int> signal_map;
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std::map<RTLIL::SigBit, RTLIL::State> signal_init;
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FfInitVals initvals;
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pool<std::string> enabled_gates;
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bool recover_init, cmos_cost;
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@ -133,10 +134,7 @@ int map_signal(RTLIL::SigBit bit, gate_type_t gate_type = G(NONE), int in1 = -1,
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gate.in4 = -1;
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gate.is_port = false;
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gate.bit = bit;
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if (signal_init.count(bit))
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gate.init = signal_init.at(bit);
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else
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gate.init = State::Sx;
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gate.init = initvals(bit);
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signal_list.push_back(gate);
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signal_map[bit] = gate.id;
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}
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@ -1468,7 +1466,7 @@ struct AbcPass : public Pass {
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assign_map.clear();
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signal_list.clear();
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signal_map.clear();
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signal_init.clear();
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initvals.clear();
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pi_map.clear();
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po_map.clear();
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@ -1854,24 +1852,7 @@ struct AbcPass : public Pass {
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}
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assign_map.set(mod);
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signal_init.clear();
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for (Wire *wire : mod->wires())
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if (wire->attributes.count(ID::init)) {
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SigSpec initsig = assign_map(wire);
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Const initval = wire->attributes.at(ID::init);
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for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
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switch (initval[i]) {
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case State::S0:
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signal_init[initsig[i]] = State::S0;
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break;
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case State::S1:
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signal_init[initsig[i]] = State::S1;
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break;
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default:
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break;
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}
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}
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initvals.set(&assign_map, mod);
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if (!dff_mode || !clk_str.empty()) {
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abc_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
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@ -2028,7 +2009,7 @@ struct AbcPass : public Pass {
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assign_map.clear();
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signal_list.clear();
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signal_map.clear();
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signal_init.clear();
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initvals.clear();
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pi_map.clear();
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po_map.clear();
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