mirror of https://github.com/YosysHQ/yosys.git
memory_share: Improve same-address merging, recognize wide write ports.
This commit is contained in:
Marcelina Kościelnicka
parent
b019db1f37
commit
1eae6025e7
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@ -33,230 +33,100 @@ struct MemoryShareWorker
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SigMap sigmap, sigmap_xmux;
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ModWalker modwalker;
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CellTypes cone_ct;
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bool flag_widen;
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// ------------------------------------------------------
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// Consolidate write ports that write to the same address
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// (or close enough to be merged to wide ports)
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// ------------------------------------------------------
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RTLIL::SigSpec mask_en_naive(RTLIL::SigSpec do_mask, RTLIL::SigSpec bits, RTLIL::SigSpec mask_bits)
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{
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// this is the naive version of the function that does not care about grouping the EN bits.
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RTLIL::SigSpec inv_mask_bits = module->Not(NEW_ID, mask_bits);
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RTLIL::SigSpec inv_mask_bits_filtered = module->Mux(NEW_ID, RTLIL::SigSpec(RTLIL::State::S1, bits.size()), inv_mask_bits, do_mask);
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RTLIL::SigSpec result = module->And(NEW_ID, inv_mask_bits_filtered, bits);
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return result;
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}
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RTLIL::SigSpec mask_en_grouped(RTLIL::SigSpec do_mask, RTLIL::SigSpec bits, RTLIL::SigSpec mask_bits)
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{
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// this version of the function preserves the bit grouping in the EN bits.
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std::vector<RTLIL::SigBit> v_bits = bits;
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std::vector<RTLIL::SigBit> v_mask_bits = mask_bits;
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std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, std::pair<int, std::vector<int>>> groups;
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RTLIL::SigSpec grouped_bits, grouped_mask_bits;
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for (int i = 0; i < bits.size(); i++) {
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std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_bits[i], v_mask_bits[i]);
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if (groups.count(key) == 0) {
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groups[key].first = grouped_bits.size();
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grouped_bits.append(v_bits[i]);
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grouped_mask_bits.append(v_mask_bits[i]);
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}
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groups[key].second.push_back(i);
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}
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std::vector<RTLIL::SigBit> grouped_result = mask_en_naive(do_mask, grouped_bits, grouped_mask_bits);
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RTLIL::SigSpec result;
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for (int i = 0; i < bits.size(); i++) {
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std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_bits[i], v_mask_bits[i]);
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result.append(grouped_result.at(groups.at(key).first));
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}
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return result;
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}
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void merge_en_data(RTLIL::SigSpec &merged_en, RTLIL::SigSpec &merged_data, RTLIL::SigSpec next_en, RTLIL::SigSpec next_data)
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{
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std::vector<RTLIL::SigBit> v_old_en = merged_en;
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std::vector<RTLIL::SigBit> v_next_en = next_en;
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// The new merged_en signal is just the old merged_en signal and next_en OR'ed together.
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// But of course we need to preserve the bit grouping..
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std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups;
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std::vector<RTLIL::SigBit> grouped_old_en, grouped_next_en;
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RTLIL::SigSpec new_merged_en;
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for (int i = 0; i < int(v_old_en.size()); i++) {
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std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_old_en[i], v_next_en[i]);
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if (groups.count(key) == 0) {
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groups[key] = grouped_old_en.size();
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grouped_old_en.push_back(key.first);
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grouped_next_en.push_back(key.second);
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}
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}
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std::vector<RTLIL::SigBit> grouped_new_en = module->Or(NEW_ID, grouped_old_en, grouped_next_en);
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for (int i = 0; i < int(v_old_en.size()); i++) {
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std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_old_en[i], v_next_en[i]);
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new_merged_en.append(grouped_new_en.at(groups.at(key)));
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}
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// Create the new merged_data signal.
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RTLIL::SigSpec new_merged_data(RTLIL::State::Sx, merged_data.size());
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RTLIL::SigSpec old_data_set = module->And(NEW_ID, merged_en, merged_data);
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RTLIL::SigSpec old_data_unset = module->And(NEW_ID, merged_en, module->Not(NEW_ID, merged_data));
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RTLIL::SigSpec new_data_set = module->And(NEW_ID, next_en, next_data);
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RTLIL::SigSpec new_data_unset = module->And(NEW_ID, next_en, module->Not(NEW_ID, next_data));
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new_merged_data = module->Or(NEW_ID, new_merged_data, old_data_set);
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new_merged_data = module->And(NEW_ID, new_merged_data, module->Not(NEW_ID, old_data_unset));
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new_merged_data = module->Or(NEW_ID, new_merged_data, new_data_set);
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new_merged_data = module->And(NEW_ID, new_merged_data, module->Not(NEW_ID, new_data_unset));
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// Update merged_* signals
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merged_en = new_merged_en;
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merged_data = new_merged_data;
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}
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void consolidate_wr_by_addr(Mem &mem)
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bool consolidate_wr_by_addr(Mem &mem)
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{
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if (GetSize(mem.wr_ports) <= 1)
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return;
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return false;
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log("Consolidating write ports of memory %s.%s by address:\n", log_id(module), log_id(mem.memid));
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std::map<RTLIL::SigSpec, int> last_port_by_addr;
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std::vector<std::vector<bool>> active_bits_on_port;
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bool cache_clk_enable = false;
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bool cache_clk_polarity = false;
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RTLIL::SigSpec cache_clk;
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int cache_wide_log2 = 0;
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bool changed = false;
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for (int i = 0; i < GetSize(mem.wr_ports); i++)
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{
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auto &port = mem.wr_ports[i];
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RTLIL::SigSpec addr = sigmap_xmux(port.addr);
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if (port.clk_enable != cache_clk_enable ||
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port.wide_log2 != cache_wide_log2 ||
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(cache_clk_enable && (sigmap(port.clk) != cache_clk ||
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port.clk_polarity != cache_clk_polarity)))
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auto &port1 = mem.wr_ports[i];
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if (port1.removed)
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continue;
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if (!port1.clk_enable)
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continue;
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for (int j = i + 1; j < GetSize(mem.wr_ports); j++)
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{
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cache_clk_enable = port.clk_enable;
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cache_clk_polarity = port.clk_polarity;
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cache_clk = sigmap(port.clk);
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cache_wide_log2 = port.wide_log2;
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last_port_by_addr.clear();
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if (cache_clk_enable)
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log(" New clock domain: %s %s\n", cache_clk_polarity ? "posedge" : "negedge", log_signal(cache_clk));
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else
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log(" New clock domain: unclocked\n");
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}
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log(" Port %d has addr %s.\n", i, log_signal(addr));
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log(" Active bits: ");
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std::vector<RTLIL::SigBit> en_bits = sigmap(port.en);
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active_bits_on_port.push_back(std::vector<bool>(en_bits.size()));
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for (int k = int(en_bits.size())-1; k >= 0; k--) {
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active_bits_on_port[i][k] = en_bits[k].wire != NULL || en_bits[k].data != RTLIL::State::S0;
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log("%c", active_bits_on_port[i][k] ? '1' : '0');
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}
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log("\n");
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if (last_port_by_addr.count(addr))
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{
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int last_i = last_port_by_addr.at(addr);
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log(" Merging port %d into this one.\n", last_i);
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bool found_overlapping_bits = false;
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for (int k = 0; k < int(en_bits.size()); k++) {
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if (active_bits_on_port[i][k] && active_bits_on_port[last_i][k])
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found_overlapping_bits = true;
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active_bits_on_port[i][k] = active_bits_on_port[i][k] || active_bits_on_port[last_i][k];
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}
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// Force this ports addr input to addr directly (skip don't care muxes)
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port.addr = addr;
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// If any of the ports between `last_i' and `i' write to the same address, this
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// will have priority over whatever `last_i` wrote. So we need to revisit those
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// ports and mask the EN bits accordingly.
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RTLIL::SigSpec merged_en = sigmap(mem.wr_ports[last_i].en);
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for (int j = last_i+1; j < i; j++)
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{
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if (mem.wr_ports[j].removed)
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auto &port2 = mem.wr_ports[j];
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if (port2.removed)
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continue;
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if (!port2.clk_enable)
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continue;
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if (port1.clk != port2.clk)
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continue;
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if (port1.clk_polarity != port2.clk_polarity)
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continue;
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// If the width of the ports doesn't match, they can still be
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// merged by widening the narrow one. Check if the conditions
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// hold for that.
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int wide_log2 = std::max(port1.wide_log2, port2.wide_log2);
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if (GetSize(port1.addr) <= wide_log2)
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continue;
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if (GetSize(port2.addr) <= wide_log2)
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continue;
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if (!port1.addr.extract(0, wide_log2).is_fully_const())
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continue;
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if (!port2.addr.extract(0, wide_log2).is_fully_const())
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continue;
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if (sigmap_xmux(port1.addr.extract_end(wide_log2)) != sigmap_xmux(port2.addr.extract_end(wide_log2))) {
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// Incompatible addresses after widening. Last chance — widen both
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// ports by one more bit to merge them.
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if (!flag_widen)
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continue;
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for (int k = 0; k < int(en_bits.size()); k++)
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if (active_bits_on_port[i][k] && active_bits_on_port[j][k])
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goto found_overlapping_bits_i_j;
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if (0) {
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found_overlapping_bits_i_j:
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log(" Creating collosion-detect logic for port %d.\n", j);
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RTLIL::SigSpec is_same_addr = module->addWire(NEW_ID);
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module->addEq(NEW_ID, addr, mem.wr_ports[j].addr, is_same_addr);
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merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(mem.wr_ports[j].en));
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wide_log2++;
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if (sigmap_xmux(port1.addr.extract_end(wide_log2)) != sigmap_xmux(port2.addr.extract_end(wide_log2)))
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continue;
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if (!port1.addr.extract(0, wide_log2).is_fully_const())
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continue;
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if (!port2.addr.extract(0, wide_log2).is_fully_const())
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continue;
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}
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log(" Merging ports %d, %d (address %s).\n", i, j, log_signal(port1.addr));
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mem.prepare_wr_merge(i, j);
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port1.addr = sigmap_xmux(port1.addr);
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port2.addr = sigmap_xmux(port2.addr);
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mem.widen_wr_port(i, wide_log2);
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mem.widen_wr_port(j, wide_log2);
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int pos = 0;
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while (pos < GetSize(port1.data)) {
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int epos = pos;
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while (epos < GetSize(port1.data) && port1.en[epos] == port1.en[pos] && port2.en[epos] == port2.en[pos])
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epos++;
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int width = epos - pos;
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SigBit new_en;
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if (port2.en[pos] == State::S0) {
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new_en = port1.en[pos];
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} else if (port1.en[pos] == State::S0) {
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port1.data.replace(pos, port2.data.extract(pos, width));
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new_en = port2.en[pos];
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} else {
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port1.data.replace(pos, module->Mux(NEW_ID, port1.data.extract(pos, width), port2.data.extract(pos, width), port2.en[pos]));
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new_en = module->Or(NEW_ID, port1.en[pos], port2.en[pos]);
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}
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for (int k = pos; k < epos; k++)
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port1.en[k] = new_en;
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pos = epos;
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}
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// Then we need to merge the (masked) EN and the DATA signals.
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RTLIL::SigSpec merged_data = mem.wr_ports[last_i].data;
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if (found_overlapping_bits) {
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log(" Creating logic for merging DATA and EN ports.\n");
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merge_en_data(merged_en, merged_data, sigmap(port.en), sigmap(port.data));
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} else {
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RTLIL::SigSpec cell_en = sigmap(port.en);
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RTLIL::SigSpec cell_data = sigmap(port.data);
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for (int k = 0; k < int(en_bits.size()); k++)
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if (!active_bits_on_port[last_i][k]) {
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merged_en.replace(k, cell_en.extract(k, 1));
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merged_data.replace(k, cell_data.extract(k, 1));
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}
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}
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// Connect the new EN and DATA signals and remove the old write port.
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port.en = merged_en;
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port.data = merged_data;
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mem.wr_ports[last_i].removed = true;
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changed = true;
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log(" Active bits: ");
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std::vector<RTLIL::SigBit> en_bits = sigmap(port.en);
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active_bits_on_port.push_back(std::vector<bool>(en_bits.size()));
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for (int k = int(en_bits.size())-1; k >= 0; k--)
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log("%c", active_bits_on_port[i][k] ? '1' : '0');
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log("\n");
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port2.removed = true;
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}
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last_port_by_addr[addr] = i;
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}
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if (changed)
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mem.emit();
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return changed;
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}
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@ -441,7 +311,7 @@ struct MemoryShareWorker
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// Setup and run
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// -------------
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MemoryShareWorker(RTLIL::Design *design) : design(design), modwalker(design) {}
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MemoryShareWorker(RTLIL::Design *design, bool flag_widen) : design(design), modwalker(design), flag_widen(flag_widen) {}
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void operator()(RTLIL::Module* module)
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{
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@ -465,8 +335,9 @@ struct MemoryShareWorker
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}
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}
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for (auto &mem : memories)
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consolidate_wr_by_addr(mem);
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for (auto &mem : memories) {
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while (consolidate_wr_by_addr(mem));
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}
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cone_ct.setup_internals();
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cone_ct.cell_types.erase(ID($mul));
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@ -515,8 +386,10 @@ struct MemorySharePass : public Pass {
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override {
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log_header(design, "Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).\n");
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// TODO: expose when wide ports are actually supported.
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bool flag_widen = false;
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extra_args(args, 1, design);
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MemoryShareWorker msw(design);
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MemoryShareWorker msw(design, flag_widen);
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for (auto module : design->selected_modules())
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msw(module);
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