mirror of https://github.com/YosysHQ/yosys.git
clk2fflogic: Support all FF types.
This commit is contained in:
Marcelina Kościelnicka
parent
0c6d0d4b5d
commit
abe4e9e607
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@ -19,6 +19,8 @@
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/ffinit.h"
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#include "kernel/ff.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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@ -80,19 +82,7 @@ struct Clk2fflogicPass : public Pass {
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for (auto module : design->selected_modules())
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{
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SigMap sigmap(module);
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dict<SigBit, State> initbits;
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pool<SigBit> del_initbits;
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for (auto wire : module->wires())
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if (wire->attributes.count(ID::init) > 0)
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{
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Const initval = wire->attributes.at(ID::init);
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SigSpec initsig = sigmap(wire);
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for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
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if (initval[i] == State::S0 || initval[i] == State::S1)
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initbits[initsig[i]] = initval[i];
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}
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FfInitVals initvals(&sigmap, module);
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for (auto cell : vector<Cell*>(module->selected_cells()))
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{
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@ -177,221 +167,153 @@ struct Clk2fflogicPass : public Pass {
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cell->setPort(ID::WR_DATA, wr_data_port);
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}
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if (cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr)))
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{
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bool enpol = cell->parameters[ID::EN_POLARITY].as_bool();
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SigSpec qval;
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if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
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FfData ff(&initvals, cell);
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SigSpec sig_en = cell->getPort(ID::EN);
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SigSpec sig_d = cell->getPort(ID::D);
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SigSpec sig_q = cell->getPort(ID::Q);
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log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
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log_id(module), log_id(cell), log_id(cell->type),
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log_signal(sig_en), log_signal(sig_d), log_signal(sig_q));
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sig_en = wrap_async_control(module, sig_en, enpol);
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Wire *past_q = module->addWire(NEW_ID, GetSize(sig_q));
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module->addFf(NEW_ID, sig_q, past_q);
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if (cell->type == ID($dlatch))
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{
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module->addMux(NEW_ID, past_q, sig_d, sig_en, sig_q);
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}
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else if (cell->type == ID($adlatch))
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{
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SigSpec t = module->Mux(NEW_ID, past_q, sig_d, sig_en);
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SigSpec arst = wrap_async_control(module, cell->getPort(ID::ARST), cell->parameters[ID::ARST_POLARITY].as_bool());
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Const rstval = cell->parameters[ID::ARST_VALUE];
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module->addMux(NEW_ID, t, rstval, arst, sig_q);
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}
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else
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{
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SigSpec t = module->Mux(NEW_ID, past_q, sig_d, sig_en);
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SigSpec s = wrap_async_control(module, cell->getPort(ID::SET), cell->parameters[ID::SET_POLARITY].as_bool());
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t = module->Or(NEW_ID, t, s);
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SigSpec c = wrap_async_control(module, cell->getPort(ID::CLR), cell->parameters[ID::CLR_POLARITY].as_bool());
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c = module->Not(NEW_ID, c);
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module->addAnd(NEW_ID, t, c, sig_q);
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if (ff.has_d && !ff.has_clk && !ff.has_en) {
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// Already a $ff or $_FF_ cell.
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continue;
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}
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Const initval;
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bool assign_initval = false;
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for (int i = 0; i < GetSize(sig_d); i++) {
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SigBit qbit = sigmap(sig_q[i]);
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if (initbits.count(qbit)) {
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initval.bits.push_back(initbits.at(qbit));
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del_initbits.insert(qbit);
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} else
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initval.bits.push_back(State::Sx);
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if (initval.bits.back() != State::Sx)
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assign_initval = true;
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}
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if (assign_initval)
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past_q->attributes[ID::init] = initval;
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module->remove(cell);
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continue;
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}
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bool word_dff = cell->type.in(ID($dff), ID($adff), ID($dffsr));
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if (word_dff || cell->type.in(ID($_DFF_N_), ID($_DFF_P_),
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ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
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ID($_DFF_PP0_), ID($_DFF_PP1_), ID($_DFF_PN0_), ID($_DFF_PN1_),
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ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_),
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ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_)))
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{
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bool clkpol;
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SigSpec clk;
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if (word_dff) {
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clkpol = cell->parameters[ID::CLK_POLARITY].as_bool();
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clk = cell->getPort(ID::CLK);
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}
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else {
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if (cell->type.in(ID($_DFF_P_), ID($_DFF_N_),
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ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
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ID($_DFF_PP0_), ID($_DFF_PP1_), ID($_DFF_PN0_), ID($_DFF_PN1_)))
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clkpol = cell->type[6] == 'P';
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else if (cell->type.in(ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_),
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ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_)))
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clkpol = cell->type[8] == 'P';
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else log_abort();
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clk = cell->getPort(ID::C);
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}
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Wire *past_clk = module->addWire(NEW_ID);
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past_clk->attributes[ID::init] = clkpol ? State::S1 : State::S0;
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if (word_dff)
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module->addFf(NEW_ID, clk, past_clk);
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else
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module->addFfGate(NEW_ID, clk, past_clk);
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SigSpec sig_d = cell->getPort(ID::D);
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SigSpec sig_q = cell->getPort(ID::Q);
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log("Replacing %s.%s (%s): CLK=%s, D=%s, Q=%s\n",
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log_id(module), log_id(cell), log_id(cell->type),
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log_signal(clk), log_signal(sig_d), log_signal(sig_q));
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SigSpec clock_edge_pattern;
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if (clkpol) {
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clock_edge_pattern.append(State::S0);
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clock_edge_pattern.append(State::S1);
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Wire *past_q = module->addWire(NEW_ID, ff.width);
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if (!ff.is_fine) {
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module->addFf(NEW_ID, ff.sig_q, past_q);
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} else {
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clock_edge_pattern.append(State::S1);
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clock_edge_pattern.append(State::S0);
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module->addFfGate(NEW_ID, ff.sig_q, past_q);
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}
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if (!ff.val_init.is_fully_undef())
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initvals.set_init(past_q, ff.val_init);
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if (ff.has_clk) {
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SigSpec sig_d = ff.sig_d;
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if (ff.has_srst && ff.has_en && ff.ce_over_srst) {
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if (!ff.is_fine) {
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if (ff.pol_srst)
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sig_d = module->Mux(NEW_ID, sig_d, ff.val_srst, ff.sig_srst);
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else
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sig_d = module->Mux(NEW_ID, ff.val_srst, sig_d, ff.sig_srst);
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} else {
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if (ff.pol_srst)
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sig_d = module->MuxGate(NEW_ID, sig_d, ff.val_srst[0], ff.sig_srst);
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else
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sig_d = module->MuxGate(NEW_ID, ff.val_srst[0], sig_d, ff.sig_srst);
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}
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}
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if (ff.has_en) {
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if (!ff.is_fine) {
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if (ff.pol_en)
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sig_d = module->Mux(NEW_ID, ff.sig_q, sig_d, ff.sig_en);
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else
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sig_d = module->Mux(NEW_ID, sig_d, ff.sig_q, ff.sig_en);
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} else {
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if (ff.pol_en)
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sig_d = module->MuxGate(NEW_ID, ff.sig_q, sig_d, ff.sig_en);
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else
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sig_d = module->MuxGate(NEW_ID, sig_d, ff.sig_q, ff.sig_en);
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}
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}
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if (ff.has_srst && !(ff.has_en && ff.ce_over_srst)) {
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if (!ff.is_fine) {
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if (ff.pol_srst)
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sig_d = module->Mux(NEW_ID, sig_d, ff.val_srst, ff.sig_srst);
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else
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sig_d = module->Mux(NEW_ID, ff.val_srst, sig_d, ff.sig_srst);
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} else {
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if (ff.pol_srst)
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sig_d = module->MuxGate(NEW_ID, sig_d, ff.val_srst[0], ff.sig_srst);
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else
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sig_d = module->MuxGate(NEW_ID, ff.val_srst[0], sig_d, ff.sig_srst);
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}
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}
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Wire *past_clk = module->addWire(NEW_ID);
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initvals.set_init(past_clk, ff.pol_clk ? State::S1 : State::S0);
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if (!ff.is_fine)
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module->addFf(NEW_ID, ff.sig_clk, past_clk);
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else
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module->addFfGate(NEW_ID, ff.sig_clk, past_clk);
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log("Replacing %s.%s (%s): CLK=%s, D=%s, Q=%s\n",
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log_id(module), log_id(cell), log_id(cell->type),
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log_signal(ff.sig_clk), log_signal(ff.sig_d), log_signal(ff.sig_q));
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SigSpec clock_edge_pattern;
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if (ff.pol_clk) {
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clock_edge_pattern.append(State::S0);
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clock_edge_pattern.append(State::S1);
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} else {
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clock_edge_pattern.append(State::S1);
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clock_edge_pattern.append(State::S0);
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}
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SigSpec clock_edge = module->Eqx(NEW_ID, {ff.sig_clk, SigSpec(past_clk)}, clock_edge_pattern);
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Wire *past_d = module->addWire(NEW_ID, ff.width);
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if (!ff.is_fine)
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module->addFf(NEW_ID, sig_d, past_d);
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else
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module->addFfGate(NEW_ID, sig_d, past_d);
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if (!ff.val_init.is_fully_undef())
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initvals.set_init(past_d, ff.val_init);
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if (!ff.is_fine)
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qval = module->Mux(NEW_ID, past_q, past_d, clock_edge);
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else
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qval = module->MuxGate(NEW_ID, past_q, past_d, clock_edge);
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} else if (ff.has_d) {
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log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
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log_id(module), log_id(cell), log_id(cell->type),
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log_signal(ff.sig_en), log_signal(ff.sig_d), log_signal(ff.sig_q));
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SigSpec sig_en = wrap_async_control(module, ff.sig_en, ff.pol_en);
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if (!ff.is_fine)
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qval = module->Mux(NEW_ID, past_q, ff.sig_d, sig_en);
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else
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qval = module->MuxGate(NEW_ID, past_q, ff.sig_d, sig_en);
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} else {
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log("Replacing %s.%s (%s): SET=%s, CLR=%s, Q=%s\n",
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log_id(module), log_id(cell), log_id(cell->type),
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log_signal(ff.sig_set), log_signal(ff.sig_clr), log_signal(ff.sig_q));
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qval = past_q;
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}
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SigSpec clock_edge = module->Eqx(NEW_ID, {clk, SigSpec(past_clk)}, clock_edge_pattern);
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Wire *past_d = module->addWire(NEW_ID, GetSize(sig_d));
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Wire *past_q = module->addWire(NEW_ID, GetSize(sig_q));
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if (word_dff) {
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module->addFf(NEW_ID, sig_d, past_d);
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module->addFf(NEW_ID, sig_q, past_q);
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}
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else {
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module->addFfGate(NEW_ID, sig_d, past_d);
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module->addFfGate(NEW_ID, sig_q, past_q);
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}
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if (cell->type == ID($adff))
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{
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SigSpec arst = wrap_async_control(module, cell->getPort(ID::ARST), cell->parameters[ID::ARST_POLARITY].as_bool());
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SigSpec qval = module->Mux(NEW_ID, past_q, past_d, clock_edge);
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Const rstval = cell->parameters[ID::ARST_VALUE];
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module->addMux(NEW_ID, qval, rstval, arst, sig_q);
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}
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else
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if (cell->type.in(ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
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ID($_DFF_PP0_), ID($_DFF_PP1_), ID($_DFF_PN0_), ID($_DFF_PN1_)))
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{
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SigSpec arst = wrap_async_control_gate(module, cell->getPort(ID::R), cell->type[7] == 'P');
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SigSpec qval = module->MuxGate(NEW_ID, past_q, past_d, clock_edge);
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SigBit rstval = (cell->type[8] == '1');
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module->addMuxGate(NEW_ID, qval, rstval, arst, sig_q);
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}
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else
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if (cell->type == ID($dffsr))
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{
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SigSpec qval = module->Mux(NEW_ID, past_q, past_d, clock_edge);
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SigSpec setval = wrap_async_control(module, cell->getPort(ID::SET), cell->parameters[ID::SET_POLARITY].as_bool());
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SigSpec clrval = wrap_async_control(module, cell->getPort(ID::CLR), cell->parameters[ID::CLR_POLARITY].as_bool());
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clrval = module->Not(NEW_ID, clrval);
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qval = module->Or(NEW_ID, qval, setval);
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module->addAnd(NEW_ID, qval, clrval, sig_q);
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}
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else
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if (cell->type.in(ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_),
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ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_)))
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{
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SigSpec qval = module->MuxGate(NEW_ID, past_q, past_d, clock_edge);
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SigSpec setval = wrap_async_control_gate(module, cell->getPort(ID::S), cell->type[9] == 'P');
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SigSpec clrval = wrap_async_control_gate(module, cell->getPort(ID::R), cell->type[10] == 'P');
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clrval = module->NotGate(NEW_ID, clrval);
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qval = module->OrGate(NEW_ID, qval, setval);
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module->addAndGate(NEW_ID, qval, clrval, sig_q);
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}
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else if (cell->type == ID($dff))
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{
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module->addMux(NEW_ID, past_q, past_d, clock_edge, sig_q);
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}
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else
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{
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module->addMuxGate(NEW_ID, past_q, past_d, clock_edge, sig_q);
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}
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Const initval;
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bool assign_initval = false;
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for (int i = 0; i < GetSize(sig_d); i++) {
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SigBit qbit = sigmap(sig_q[i]);
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if (initbits.count(qbit)) {
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initval.bits.push_back(initbits.at(qbit));
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del_initbits.insert(qbit);
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} else
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initval.bits.push_back(State::Sx);
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if (initval.bits.back() != State::Sx)
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assign_initval = true;
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}
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if (assign_initval) {
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past_d->attributes[ID::init] = initval;
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past_q->attributes[ID::init] = initval;
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if (ff.has_sr) {
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SigSpec setval = wrap_async_control(module, ff.sig_set, ff.pol_set);
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SigSpec clrval = wrap_async_control(module, ff.sig_clr, ff.pol_clr);
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if (!ff.is_fine) {
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clrval = module->Not(NEW_ID, clrval);
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qval = module->Or(NEW_ID, qval, setval);
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module->addAnd(NEW_ID, qval, clrval, ff.sig_q);
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} else {
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clrval = module->NotGate(NEW_ID, clrval);
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qval = module->OrGate(NEW_ID, qval, setval);
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module->addAndGate(NEW_ID, qval, clrval, ff.sig_q);
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}
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} else if (ff.has_arst) {
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SigSpec arst = wrap_async_control(module, ff.sig_arst, ff.pol_arst);
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if (!ff.is_fine)
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module->addMux(NEW_ID, qval, ff.val_arst, arst, ff.sig_q);
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else
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module->addMuxGate(NEW_ID, qval, ff.val_arst[0], arst, ff.sig_q);
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} else {
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module->connect(ff.sig_q, qval);
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}
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initvals.remove_init(ff.sig_q);
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module->remove(cell);
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continue;
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}
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}
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for (auto wire : module->wires())
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if (wire->attributes.count(ID::init) > 0)
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{
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bool delete_initattr = true;
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Const initval = wire->attributes.at(ID::init);
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SigSpec initsig = sigmap(wire);
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for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
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if (del_initbits.count(initsig[i]) > 0)
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initval[i] = State::Sx;
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else if (initval[i] != State::Sx)
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delete_initattr = false;
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if (delete_initattr)
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wire->attributes.erase(ID::init);
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else
|
||||
wire->attributes.at(ID::init) = initval;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -23,7 +23,6 @@ connect -port remove6 EN 1'b1
|
|||
connect -port remove15 E 1'b1
|
||||
cd ..
|
||||
|
||||
dff2dffe -unmap
|
||||
clk2fflogic
|
||||
opt_clean
|
||||
|
||||
|
|
|
|||
|
|
@ -37,10 +37,10 @@ EOT
|
|||
|
||||
design -save orig
|
||||
flatten
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP0_ x
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ x
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ x
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ x
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ x
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ x
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x
|
||||
|
||||
|
||||
# Convert everything to ADFFs.
|
||||
|
|
|
|||
|
|
@ -37,18 +37,18 @@ EOT
|
|||
|
||||
design -save orig
|
||||
flatten
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP0_ 0 -cell $_DLATCH_P_ 0
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP0_ 1 -cell $_DLATCH_P_ 0
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP1_ 0 -cell $_DLATCH_P_ 0
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP1_ 1 -cell $_DLATCH_P_ 0
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_DLATCH_P_ 1
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_DLATCH_P_ 1
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_DLATCH_P_ 1
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_DLATCH_P_ 1
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 0
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 1
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 0
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 1
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 0 -cell $_DLATCH_P_ 0
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 1 -cell $_DLATCH_P_ 0
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 0 -cell $_DLATCH_P_ 0
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 1 -cell $_DLATCH_P_ 0
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_DLATCH_P_ 1
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_DLATCH_P_ 1
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_DLATCH_P_ 1
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_DLATCH_P_ 1
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
|
||||
|
||||
|
||||
# Convert everything to ADFFs.
|
||||
|
|
|
|||
|
|
@ -21,8 +21,8 @@ EOT
|
|||
|
||||
design -save orig
|
||||
flatten
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ x
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ x
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x
|
||||
|
||||
|
||||
# Convert everything to ADLATCHs.
|
||||
|
|
|
|||
|
|
@ -21,12 +21,12 @@ EOT
|
|||
|
||||
design -save orig
|
||||
flatten
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ 0
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ 1
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 0
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 1
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 0
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 1
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1
|
||||
|
||||
|
||||
# Convert everything to ADLATCHs.
|
||||
|
|
|
|||
|
|
@ -66,15 +66,15 @@ EOT
|
|||
|
||||
design -save orig
|
||||
flatten
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_P_ x
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP_ x
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP0_ x
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ x
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ x
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ x
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFF_PP0_ x
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFFE_PP0P_ x
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFFCE_PP0P_ x
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ x
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP_ x
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ x
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ x
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP0_ x
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_SDFFE_PP0P_ x
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_SDFFCE_PP0P_ x
|
||||
|
||||
# Convert everything to DFFs.
|
||||
|
||||
|
|
|
|||
|
|
@ -66,34 +66,34 @@ EOT
|
|||
|
||||
design -save orig
|
||||
flatten
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_P_ 0
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_P_ 1
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP_ 0
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP_ 1
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP0_ 0
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP0_ 1
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP1_ 0
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP1_ 1
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ 0
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ 1
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP1P_ 0
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP1P_ 1
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 0
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 1
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 0
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 1
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFF_PP0_ 0
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFF_PP0_ 1
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFF_PP1_ 0
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFF_PP1_ 1
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFFE_PP0P_ 0
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFFE_PP0P_ 1
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFFE_PP1P_ 0
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFFE_PP1P_ 1
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFFCE_PP0P_ 0
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFFCE_PP0P_ 1
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFFCE_PP1P_ 0
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFFCE_PP1P_ 1
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ 0
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ 1
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP_ 0
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP_ 1
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 0
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 1
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 0
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 1
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP0_ 0
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP0_ 1
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP1_ 0
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP1_ 1
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_SDFFE_PP0P_ 0
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_SDFFE_PP0P_ 1
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_SDFFE_PP1P_ 0
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_SDFFE_PP1P_ 1
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_SDFFCE_PP0P_ 0
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_SDFFCE_PP0P_ 1
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_SDFFCE_PP1P_ 0
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_SDFFCE_PP1P_ 1
|
||||
|
||||
# Convert everything to DFFs.
|
||||
|
||||
|
|
|
|||
|
|
@ -24,10 +24,10 @@ EOT
|
|||
|
||||
design -save orig
|
||||
flatten
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP0_ x -cell $_SR_PP_ x
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ x -cell $_SR_PP_ x
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ x
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ x
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ x -cell $_SR_PP_ x
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ x -cell $_SR_PP_ x
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x
|
||||
|
||||
|
||||
# Convert everything to ADFFs.
|
||||
|
|
|
|||
|
|
@ -41,18 +41,18 @@ EOT
|
|||
|
||||
design -save orig
|
||||
flatten
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP0_ 0 -cell $_SR_PP_ 0
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP0_ 1 -cell $_SR_PP_ 0
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP1_ 0 -cell $_SR_PP_ 0
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP1_ 1 -cell $_SR_PP_ 0
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_SR_PP_ 0
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_SR_PP_ 0
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_SR_PP_ 0
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_SR_PP_ 0
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 0
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 1
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 0
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 1
|
||||
#equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 0 -cell $_SR_PP_ 0
|
||||
#equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 1 -cell $_SR_PP_ 0
|
||||
#equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 0 -cell $_SR_PP_ 0
|
||||
#equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 1 -cell $_SR_PP_ 0
|
||||
#equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_SR_PP_ 0
|
||||
#equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_SR_PP_ 0
|
||||
#equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_SR_PP_ 0
|
||||
#equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_SR_PP_ 0
|
||||
#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
|
||||
#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
|
||||
#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
|
||||
#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
|
||||
|
||||
|
||||
# Convert everything to ADFFs.
|
||||
|
|
|
|||
|
|
@ -8,9 +8,9 @@ endmodule
|
|||
EOT
|
||||
|
||||
design -save orig
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_P_ x
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ x
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ x
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_P_ x
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x
|
||||
|
||||
# Convert everything to DFFs.
|
||||
|
||||
|
|
|
|||
|
|
@ -14,10 +14,10 @@ endmodule
|
|||
EOT
|
||||
|
||||
design -save orig
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP0_ 01
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP?_ 0
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 0
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 1
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 01
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP?_ 0
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
|
||||
|
||||
# Convert everything to ADFFs.
|
||||
|
||||
|
|
|
|||
|
|
@ -8,14 +8,14 @@ endmodule
|
|||
EOT
|
||||
|
||||
design -save orig
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_P_ 0
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_P_ 1
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ 0
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ 1
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 0
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 1
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 0
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 1
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_P_ 0
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_P_ 1
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1
|
||||
|
||||
# Convert everything to DFFs.
|
||||
|
||||
|
|
|
|||
|
|
@ -10,8 +10,8 @@ endmodule
|
|||
EOT
|
||||
|
||||
design -save orig
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ x -cell $_SR_PP_ x
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ x
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x -cell $_SR_PP_ x
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x
|
||||
|
||||
|
||||
# Convert everything to ADLATCHs.
|
||||
|
|
|
|||
|
|
@ -23,12 +23,12 @@ EOT
|
|||
|
||||
design -save orig
|
||||
flatten
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ 0
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ 1
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 0
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 1
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 0
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 1
|
||||
#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0
|
||||
#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1
|
||||
#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0
|
||||
#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1
|
||||
#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0
|
||||
#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1
|
||||
|
||||
|
||||
# Convert everything to ADLATCHs.
|
||||
|
|
|
|||
|
|
@ -94,7 +94,7 @@ EOT
|
|||
|
||||
design -save orig
|
||||
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_P_ x -cell $_DFFE_PP_ x -cell $_DFF_PP?_ x -cell $_DFFE_PP?P_ x -cell $_DFFSR_PPP_ x -cell $_DFFSRE_PPPP_ x -cell $_SDFF_PP?_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -cell $_DLATCH_P_ x -cell $_DLATCH_PP?_ x -cell $_DLATCHSR_PPP_ x -cell $_SR_PP_ x
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ x -cell $_DFFE_PP_ x -cell $_DFF_PP?_ x -cell $_DFFE_PP?P_ x -cell $_DFFSR_PPP_ x -cell $_DFFSRE_PPPP_ x -cell $_SDFF_PP?_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -cell $_DLATCH_P_ x -cell $_DLATCH_PP?_ x -cell $_DLATCHSR_PPP_ x -cell $_SR_PP_ x
|
||||
design -load postopt
|
||||
|
||||
select -assert-count 46 t:$_NOT_
|
||||
|
|
@ -123,7 +123,7 @@ select -assert-none t:$_DFF_P_ t:$_DFFE_PP_ t:$_DFF_PP?_ t:$_DFFE_PP?P_ t:$_DFFS
|
|||
|
||||
design -load orig
|
||||
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_N_ x -cell $_DFFE_NN_ x -cell $_DFF_NN?_ x -cell $_DFFE_NN?N_ x -cell $_DFFSR_NNN_ x -cell $_DFFSRE_NNNN_ x -cell $_SDFF_NN?_ x -cell $_SDFFE_NN?N_ x -cell $_SDFFCE_NN?N_ x -cell $_DLATCH_N_ x -cell $_DLATCH_NN?_ x -cell $_DLATCHSR_NNN_ x -cell $_SR_NN_ x
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_N_ x -cell $_DFFE_NN_ x -cell $_DFF_NN?_ x -cell $_DFFE_NN?N_ x -cell $_DFFSR_NNN_ x -cell $_DFFSRE_NNNN_ x -cell $_SDFF_NN?_ x -cell $_SDFFE_NN?N_ x -cell $_SDFFCE_NN?N_ x -cell $_DLATCH_N_ x -cell $_DLATCH_NN?_ x -cell $_DLATCHSR_NNN_ x -cell $_SR_NN_ x
|
||||
design -load postopt
|
||||
|
||||
select -assert-count 122 t:$_NOT_
|
||||
|
|
@ -166,7 +166,7 @@ endmodule
|
|||
|
||||
EOT
|
||||
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_NNNN_ x -cell $_DFFSRE_PPPP_ x
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_NNNN_ x -cell $_DFFSRE_PPPP_ x
|
||||
design -load postopt
|
||||
|
||||
select -assert-count 6 t:$_NOT_
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@ endmodule
|
|||
EOT
|
||||
|
||||
design -save orig
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP_ x -cell $_DFFE_PP?P_ x -cell $_DFFSRE_PPPP_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -mince 3
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP_ x -cell $_DFFE_PP?P_ x -cell $_DFFSRE_PPPP_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -mince 3
|
||||
design -load postopt
|
||||
|
||||
select -assert-count 4 t:$_DFFE_PP_
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@ endmodule
|
|||
EOT
|
||||
|
||||
design -save orig
|
||||
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFF_PP?_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -minsrst 3
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP?_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -minsrst 3
|
||||
design -load postopt
|
||||
|
||||
select -assert-count 5 t:$_SDFF_PP0_
|
||||
|
|
|
|||
|
|
@ -9,12 +9,12 @@ endmodule
|
|||
EOT
|
||||
|
||||
design -save orig
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SR_PP_ x
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ x
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ x
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ x
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ x
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ x
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_SR_PP_ x
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ x
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x
|
||||
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x
|
||||
|
||||
|
||||
# Convert everything to SRs.
|
||||
|
|
|
|||
|
|
@ -21,18 +21,18 @@ EOT
|
|||
|
||||
design -save orig
|
||||
flatten
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SR_PP_ 0
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SR_PP_ 1
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ 0
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ 1
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 0
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 1
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 0
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 1
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 0
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 1
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 0
|
||||
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 1
|
||||
#equiv_opt -assert -multiclock dfflegalize -cell $_SR_PP_ 0
|
||||
#equiv_opt -assert -multiclock dfflegalize -cell $_SR_PP_ 1
|
||||
#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0
|
||||
#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1
|
||||
#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0
|
||||
#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1
|
||||
#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0
|
||||
#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1
|
||||
#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
|
||||
#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
|
||||
#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
|
||||
#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
|
||||
|
||||
|
||||
# Convert everything to SRs.
|
||||
|
|
|
|||
Loading…
Reference in New Issue