mirror of https://github.com/YosysHQ/yosys.git
dfflibmap: Refactor to use dfflegalize internally.
This commit is contained in:
Marcelina Kościelnicka
parent
68babb2ae4
commit
7ed9d18907
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@ -115,7 +115,7 @@ static bool parse_pin(LibertyAst *cell, LibertyAst *attr, std::string &pin_name,
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return false;
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}
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static void find_cell(LibertyAst *ast, IdString cell_type, bool clkpol, bool has_reset, bool rstpol, bool rstval, bool prepare_mode)
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static void find_cell(LibertyAst *ast, IdString cell_type, bool clkpol, bool has_reset, bool rstpol, bool rstval)
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{
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LibertyAst *best_cell = nullptr;
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std::map<std::string, char> best_cell_ports;
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@ -222,21 +222,12 @@ static void find_cell(LibertyAst *ast, IdString cell_type, bool clkpol, bool has
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if (best_cell != nullptr) {
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log(" cell %s (%sinv, pins=%d, area=%.2f) is a direct match for cell type %s.\n",
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best_cell->args[0].c_str(), best_cell_noninv ? "non" : "", best_cell_pins, best_cell_area, cell_type.c_str());
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if (prepare_mode) {
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cell_mappings[cell_type].cell_name = cell_type;
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cell_mappings[cell_type].ports["C"] = 'C';
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if (has_reset)
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cell_mappings[cell_type].ports["R"] = 'R';
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cell_mappings[cell_type].ports["D"] = 'D';
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cell_mappings[cell_type].ports["Q"] = 'Q';
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} else {
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cell_mappings[cell_type].cell_name = RTLIL::escape_id(best_cell->args[0]);
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cell_mappings[cell_type].ports = best_cell_ports;
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}
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cell_mappings[cell_type].cell_name = RTLIL::escape_id(best_cell->args[0]);
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cell_mappings[cell_type].ports = best_cell_ports;
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}
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}
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static void find_cell_sr(LibertyAst *ast, IdString cell_type, bool clkpol, bool setpol, bool clrpol, bool prepare_mode)
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static void find_cell_sr(LibertyAst *ast, IdString cell_type, bool clkpol, bool setpol, bool clrpol)
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{
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LibertyAst *best_cell = nullptr;
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std::map<std::string, char> best_cell_ports;
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@ -339,141 +330,12 @@ static void find_cell_sr(LibertyAst *ast, IdString cell_type, bool clkpol, bool
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if (best_cell != nullptr) {
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log(" cell %s (%sinv, pins=%d, area=%.2f) is a direct match for cell type %s.\n",
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best_cell->args[0].c_str(), best_cell_noninv ? "non" : "", best_cell_pins, best_cell_area, cell_type.c_str());
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if (prepare_mode) {
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cell_mappings[cell_type].cell_name = cell_type;
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cell_mappings[cell_type].ports["C"] = 'C';
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cell_mappings[cell_type].ports["S"] = 'S';
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cell_mappings[cell_type].ports["R"] = 'R';
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cell_mappings[cell_type].ports["D"] = 'D';
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cell_mappings[cell_type].ports["Q"] = 'Q';
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} else {
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cell_mappings[cell_type].cell_name = RTLIL::escape_id(best_cell->args[0]);
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cell_mappings[cell_type].ports = best_cell_ports;
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}
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cell_mappings[cell_type].cell_name = RTLIL::escape_id(best_cell->args[0]);
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cell_mappings[cell_type].ports = best_cell_ports;
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}
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}
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static bool expand_cellmap_worker(std::string from, std::string to, std::string inv)
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{
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if (cell_mappings.count(to) > 0)
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return false;
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log(" create mapping for %s from mapping for %s.\n", to.c_str(), from.c_str());
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cell_mappings[to].cell_name = cell_mappings[from].cell_name;
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cell_mappings[to].ports = cell_mappings[from].ports;
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for (auto &it : cell_mappings[to].ports) {
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char cmp_ch = it.second;
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if ('a' <= cmp_ch && cmp_ch <= 'z')
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cmp_ch -= 'a' - 'A';
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if (inv.find(cmp_ch) == std::string::npos)
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continue;
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if ('a' <= it.second && it.second <= 'z')
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it.second -= 'a' - 'A';
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else if ('A' <= it.second && it.second <= 'Z')
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it.second += 'a' - 'A';
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}
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return true;
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}
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static bool expand_cellmap(std::string pattern, std::string inv)
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{
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std::vector<std::pair<std::string, std::string>> from_to_list;
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bool return_status = false;
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for (auto &it : cell_mappings) {
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std::string from = it.first.str(), to = it.first.str();
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if (from.size() != pattern.size())
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continue;
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for (size_t i = 0; i < from.size(); i++) {
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if (pattern[i] == '*') {
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to[i] = from[i] == 'P' ? 'N' :
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from[i] == 'N' ? 'P' :
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from[i] == '1' ? '0' :
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from[i] == '0' ? '1' : '*';
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} else
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if (pattern[i] != '?' && pattern[i] != from[i])
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goto pattern_failed;
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}
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from_to_list.push_back(std::pair<std::string, std::string>(from, to));
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pattern_failed:;
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}
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for (auto &it : from_to_list)
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return_status = return_status || expand_cellmap_worker(it.first, it.second, inv);
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return return_status;
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}
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static void map_sr_to_arst(IdString from, IdString to)
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{
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if (!cell_mappings.count(from) || cell_mappings.count(to) > 0)
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return;
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char from_clk_pol = from[8];
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char from_set_pol = from[9];
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char from_clr_pol = from[10];
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char to_clk_pol = to[6];
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char to_rst_pol = to[7];
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char to_rst_val = to[8];
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log_assert(from_clk_pol == to_clk_pol);
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log_assert(to_rst_pol == from_set_pol && to_rst_pol == from_clr_pol);
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log(" create mapping for %s from mapping for %s.\n", to.c_str(), from.c_str());
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cell_mappings[to].cell_name = cell_mappings[from].cell_name;
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cell_mappings[to].ports = cell_mappings[from].ports;
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for (auto &it : cell_mappings[to].ports)
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{
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bool is_set_pin = it.second == 'S' || it.second == 's';
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bool is_clr_pin = it.second == 'R' || it.second == 'r';
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if (!is_set_pin && !is_clr_pin)
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continue;
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if ((to_rst_val == '0' && is_set_pin) || (to_rst_val == '1' && is_clr_pin))
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{
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// this is the unused set/clr pin -- deactivate it
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if (is_set_pin)
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it.second = (from_set_pol == 'P') == (it.second == 'S') ? '0' : '1';
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else
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it.second = (from_clr_pol == 'P') == (it.second == 'R') ? '0' : '1';
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}
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else
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{
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// this is the used set/clr pin -- rename it to 'reset'
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if (it.second == 'S')
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it.second = 'R';
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if (it.second == 's')
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it.second = 'r';
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}
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}
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}
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static void map_adff_to_dff(IdString from, IdString to)
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{
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if (!cell_mappings.count(from) || cell_mappings.count(to) > 0)
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return;
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char from_clk_pol = from[6];
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char from_rst_pol = from[7];
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char to_clk_pol = to[6];
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log_assert(from_clk_pol == to_clk_pol);
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log(" create mapping for %s from mapping for %s.\n", to.c_str(), from.c_str());
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cell_mappings[to].cell_name = cell_mappings[from].cell_name;
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cell_mappings[to].ports = cell_mappings[from].ports;
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for (auto &it : cell_mappings[to].ports) {
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if (it.second == 'S' || it.second == 'R')
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it.second = from_rst_pol == 'P' ? '0' : '1';
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if (it.second == 's' || it.second == 'r')
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it.second = from_rst_pol == 'P' ? '1' : '0';
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}
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}
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static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare_mode)
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static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
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{
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log("Mapping DFF cells in module `%s':\n", module->name.c_str());
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@ -499,7 +361,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare
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module->remove(cell);
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cell_mapping &cm = cell_mappings[cell_type];
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RTLIL::Cell *new_cell = module->addCell(cell_name, prepare_mode ? cm.cell_name : cm.cell_name);
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RTLIL::Cell *new_cell = module->addCell(cell_name, cm.cell_name);
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new_cell->set_src_attribute(src);
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@ -552,7 +414,7 @@ struct DfflibmapPass : public Pass {
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void help() override
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{
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log("\n");
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log(" dfflibmap [-prepare] -liberty <file> [selection]\n");
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log(" dfflibmap [-prepare] [-map-only] [-info] -liberty <file> [selection]\n");
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log("\n");
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log("Map internal flip-flop cells to the flip-flop cells in the technology\n");
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log("library specified in the given liberty file.\n");
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@ -562,15 +424,27 @@ struct DfflibmapPass : public Pass {
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log("\n");
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log("When called with -prepare, this command will convert the internal FF cells\n");
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log("to the internal cell types that best match the cells found in the given\n");
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log("liberty file.\n");
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log("liberty file, but won't actually map them to the target cells.\n");
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log("\n");
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log("When called with -map-only, this command will only map internal cell\n");
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log("types that are already of exactly the right type to match the target\n");
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log("cells, leaving remaining internal cells untouched.\n");
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log("\n");
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log("When called with -info, this command will only print the target cell\n");
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log("list, along with their associated internal cell types, and the arguments");
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log("that would be passed to the dfflegalize pass. The design will not be\n");
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log("changed.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).\n");
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log_push();
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std::string liberty_file;
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bool prepare_mode = false;
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bool map_only_mode = false;
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bool info_mode = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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@ -585,10 +459,28 @@ struct DfflibmapPass : public Pass {
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prepare_mode = true;
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continue;
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}
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if (arg == "-map-only") {
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map_only_mode = true;
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continue;
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}
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if (arg == "-info") {
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info_mode = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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int modes = 0;
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if (prepare_mode)
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modes++;
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if (map_only_mode)
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modes++;
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if (info_mode)
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modes++;
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if (modes > 1)
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log_cmd_error("Only one of -prepare, -map-only, or -info options should be given!\n");
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if (liberty_file.empty())
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log_cmd_error("Missing `-liberty liberty_file' option!\n");
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@ -599,74 +491,49 @@ struct DfflibmapPass : public Pass {
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LibertyParser libparser(f);
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f.close();
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find_cell(libparser.ast, ID($_DFF_N_), false, false, false, false, prepare_mode);
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find_cell(libparser.ast, ID($_DFF_P_), true, false, false, false, prepare_mode);
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find_cell(libparser.ast, ID($_DFF_N_), false, false, false, false);
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find_cell(libparser.ast, ID($_DFF_P_), true, false, false, false);
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find_cell(libparser.ast, ID($_DFF_NN0_), false, true, false, false, prepare_mode);
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find_cell(libparser.ast, ID($_DFF_NN1_), false, true, false, true, prepare_mode);
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find_cell(libparser.ast, ID($_DFF_NP0_), false, true, true, false, prepare_mode);
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find_cell(libparser.ast, ID($_DFF_NP1_), false, true, true, true, prepare_mode);
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find_cell(libparser.ast, ID($_DFF_PN0_), true, true, false, false, prepare_mode);
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find_cell(libparser.ast, ID($_DFF_PN1_), true, true, false, true, prepare_mode);
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find_cell(libparser.ast, ID($_DFF_PP0_), true, true, true, false, prepare_mode);
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find_cell(libparser.ast, ID($_DFF_PP1_), true, true, true, true, prepare_mode);
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find_cell(libparser.ast, ID($_DFF_NN0_), false, true, false, false);
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find_cell(libparser.ast, ID($_DFF_NN1_), false, true, false, true);
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find_cell(libparser.ast, ID($_DFF_NP0_), false, true, true, false);
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find_cell(libparser.ast, ID($_DFF_NP1_), false, true, true, true);
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find_cell(libparser.ast, ID($_DFF_PN0_), true, true, false, false);
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find_cell(libparser.ast, ID($_DFF_PN1_), true, true, false, true);
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find_cell(libparser.ast, ID($_DFF_PP0_), true, true, true, false);
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find_cell(libparser.ast, ID($_DFF_PP1_), true, true, true, true);
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find_cell_sr(libparser.ast, ID($_DFFSR_NNN_), false, false, false, prepare_mode);
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find_cell_sr(libparser.ast, ID($_DFFSR_NNP_), false, false, true, prepare_mode);
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find_cell_sr(libparser.ast, ID($_DFFSR_NPN_), false, true, false, prepare_mode);
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find_cell_sr(libparser.ast, ID($_DFFSR_NPP_), false, true, true, prepare_mode);
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find_cell_sr(libparser.ast, ID($_DFFSR_PNN_), true, false, false, prepare_mode);
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find_cell_sr(libparser.ast, ID($_DFFSR_PNP_), true, false, true, prepare_mode);
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find_cell_sr(libparser.ast, ID($_DFFSR_PPN_), true, true, false, prepare_mode);
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find_cell_sr(libparser.ast, ID($_DFFSR_PPP_), true, true, true, prepare_mode);
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// try to implement as many cells as possible just by inverting
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// the SET and RESET pins. If necessary, implement cell types
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// by inverting both D and Q. Only invert clock pins if there
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// is no other way of implementing the cell.
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while (1)
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{
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if (expand_cellmap("$_DFF_?*?_", "R") ||
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expand_cellmap("$_DFFSR_?*?_", "S") ||
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expand_cellmap("$_DFFSR_??*_", "R"))
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continue;
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if (expand_cellmap("$_DFF_??*_", "DQ"))
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continue;
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if (expand_cellmap("$_DFF_*_", "C") ||
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expand_cellmap("$_DFF_*??_", "C") ||
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expand_cellmap("$_DFFSR_*??_", "C"))
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continue;
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break;
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}
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map_sr_to_arst(ID($_DFFSR_NNN_), ID($_DFF_NN0_));
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map_sr_to_arst(ID($_DFFSR_NNN_), ID($_DFF_NN1_));
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map_sr_to_arst(ID($_DFFSR_NPP_), ID($_DFF_NP0_));
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map_sr_to_arst(ID($_DFFSR_NPP_), ID($_DFF_NP1_));
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map_sr_to_arst(ID($_DFFSR_PNN_), ID($_DFF_PN0_));
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map_sr_to_arst(ID($_DFFSR_PNN_), ID($_DFF_PN1_));
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map_sr_to_arst(ID($_DFFSR_PPP_), ID($_DFF_PP0_));
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map_sr_to_arst(ID($_DFFSR_PPP_), ID($_DFF_PP1_));
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map_adff_to_dff(ID($_DFF_NN0_), ID($_DFF_N_));
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map_adff_to_dff(ID($_DFF_NN1_), ID($_DFF_N_));
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map_adff_to_dff(ID($_DFF_NP0_), ID($_DFF_N_));
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map_adff_to_dff(ID($_DFF_NP1_), ID($_DFF_N_));
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map_adff_to_dff(ID($_DFF_PN0_), ID($_DFF_P_));
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map_adff_to_dff(ID($_DFF_PN1_), ID($_DFF_P_));
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map_adff_to_dff(ID($_DFF_PP0_), ID($_DFF_P_));
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map_adff_to_dff(ID($_DFF_PP1_), ID($_DFF_P_));
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find_cell_sr(libparser.ast, ID($_DFFSR_NNN_), false, false, false);
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find_cell_sr(libparser.ast, ID($_DFFSR_NNP_), false, false, true);
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find_cell_sr(libparser.ast, ID($_DFFSR_NPN_), false, true, false);
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find_cell_sr(libparser.ast, ID($_DFFSR_NPP_), false, true, true);
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find_cell_sr(libparser.ast, ID($_DFFSR_PNN_), true, false, false);
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find_cell_sr(libparser.ast, ID($_DFFSR_PNP_), true, false, true);
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find_cell_sr(libparser.ast, ID($_DFFSR_PPN_), true, true, false);
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find_cell_sr(libparser.ast, ID($_DFFSR_PPP_), true, true, true);
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log(" final dff cell mappings:\n");
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logmap_all();
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for (auto module : design->selected_modules())
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if (!module->get_blackbox_attribute())
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dfflibmap(design, module, prepare_mode);
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if (!map_only_mode) {
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std::string dfflegalize_cmd = "dfflegalize";
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for (auto it : cell_mappings)
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dfflegalize_cmd += stringf(" -cell %s 01", it.first.c_str());
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dfflegalize_cmd += " t:$_DFF* t:$_SDFF*";
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if (info_mode) {
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log("dfflegalize command line: %s\n", dfflegalize_cmd.c_str());
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} else {
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Pass::call(design, dfflegalize_cmd);
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}
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}
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if (!prepare_mode && !info_mode) {
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for (auto module : design->selected_modules())
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if (!module->get_blackbox_attribute())
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dfflibmap(design, module);
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}
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log_pop();
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||||
cell_mappings.clear();
|
||||
}
|
||||
} DfflibmapPass;
|
||||
|
|
|
|||
|
|
@ -5,6 +5,6 @@ for x in *.lib; do
|
|||
echo "Running $x.."
|
||||
echo "read_verilog small.v" > test.ys
|
||||
echo "synth -top small" >> test.ys
|
||||
echo "dfflibmap -liberty ${x}" >> test.ys
|
||||
echo "dfflibmap -info -liberty ${x}" >> test.ys
|
||||
../../yosys -ql ${x%.lib}.log -s test.ys
|
||||
done
|
||||
|
|
|
|||
|
|
@ -0,0 +1,22 @@
|
|||
module dffn(input CLK, D, output reg Q, output QN);
|
||||
|
||||
always @(negedge CLK)
|
||||
Q <= D;
|
||||
|
||||
assign QN = ~Q;
|
||||
|
||||
endmodule
|
||||
|
||||
module dffsr(input CLK, D, CLEAR, PRESET, output reg Q, output QN);
|
||||
|
||||
always @(posedge CLK, posedge CLEAR, posedge PRESET)
|
||||
if (CLEAR)
|
||||
Q <= 0;
|
||||
else if (PRESET)
|
||||
Q <= 1;
|
||||
else
|
||||
Q <= D;
|
||||
|
||||
assign QN = ~Q;
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
library(test) {
|
||||
/* D-type flip-flop with asynchronous reset and preset */
|
||||
cell (dffn) {
|
||||
area : 6;
|
||||
ff("IQ", "IQN") {
|
||||
next_state : "D";
|
||||
clocked_on : "!CLK";
|
||||
}
|
||||
pin(D) {
|
||||
direction : input;
|
||||
}
|
||||
pin(CLK) {
|
||||
direction : input;
|
||||
}
|
||||
pin(Q) {
|
||||
direction: output;
|
||||
function : "IQ";
|
||||
}
|
||||
pin(QN) {
|
||||
direction: output;
|
||||
function : "IQN";
|
||||
}
|
||||
}
|
||||
cell (dffsr) {
|
||||
area : 6;
|
||||
ff("IQ", "IQN") {
|
||||
next_state : "D";
|
||||
clocked_on : "CLK";
|
||||
clear : "CLEAR";
|
||||
preset : "PRESET";
|
||||
clear_preset_var1 : L;
|
||||
clear_preset_var2 : L;
|
||||
}
|
||||
pin(D) {
|
||||
direction : input;
|
||||
}
|
||||
pin(CLK) {
|
||||
direction : input;
|
||||
}
|
||||
pin(CLEAR) {
|
||||
direction : input;
|
||||
}
|
||||
pin(PRESET) {
|
||||
direction : input;
|
||||
}
|
||||
pin(Q) {
|
||||
direction: output;
|
||||
function : "IQ";
|
||||
}
|
||||
pin(QN) {
|
||||
direction: output;
|
||||
function : "IQN";
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
read_verilog -icells <<EOT
|
||||
|
||||
module top(input C, D, S, R, output [9:0] Q);
|
||||
|
||||
$_DFF_P_ ff0 (.C(C), .D(D), .Q(Q[0]));
|
||||
$_DFF_PP0_ ff1 (.C(C), .D(D), .R(R), .Q(Q[1]));
|
||||
$_DFF_PP1_ ff2 (.C(C), .D(D), .R(R), .Q(Q[2]));
|
||||
$_DFFSR_PPP_ ff3 (.C(C), .D(D), .R(R), .S(S), .Q(Q[3]));
|
||||
$_DFFSR_NNN_ ff4 (.C(C), .D(D), .R(R), .S(S), .Q(Q[4]));
|
||||
|
||||
assign Q[9:5] = ~Q[4:0];
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
simplemap
|
||||
|
||||
design -save orig
|
||||
|
||||
#equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -liberty dfflibmap.lib
|
||||
#equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -prepare -liberty dfflibmap.lib
|
||||
dfflibmap -prepare -liberty dfflibmap.lib
|
||||
equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -map-only -liberty dfflibmap.lib
|
||||
|
||||
design -load orig
|
||||
dfflibmap -liberty dfflibmap.lib
|
||||
clean
|
||||
|
||||
select -assert-count 4 t:$_NOT_
|
||||
select -assert-count 1 t:dffn
|
||||
select -assert-count 4 t:dffsr
|
||||
select -assert-none t:dffn t:dffsr t:$_NOT_ %% %n t:* %i
|
||||
|
||||
design -load orig
|
||||
dfflibmap -prepare -liberty dfflibmap.lib
|
||||
|
||||
select -assert-count 9 t:$_NOT_
|
||||
select -assert-count 1 t:$_DFF_N_
|
||||
select -assert-count 4 t:$_DFFSR_PPP_
|
||||
select -assert-none t:$_DFF_N_ t:$_DFFSR_PPP_ t:$_NOT_ %% %n t:* %i
|
||||
|
||||
design -load orig
|
||||
dfflibmap -map-only -liberty dfflibmap.lib
|
||||
|
||||
select -assert-count 5 t:$_NOT_
|
||||
select -assert-count 0 t:dffn
|
||||
select -assert-count 1 t:dffsr
|
||||
|
||||
design -load orig
|
||||
dfflibmap -prepare -liberty dfflibmap.lib
|
||||
dfflibmap -map-only -liberty dfflibmap.lib
|
||||
clean
|
||||
|
||||
select -assert-count 4 t:$_NOT_
|
||||
select -assert-count 1 t:dffn
|
||||
select -assert-count 4 t:dffsr
|
||||
select -assert-none t:dffn t:dffsr t:$_NOT_ %% %n t:* %i
|
||||
Loading…
Reference in New Issue