mirror of https://github.com/YosysHQ/yosys.git
Start work on memory init
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@ -1229,6 +1229,12 @@ struct SimWorker : SimShared
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int prev_cycle = 0;
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int curr_cycle = 0;
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std::vector<std::string> parts;
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size_t len = 0;
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dict<IdString, Mem*> mem_dict;
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for (auto &mem : top->memories) {
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mem.narrow();
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mem_dict[mem.memid] = &mem;
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}
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while (!f.eof())
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{
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std::string line;
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@ -1272,17 +1278,36 @@ struct SimWorker : SimShared
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break;
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default: // set state or inputs
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parts = split(line, " ");
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if (parts.size()!=3)
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len = parts.size();
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if (len<3 || len>4)
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log_error("Invalid set state line content.\n");
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RTLIL::IdString escaped_s = RTLIL::escape_id(signal_name(parts[2]));
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Wire *w = topmod->wire(escaped_s);
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if (!w)
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log_error("Wire %s not present in module %s\n",log_id(escaped_s),log_id(topmod));
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if ((int)parts[1].size() != w->width)
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log_error("Size of wire %s is different than provided data.\n", log_signal(w));
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top->set_state(w, Const::from_string(parts[1]));
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RTLIL::IdString escaped_s = RTLIL::escape_id(signal_name(parts[len-1]));
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if (len==3) {
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Wire *w = topmod->wire(escaped_s);
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if (!w)
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log_warning("Wire %s not present in module %s\n",log_id(escaped_s),log_id(topmod));
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if (w && (int)parts[1].size() != w->width)
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log_error("Size of wire %s is different than provided data.\n", log_signal(w));
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if (w)
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top->set_state(w, Const::from_string(parts[1]));
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} else {
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Cell *c = topmod->cell(escaped_s);
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if (!c)
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log_error("Cell %s not present in module %s\n",log_id(escaped_s),log_id(topmod));
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if (!c->is_mem_cell())
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log_error("Cell %s is not memory cell in module %s\n",log_id(escaped_s),log_id(topmod));
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Mem *mem = mem_dict[c->parameters.at(ID::MEMID).decode_string()];
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mem->clear_inits();
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MemInit minit;
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minit.addr = Const::from_string(parts[1].substr(1,parts[1].size()-2));
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minit.data = Const::from_string(parts[2]);
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log("[%s] = %s\n",log_signal(minit.addr), log_signal(minit.data));
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minit.en = Const(State::S1, mem->width);
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mem->inits.push_back(minit);
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mem->emit();
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}
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break;
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}
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}
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