riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

opt_mem: Add reset/init value support.

This commit is contained in:
Marcelina Kościelnicka 2021-05-25 18:49:17 +02:00
parent 24b880b2de
commit e6b078d156
1 changed files with 12 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
passes/opt/opt_mem.cc
View File

@ -51,6 +51,8 @@ struct OptMemPass : public Pass {
int total_count = 0;
for (auto module : design->selected_modules()) {
SigMap sigmap(module);
FfInitVals initvals(&sigmap, module);
for (auto &mem : Mem::get_selected_memories(module)) {
bool changed = false;
for (auto &port : mem.wr_ports) {
@ -65,6 +67,16 @@ struct OptMemPass : public Pass {
}
if (mem.wr_ports.empty() && mem.inits.empty()) {
// The whole memory array will contain
// only State::Sx, but the embedded read
// registers could have reset or init values.
// They will probably be optimized away by
// opt_dff later.
for (int i = 0; i < GetSize(mem.rd_ports); i++) {
mem.extract_rdff(i, &initvals);
auto &port = mem.rd_ports[i];
module->connect(port.data, Const(State::Sx, GetSize(port.data)));
}
mem.remove();
total_count++;
}