riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Use edges when explicit

This commit is contained in:
Miodrag Milanovic 2022-01-31 09:38:25 +01:00
parent cbadfa0268
commit a6959d30df
1 changed files with 5 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
passes/sat/sim.cc
View File

@ -74,6 +74,7 @@ struct SimShared
double start_time = 0;
double stop_time = -1;
SimulationMode sim_mode = SimulationMode::cmp;
bool cycles_set = false;
};
void zinit(State &v)
@ -1016,7 +1017,9 @@ struct SimWorker : SimShared
log_error("Stop time is before start time\n");
}
auto edges = fst->getAllEdges(fst_clock, startCount, stopCount);
if (cycles_set && ((size_t)(numcycles *2) < edges.size()))
edges.erase(edges.begin() + (numcycles*2), edges.end());
if ((startCount == stopCount) && writeback) {
log("Update initial state with values from %zu\n",startCount);
if (edges.empty())
@ -1143,6 +1146,7 @@ struct SimPass : public Pass {
}
if (args[argidx] == "-n" && argidx+1 < args.size()) {
numcycles = atoi(args[++argidx].c_str());
worker.cycles_set = true;
continue;
}
if (args[argidx] == "-rstlen" && argidx+1 < args.size()) {