mirror of https://github.com/YosysHQ/yosys.git
Fix for last clock edge data
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ca261d3c28
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@ -184,6 +184,7 @@ void FstData::reconstructAllAtTimes(std::vector<fstHandle> &signal, uint64_t sta
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fstReaderSetUnlimitedTimeRange(ctx);
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fstReaderSetFacProcessMaskAll(ctx);
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fstReaderIterBlocks2(ctx, reconstruct_clb_attimes, reconstruct_clb_varlen_attimes, this, nullptr);
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past_data = last_data;
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callback(last_time);
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if (last_time!=end_time)
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callback(end_time);
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@ -1125,7 +1125,7 @@ struct SimWorker : SimShared
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try {
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fst->reconstructAllAtTimes(fst_clock, startCount, stopCount, [&](uint64_t time) {
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log("Co-simulating %s %d [%lu%s].\n", (all_samples ? "sample" : "cycle"), cycle, (unsigned long)time, fst->getTimescaleString());
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bool did_something = time < stopCount; // FIXME
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bool did_something = false;
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for(auto &item : inputs) {
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std::string v = fst->valueOf(item.second);
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did_something |= top->set_state(item.first, Const::from_string(v));
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@ -1138,8 +1138,6 @@ struct SimWorker : SimShared
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}
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if (did_something)
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update();
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else
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log("nothing to update.\n");
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write_output_step(time);
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bool status = top->checkSignals();
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