mirror of https://github.com/YosysHQ/yosys.git
added stimulus mode and param check
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8ba2000a50
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820b2fdd65
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@ -29,6 +29,7 @@ USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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enum class SimulationMode {
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sim,
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cmp,
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gold,
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gate,
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@ -73,7 +74,7 @@ struct SimShared
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FstData *fst = nullptr;
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double start_time = 0;
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double stop_time = -1;
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SimulationMode sim_mode = SimulationMode::cmp;
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SimulationMode sim_mode = SimulationMode::sim;
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bool cycles_set = false;
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};
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@ -746,7 +747,9 @@ struct SimInstance
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Const sim_val = get_state(item.first);
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if (sim_val.size()!=fst_val.size())
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log_error("Signal '%s' size is different in gold and gate.\n", log_id(item.first));
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if (shared->sim_mode == SimulationMode::gate && !fst_val.is_fully_def()) { // FST data contains X
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if (shared->sim_mode == SimulationMode::sim) {
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// No checks performed when using stimulus
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} else if (shared->sim_mode == SimulationMode::gate && !fst_val.is_fully_def()) { // FST data contains X
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for(int i=0;i<fst_val.size();i++) {
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if (fst_val[i]!=State::Sx && fst_val[i]!=sim_val[i]) {
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log_warning("Signal '%s' in file '%s' in simulation '%s'\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
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@ -1109,10 +1112,10 @@ struct SimPass : public Pass {
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log(" include the specified timescale declaration in the vcd\n");
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log("\n");
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log(" -n <integer>\n");
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log(" number of cycles to simulate (default: 20)\n");
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log(" number of clock cycles to simulate (default: 20)\n");
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log("\n");
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log(" -a\n");
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log(" include all nets in VCD output, not just those with public names\n");
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log(" use all nets in VCD/FST operations, not just those with public names\n");
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log("\n");
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log(" -w\n");
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log(" writeback mode: use final simulation state as new init state\n");
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@ -1123,14 +1126,20 @@ struct SimPass : public Pass {
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log(" -scope\n");
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log(" scope of simulation top model\n");
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log("\n");
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log(" -at <time>\n");
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log(" sets start and stop time\n");
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log("\n");
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log(" -start <time>\n");
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log(" start co-simulation in arbitary time (default 0)\n");
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log("\n");
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log(" -stop <time>\n");
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log(" stop co-simulation in arbitary time (default END)\n");
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log("\n");
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log(" -sim\n");
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log(" simulation with stimulus from FST (default)\n");
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log("\n");
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log(" -sim-cmp\n");
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log(" co-simulation expect exact match (default)\n");
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log(" co-simulation expect exact match\n");
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log("\n");
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log(" -sim-gold\n");
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log(" co-simulation, x in simulation can match any value in FST\n");
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@ -1146,6 +1155,7 @@ struct SimPass : public Pass {
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{
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SimWorker worker;
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int numcycles = 20;
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bool start_set = false, stop_set = false, at_set = false;
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log_header(design, "Executing SIM pass (simulate the circuit).\n");
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@ -1220,10 +1230,22 @@ struct SimPass : public Pass {
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}
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if (args[argidx] == "-start" && argidx+1 < args.size()) {
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worker.start_time = stringToTime(args[++argidx]);
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start_set = true;
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continue;
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}
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if (args[argidx] == "-stop" && argidx+1 < args.size()) {
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worker.stop_time = stringToTime(args[++argidx]);
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stop_set = true;
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continue;
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}
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if (args[argidx] == "-at" && argidx+1 < args.size()) {
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worker.start_time = stringToTime(args[++argidx]);
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worker.stop_time = worker.start_time;
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at_set = true;
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continue;
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}
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if (args[argidx] == "-sim") {
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worker.sim_mode = SimulationMode::sim;
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continue;
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}
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if (args[argidx] == "-sim-cmp") {
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@ -1241,6 +1263,10 @@ struct SimPass : public Pass {
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break;
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}
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extra_args(args, argidx, design);
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if (at_set && (start_set || stop_set || worker.cycles_set))
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log_error("'at' option can only be defined separate of 'start','stop' and 'n'\n");
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if (stop_set && worker.cycles_set)
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log_error("'stop' and 'n' can only be used exclusively'\n");
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Module *top_mod = nullptr;
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