riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

mem/extract_rdff: Fix "no FF made" edge case. 

When converting a sync transparent read port with const address to async
read port, nothing at all needs to be done other than clk_enable change,
and thus we have no FF cell to return.  Handle this case correctly in
the helper and in its users.
This commit is contained in:
Marcelina Kościelnicka 2021-05-25 22:39:50 +02:00
parent 18806f1ef6
commit d99fce3bc7
2 changed files with 9 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
kernel/mem.cc
View File

@ -579,7 +579,8 @@ Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) {
if (port.addr[i].wire)
width++;
if (width) {
if (width)
{
SigSpec sig_q = module->addWire(stringf("$%s$rdreg[%d]$q", memid.c_str(), idx), width);
SigSpec sig_d;
@ -591,6 +592,8 @@ Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) {
}
c = module->addDff(stringf("$%s$rdreg[%d]", memid.c_str(), idx), port.clk, sig_d, sig_q, port.clk_polarity);
} else {
c = nullptr;
}
}
else

7
passes/memory/memory_nordff.cc
View File

@ -57,9 +57,12 @@ struct MemoryNordffPass : public Pass {
for (auto &mem : Mem::get_selected_memories(module))
{
bool changed = false;
for (int i = 0; i < GetSize(mem.rd_ports); i++)
if (mem.extract_rdff(i, &initvals))
for (int i = 0; i < GetSize(mem.rd_ports); i++) {
if (mem.rd_ports[i].clk_enable) {
mem.extract_rdff(i, &initvals);
changed = true;
}
}
if (changed)
mem.emit();