mirror of https://github.com/YosysHQ/yosys.git
flatten: Keep sigmap around between flatten_cell invocations.
Fixes #3064.
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@ -77,7 +77,7 @@ struct FlattenWorker
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{
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bool ignore_wb = false;
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void flatten_cell(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl, std::vector<RTLIL::Cell*> &new_cells)
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void flatten_cell(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl, SigMap &sigmap, std::vector<RTLIL::Cell*> &new_cells)
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{
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// Copy the contents of the flattened cell
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@ -165,7 +165,6 @@ struct FlattenWorker
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for (auto bit : tpl_conn.first)
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tpl_driven.insert(bit);
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SigMap sigmap(module);
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for (auto &port_it : cell->connections())
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{
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IdString port_name = port_it.first;
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@ -218,6 +217,7 @@ struct FlattenWorker
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log_id(module), log_id(cell), log_id(port_it.first), log_signal(new_conn.first), log_signal(new_conn.second));
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module->connect(new_conn);
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sigmap.add(new_conn.first, new_conn.second);
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}
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module->remove(cell);
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@ -228,6 +228,7 @@ struct FlattenWorker
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if (!design->selected(module) || module->get_blackbox_attribute(ignore_wb))
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return;
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SigMap sigmap(module);
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std::vector<RTLIL::Cell*> worklist = module->selected_cells();
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while (!worklist.empty())
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{
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@ -251,7 +252,7 @@ struct FlattenWorker
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// If a design is fully selected and has a top module defined, topological sorting ensures that all cells
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// added during flattening are black boxes, and flattening is finished in one pass. However, when flattening
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// individual modules, this isn't the case, and the newly added cells might have to be flattened further.
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flatten_cell(design, module, cell, tpl, worklist);
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flatten_cell(design, module, cell, tpl, sigmap, worklist);
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}
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}
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};
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