mirror of https://github.com/YosysHQ/yosys.git
opt_share: Refactor, fix some bugs.
Fixes #2334. Fixes #2335. Fixes #2336.
This commit is contained in:
Marcelina Kościelnicka
parent
9a4f420b4b
commit
2b777bbda8
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@ -30,8 +30,6 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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SigMap assign_map;
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struct OpMuxConn {
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RTLIL::SigSpec sig;
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RTLIL::Cell *mux;
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@ -157,9 +155,9 @@ bool decode_port_signed(RTLIL::Cell *cell, RTLIL::IdString port_name)
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return false;
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}
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ExtSigSpec decode_port(RTLIL::Cell *cell, RTLIL::IdString port_name, SigMap *sigmap)
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ExtSigSpec decode_port(RTLIL::Cell *cell, RTLIL::IdString port_name, const SigMap &sigmap)
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{
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auto sig = (*sigmap)(cell->getPort(port_name));
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auto sig = sigmap(cell->getPort(port_name));
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RTLIL::SigSpec sign = decode_port_sign(cell, port_name);
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RTLIL::IdString semantics = decode_port_semantics(cell, port_name);
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@ -169,7 +167,7 @@ ExtSigSpec decode_port(RTLIL::Cell *cell, RTLIL::IdString port_name, SigMap *sig
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return ExtSigSpec(sig, sign, is_signed, semantics);
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}
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void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<OpMuxConn> &ports, const ExtSigSpec &operand)
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void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<OpMuxConn> &ports, const ExtSigSpec &operand, const SigMap &sigmap)
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{
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std::vector<ExtSigSpec> muxed_operands;
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int max_width = 0;
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@ -177,10 +175,10 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
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auto op = p.op;
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RTLIL::IdString muxed_port_name = ID::A;
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if (decode_port(op, ID::A, &assign_map) == operand)
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if (decode_port(op, ID::A, sigmap) == operand)
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muxed_port_name = ID::B;
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auto operand = decode_port(op, muxed_port_name, &assign_map);
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auto operand = decode_port(op, muxed_port_name, sigmap);
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if (operand.sig.size() > max_width)
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max_width = operand.sig.size();
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@ -190,11 +188,13 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
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auto shared_op = ports[0].op;
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if (std::any_of(muxed_operands.begin(), muxed_operands.end(), [&](ExtSigSpec &op) { return op.sign != muxed_operands[0].sign; }))
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max_width = std::max(max_width, shared_op->getParam(ID::Y_WIDTH).as_int());
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max_width = std::max(max_width, shared_op->getParam(ID::Y_WIDTH).as_int());
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for (auto &operand : muxed_operands)
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for (auto &operand : muxed_operands) {
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operand.sig.extend_u0(max_width, operand.is_signed);
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if (operand.sign != muxed_operands[0].sign)
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operand = ExtSigSpec(module->Neg(NEW_ID, operand.sig, operand.is_signed));
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}
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for (const auto& p : ports) {
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auto op = p.op;
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@ -203,61 +203,58 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
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module->remove(op);
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}
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for (auto &muxed_op : muxed_operands)
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if (muxed_op.sign != muxed_operands[0].sign)
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muxed_op = ExtSigSpec(module->Neg(NEW_ID, muxed_op.sig, muxed_op.is_signed));
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RTLIL::SigSpec mux_y = mux->getPort(ID::Y);
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RTLIL::SigSpec mux_a = mux->getPort(ID::A);
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RTLIL::SigSpec mux_b = mux->getPort(ID::B);
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RTLIL::SigSpec mux_s = mux->getPort(ID::S);
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int conn_width = ports[0].sig.size();
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int conn_mux_offset = ports[0].mux_port_offset;
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int conn_op_offset = ports[0].op_outsig_offset;
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RTLIL::SigSpec shared_pmux_a = RTLIL::Const(RTLIL::State::Sx, max_width);
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RTLIL::SigSpec shared_pmux_b;
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RTLIL::SigSpec shared_pmux_s;
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int conn_width = ports[0].sig.size();
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int conn_offset = ports[0].mux_port_offset;
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// Make a new wire to avoid false equivalence with whatever the former shared output was connected to.
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Wire *new_out = module->addWire(NEW_ID, conn_op_offset + conn_width);
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SigSpec new_sig_out = SigSpec(new_out, conn_op_offset, conn_width);
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shared_op->setPort(ID::Y, shared_op->getPort(ID::Y).extract(0, conn_width));
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if (mux->type == ID($pmux)) {
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shared_pmux_s = RTLIL::SigSpec();
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for (const auto &p : ports) {
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for (int i = 0; i < GetSize(ports); i++) {
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auto &p = ports[i];
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auto &op = muxed_operands[i];
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if (p.mux_port_id == GetSize(mux_s)) {
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shared_pmux_a = op.sig;
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mux_a.replace(conn_mux_offset, new_sig_out);
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} else {
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shared_pmux_s.append(mux_s[p.mux_port_id]);
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mux_b.replace(p.mux_port_id * mux_a.size() + conn_offset, shared_op->getPort(ID::Y));
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shared_pmux_b.append(op.sig);
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mux_b.replace(p.mux_port_id * mux_a.size() + conn_mux_offset, new_sig_out);
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}
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} else {
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shared_pmux_s = RTLIL::SigSpec{mux_s, module->Not(NEW_ID, mux_s)};
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mux_a.replace(conn_offset, shared_op->getPort(ID::Y));
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mux_b.replace(conn_offset, shared_op->getPort(ID::Y));
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}
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mux->setPort(ID::A, mux_a);
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mux->setPort(ID::B, mux_b);
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mux->setPort(ID::Y, mux_y);
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mux->setPort(ID::S, mux_s);
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for (const auto &op : muxed_operands)
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shared_pmux_b.append(op.sig);
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auto mux_to_oper = module->Pmux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s);
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SigSpec mux_to_oper;
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if (GetSize(shared_pmux_s) == 1) {
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mux_to_oper = module->Mux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s);
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} else {
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mux_to_oper = module->Pmux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s);
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}
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if (shared_op->type.in(ID($alu))) {
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RTLIL::SigSpec alu_x = shared_op->getPort(ID::X);
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RTLIL::SigSpec alu_co = shared_op->getPort(ID::CO);
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shared_op->setPort(ID::X, alu_x.extract(0, conn_width));
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shared_op->setPort(ID::CO, alu_co.extract(0, conn_width));
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shared_op->setPort(ID::X, module->addWire(NEW_ID, GetSize(new_sig_out)));
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shared_op->setPort(ID::CO, module->addWire(NEW_ID, GetSize(new_sig_out)));
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}
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bool is_fine = shared_op->type.in(FINE_BITWISE_OPS);
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shared_op->setPort(ID::Y, new_out);
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if (!is_fine)
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shared_op->setParam(ID::Y_WIDTH, conn_width);
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shared_op->setParam(ID::Y_WIDTH, GetSize(new_out));
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if (decode_port(shared_op, ID::A, &assign_map) == operand) {
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if (decode_port(shared_op, ID::A, sigmap) == operand) {
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shared_op->setPort(ID::B, mux_to_oper);
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if (!is_fine)
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shared_op->setParam(ID::B_WIDTH, max_width);
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@ -275,17 +272,7 @@ typedef struct {
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} merged_op_t;
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template <typename T> void remove_val(std::vector<T> &v, const std::vector<T> &vals)
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{
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auto val_iter = vals.rbegin();
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for (auto i = v.rbegin(); i != v.rend(); ++i)
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if ((val_iter != vals.rend()) && (*i == *val_iter)) {
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v.erase(i.base() - 1);
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++val_iter;
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}
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}
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void check_muxed_operands(std::vector<const OpMuxConn *> &ports, const ExtSigSpec &shared_operand)
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void check_muxed_operands(std::vector<const OpMuxConn *> &ports, const ExtSigSpec &shared_operand, const SigMap &sigmap)
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{
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auto it = ports.begin();
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ExtSigSpec seed;
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@ -295,11 +282,11 @@ void check_muxed_operands(std::vector<const OpMuxConn *> &ports, const ExtSigSpe
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auto op = p->op;
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RTLIL::IdString muxed_port_name = ID::A;
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if (decode_port(op, ID::A, &assign_map) == shared_operand) {
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if (decode_port(op, ID::A, sigmap) == shared_operand) {
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muxed_port_name = ID::B;
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}
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auto operand = decode_port(op, muxed_port_name, &assign_map);
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auto operand = decode_port(op, muxed_port_name, sigmap);
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if (seed.empty())
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seed = operand;
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@ -312,7 +299,7 @@ void check_muxed_operands(std::vector<const OpMuxConn *> &ports, const ExtSigSpe
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}
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}
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ExtSigSpec find_shared_operand(const OpMuxConn* seed, std::vector<const OpMuxConn *> &ports, const std::map<ExtSigSpec, std::set<RTLIL::Cell *>> &operand_to_users)
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ExtSigSpec find_shared_operand(const OpMuxConn* seed, std::vector<const OpMuxConn *> &ports, const std::map<ExtSigSpec, std::set<RTLIL::Cell *>> &operand_to_users, const SigMap &sigmap)
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{
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std::set<RTLIL::Cell *> ops_using_operand;
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std::set<RTLIL::Cell *> ops_set;
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@ -324,7 +311,7 @@ ExtSigSpec find_shared_operand(const OpMuxConn* seed, std::vector<const OpMuxCon
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auto op_a = seed->op;
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for (RTLIL::IdString port_name : {ID::A, ID::B}) {
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oper = decode_port(op_a, port_name, &assign_map);
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oper = decode_port(op_a, port_name, sigmap);
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auto operand_users = operand_to_users.at(oper);
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if (operand_users.size() == 1)
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@ -345,132 +332,6 @@ ExtSigSpec find_shared_operand(const OpMuxConn* seed, std::vector<const OpMuxCon
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return ExtSigSpec();
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}
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dict<RTLIL::SigSpec, OpMuxConn> find_valid_op_mux_conns(RTLIL::Module *module, dict<RTLIL::SigBit, RTLIL::SigSpec> &op_outbit_to_outsig,
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dict<RTLIL::SigSpec, RTLIL::Cell *> outsig_to_operator,
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dict<RTLIL::SigBit, RTLIL::SigSpec> &op_aux_to_outsig)
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{
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dict<RTLIL::SigSpec, int> op_outsig_user_track;
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dict<RTLIL::SigSpec, OpMuxConn> op_mux_conn_map;
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std::function<void(RTLIL::SigSpec)> remove_outsig = [&](RTLIL::SigSpec outsig) {
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for (auto op_outbit : outsig)
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op_outbit_to_outsig.erase(op_outbit);
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if (op_mux_conn_map.count(outsig))
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op_mux_conn_map.erase(outsig);
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};
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std::function<void(RTLIL::SigBit)> remove_outsig_from_aux_bit = [&](RTLIL::SigBit auxbit) {
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auto aux_outsig = op_aux_to_outsig.at(auxbit);
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auto op = outsig_to_operator.at(aux_outsig);
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auto op_outsig = assign_map(op->getPort(ID::Y));
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remove_outsig(op_outsig);
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for (auto aux_outbit : aux_outsig)
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op_aux_to_outsig.erase(aux_outbit);
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};
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std::function<void(RTLIL::Cell *)> find_op_mux_conns = [&](RTLIL::Cell *mux) {
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RTLIL::SigSpec sig;
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int mux_port_size;
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if (mux->type.in(ID($mux), ID($_MUX_))) {
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mux_port_size = mux->getPort(ID::A).size();
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sig = RTLIL::SigSpec{mux->getPort(ID::B), mux->getPort(ID::A)};
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} else {
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mux_port_size = mux->getPort(ID::A).size();
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sig = mux->getPort(ID::B);
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}
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auto mux_insig = assign_map(sig);
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for (int i = 0; i < mux_insig.size(); ++i) {
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if (op_aux_to_outsig.count(mux_insig[i])) {
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remove_outsig_from_aux_bit(mux_insig[i]);
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continue;
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}
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if (!op_outbit_to_outsig.count(mux_insig[i]))
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continue;
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auto op_outsig = op_outbit_to_outsig.at(mux_insig[i]);
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if (op_mux_conn_map.count(op_outsig)) {
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remove_outsig(op_outsig);
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continue;
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}
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int mux_port_id = i / mux_port_size;
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int mux_port_offset = i % mux_port_size;
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int op_outsig_offset;
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for (op_outsig_offset = 0; op_outsig[op_outsig_offset] != mux_insig[i]; ++op_outsig_offset)
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;
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int j = op_outsig_offset;
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do {
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if (!op_outbit_to_outsig.count(mux_insig[i]))
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break;
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if (op_outbit_to_outsig.at(mux_insig[i]) != op_outsig)
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break;
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++i;
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++j;
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} while ((i / mux_port_size == mux_port_id) && (j < op_outsig.size()));
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int op_conn_width = j - op_outsig_offset;
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OpMuxConn inp = {
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op_outsig.extract(op_outsig_offset, op_conn_width),
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mux,
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outsig_to_operator.at(op_outsig),
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mux_port_id,
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mux_port_offset,
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op_outsig_offset,
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};
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op_mux_conn_map[op_outsig] = inp;
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--i;
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}
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};
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std::function<void(RTLIL::SigSpec)> remove_connected_ops = [&](RTLIL::SigSpec sig) {
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auto mux_insig = assign_map(sig);
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for (auto outbit : mux_insig) {
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if (op_aux_to_outsig.count(outbit)) {
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remove_outsig_from_aux_bit(outbit);
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continue;
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}
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if (!op_outbit_to_outsig.count(outbit))
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continue;
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remove_outsig(op_outbit_to_outsig.at(outbit));
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}
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};
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for (auto cell : module->cells()) {
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if (cell->type.in(ID($mux), ID($_MUX_), ID($pmux))) {
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remove_connected_ops(cell->getPort(ID::S));
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find_op_mux_conns(cell);
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} else {
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for (auto &conn : cell->connections())
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if (cell->input(conn.first))
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remove_connected_ops(conn.second);
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}
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}
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for (auto w : module->wires()) {
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if (!w->port_output)
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continue;
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remove_connected_ops(w);
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}
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return op_mux_conn_map;
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}
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struct OptSharePass : public Pass {
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OptSharePass() : Pass("opt_share", "merge mutually exclusive cells of the same type that share an input signal") {}
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void help() override
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@ -495,37 +356,46 @@ struct OptSharePass : public Pass {
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extra_args(args, 1, design);
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for (auto module : design->selected_modules()) {
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assign_map.clear();
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assign_map.set(module);
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SigMap sigmap(module);
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dict<RTLIL::SigBit, int> bit_users;
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for (auto cell : module->cells())
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for (auto conn : cell->connections())
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for (auto bit : conn.second)
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bit_users[sigmap(bit)]++;
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for (auto wire : module->wires())
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if (wire->port_id != 0)
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for (auto bit : SigSpec(wire))
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bit_users[sigmap(bit)]++;
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std::map<ExtSigSpec, std::set<RTLIL::Cell *>> operand_to_users;
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dict<RTLIL::SigSpec, RTLIL::Cell *> outsig_to_operator;
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dict<RTLIL::SigBit, RTLIL::SigSpec> op_outbit_to_outsig;
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dict<RTLIL::SigBit, RTLIL::SigSpec> op_aux_to_outsig;
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dict<RTLIL::SigBit, std::pair<RTLIL::Cell *, int>> op_outbit_to_outsig;
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bool any_shared_operands = false;
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std::vector<ExtSigSpec> op_insigs;
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for (auto cell : module->cells()) {
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for (auto cell : module->selected_cells()) {
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if (!cell_supported(cell))
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continue;
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bool skip = false;
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if (cell->type == ID($alu)) {
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for (RTLIL::IdString port_name : {ID::X, ID::CO}) {
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auto mux_insig = assign_map(cell->getPort(port_name));
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outsig_to_operator[mux_insig] = cell;
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for (auto outbit : mux_insig)
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op_aux_to_outsig[outbit] = mux_insig;
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for (auto outbit : sigmap(cell->getPort(port_name)))
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if (bit_users[outbit] > 1)
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skip = true;
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}
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}
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auto mux_insig = assign_map(cell->getPort(ID::Y));
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outsig_to_operator[mux_insig] = cell;
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for (auto outbit : mux_insig)
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op_outbit_to_outsig[outbit] = mux_insig;
|
||||
if (skip)
|
||||
continue;
|
||||
|
||||
auto mux_insig = sigmap(cell->getPort(ID::Y));
|
||||
for (int i = 0; i < GetSize(mux_insig); i++)
|
||||
op_outbit_to_outsig[mux_insig[i]] = std::make_pair(cell, i);
|
||||
|
||||
for (RTLIL::IdString port_name : {ID::A, ID::B}) {
|
||||
auto op_insig = decode_port(cell, port_name, &assign_map);
|
||||
op_insigs.push_back(op_insig);
|
||||
auto op_insig = decode_port(cell, port_name, sigmap);
|
||||
operand_to_users[op_insig].insert(cell);
|
||||
if (operand_to_users[op_insig].size() > 1)
|
||||
any_shared_operands = true;
|
||||
|
|
@ -537,34 +407,79 @@ struct OptSharePass : public Pass {
|
|||
|
||||
// Operator outputs need to be exclusively connected to the $mux inputs in order to be mergeable. Hence we count to
|
||||
// how many points are operator output bits connected.
|
||||
dict<RTLIL::SigSpec, OpMuxConn> op_mux_conn_map =
|
||||
find_valid_op_mux_conns(module, op_outbit_to_outsig, outsig_to_operator, op_aux_to_outsig);
|
||||
std::vector<merged_op_t> merged_ops;
|
||||
|
||||
// Group op connections connected to same ports of the same $mux. Sort them in ascending order of their port offset
|
||||
dict<RTLIL::Cell*, std::vector<std::set<OpMuxConn>>> mux_port_op_conns;
|
||||
for (auto& val: op_mux_conn_map) {
|
||||
OpMuxConn p = val.second;
|
||||
auto& mux_port_conns = mux_port_op_conns[p.mux];
|
||||
for (auto mux : module->selected_cells()) {
|
||||
if (!mux->type.in(ID($mux), ID($_MUX_), ID($pmux)))
|
||||
continue;
|
||||
|
||||
if (mux_port_conns.size() == 0) {
|
||||
int mux_port_num;
|
||||
int mux_port_size = GetSize(mux->getPort(ID::A));
|
||||
int mux_port_num = GetSize(mux->getPort(ID::S)) + 1;
|
||||
|
||||
if (p.mux->type.in(ID($mux), ID($_MUX_)))
|
||||
mux_port_num = 2;
|
||||
else
|
||||
mux_port_num = p.mux->getPort(ID::S).size();
|
||||
RTLIL::SigSpec mux_insig = sigmap(RTLIL::SigSpec{mux->getPort(ID::B), mux->getPort(ID::A)});
|
||||
std::vector<std::set<OpMuxConn>> mux_port_conns(mux_port_num);
|
||||
int found = 0;
|
||||
|
||||
mux_port_conns.resize(mux_port_num);
|
||||
for (int mux_port_id = 0; mux_port_id < mux_port_num; mux_port_id++) {
|
||||
SigSpec mux_insig;
|
||||
if (mux_port_id == mux_port_num - 1) {
|
||||
mux_insig = sigmap(mux->getPort(ID::A));
|
||||
} else {
|
||||
mux_insig = sigmap(mux->getPort(ID::B).extract(mux_port_id * mux_port_size, mux_port_size));
|
||||
}
|
||||
|
||||
for (int mux_port_offset = 0; mux_port_offset < mux_port_size; ++mux_port_offset) {
|
||||
if (!op_outbit_to_outsig.count(mux_insig[mux_port_offset]))
|
||||
continue;
|
||||
|
||||
RTLIL::Cell *cell;
|
||||
int op_outsig_offset;
|
||||
std::tie(cell, op_outsig_offset) = op_outbit_to_outsig.at(mux_insig[mux_port_offset]);
|
||||
SigSpec op_outsig = sigmap(cell->getPort(ID::Y));
|
||||
int op_outsig_size = GetSize(op_outsig);
|
||||
int op_conn_width = 0;
|
||||
|
||||
while (mux_port_offset + op_conn_width < mux_port_size &&
|
||||
op_outsig_offset + op_conn_width < op_outsig_size &&
|
||||
mux_insig[mux_port_offset + op_conn_width] == op_outsig[op_outsig_offset + op_conn_width])
|
||||
op_conn_width++;
|
||||
|
||||
log_assert(op_conn_width >= 1);
|
||||
|
||||
bool skip = false;
|
||||
for (int i = 0; i < op_outsig_size; i++) {
|
||||
int expected = 1;
|
||||
if (i >= op_outsig_offset && i < op_outsig_offset + op_conn_width)
|
||||
expected = 2;
|
||||
if (bit_users[op_outsig[i]] != expected)
|
||||
skip = true;
|
||||
}
|
||||
if (skip) {
|
||||
mux_port_offset += op_conn_width;
|
||||
mux_port_offset--;
|
||||
continue;
|
||||
}
|
||||
|
||||
OpMuxConn inp = {
|
||||
op_outsig.extract(op_outsig_offset, op_conn_width),
|
||||
mux,
|
||||
cell,
|
||||
mux_port_id,
|
||||
mux_port_offset,
|
||||
op_outsig_offset,
|
||||
};
|
||||
|
||||
mux_port_conns[mux_port_id].insert(inp);
|
||||
|
||||
mux_port_offset += op_conn_width;
|
||||
mux_port_offset--;
|
||||
|
||||
found++;
|
||||
}
|
||||
}
|
||||
|
||||
mux_port_conns[p.mux_port_id].insert(p);
|
||||
}
|
||||
|
||||
std::vector<merged_op_t> merged_ops;
|
||||
for (auto& val: mux_port_op_conns) {
|
||||
|
||||
RTLIL::Cell* cell = val.first;
|
||||
auto &mux_port_conns = val.second;
|
||||
if (found < 2)
|
||||
continue;
|
||||
|
||||
const OpMuxConn *seed = NULL;
|
||||
|
||||
|
|
@ -612,12 +527,12 @@ struct OptSharePass : public Pass {
|
|||
continue;
|
||||
|
||||
// Filter mergeable connections whose ops share an operand with seed connection's op
|
||||
auto shared_operand = find_shared_operand(seed, mergeable_conns, operand_to_users);
|
||||
auto shared_operand = find_shared_operand(seed, mergeable_conns, operand_to_users, sigmap);
|
||||
|
||||
if (shared_operand.empty())
|
||||
continue;
|
||||
|
||||
check_muxed_operands(mergeable_conns, shared_operand);
|
||||
check_muxed_operands(mergeable_conns, shared_operand, sigmap);
|
||||
|
||||
if (mergeable_conns.size() < 2)
|
||||
continue;
|
||||
|
|
@ -631,7 +546,7 @@ struct OptSharePass : public Pass {
|
|||
|
||||
seed = NULL;
|
||||
|
||||
merged_ops.push_back(merged_op_t{cell, merged_ports, shared_operand});
|
||||
merged_ops.push_back(merged_op_t{mux, merged_ports, shared_operand});
|
||||
|
||||
design->scratchpad_set_bool("opt.did_something", true);
|
||||
}
|
||||
|
|
@ -647,7 +562,7 @@ struct OptSharePass : public Pass {
|
|||
log(" %s\n", log_id(op.op));
|
||||
log("\n");
|
||||
|
||||
merge_operators(module, shared.mux, shared.ports, shared.shared_operand);
|
||||
merge_operators(module, shared.mux, shared.ports, shared.shared_operand, sigmap);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,13 @@
|
|||
read_verilog <<EOT
|
||||
|
||||
module t(input [3:0] A, input [3:0] B, input [3:0] C, input S, output [3:0] Y);
|
||||
|
||||
wire [3:0] t = A + C;
|
||||
|
||||
assign Y = S ? A + B : {4{t[0]}};
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
equiv_opt -assert opt_share
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
read_verilog <<EOT
|
||||
|
||||
module top(...);
|
||||
|
||||
input [3:0] A, B, C;
|
||||
input S;
|
||||
input [1:0] T;
|
||||
output [3:0] X;
|
||||
output reg [3:0] Y;
|
||||
|
||||
wire [3:0] D = A + B;
|
||||
|
||||
assign X = S ? D : A + C;
|
||||
always @* begin
|
||||
case(T)
|
||||
2'b01: Y <= A;
|
||||
2'b10: Y <= B;
|
||||
default: Y <= D;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
proc
|
||||
equiv_opt -assert opt_share
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
read_verilog <<EOT
|
||||
|
||||
module top(input [3:0] A, B, C, input S, output [2:0] O);
|
||||
|
||||
wire [3:0] tb = A + B;
|
||||
wire [3:0] tc = A + C;
|
||||
|
||||
assign O = S ? tb[3:1] : tc[3:1];
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
equiv_opt -assert opt_share
|
||||
Loading…
Reference in New Issue