mirror of https://github.com/YosysHQ/yosys.git
rtlil: Make Process handling more uniform with Cell and Wire.
- add a backlink to module from Process - make constructor and destructor protected, expose Module functions to add and remove processes
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726fabd65e
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@ -319,16 +319,14 @@ struct AST_INTERNAL::ProcessGenerator
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LookaheadRewriter la_rewriter(always);
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// generate process and simple root case
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proc = new RTLIL::Process;
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proc = current_module->addProcess(stringf("$proc$%s:%d$%d", always->filename.c_str(), always->location.first_line, autoidx++));
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set_src_attr(proc, always);
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proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->location.first_line, autoidx++);
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for (auto &attr : always->attributes) {
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if (attr.second->type != AST_CONSTANT)
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log_file_error(always->filename, always->location.first_line, "Attribute `%s' with non-constant value!\n",
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attr.first.c_str());
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proc->attributes[attr.first] = attr.second->asAttrConst();
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}
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current_module->processes[proc->name] = proc;
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current_case = &proc->root_case;
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// create initial temporary signal for all output registers
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@ -283,10 +283,8 @@ proc_stmt:
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TOK_PROCESS TOK_ID EOL {
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if (current_module->processes.count($2) != 0)
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rtlil_frontend_yyerror(stringf("RTLIL error: redefinition of process %s.", $2).c_str());
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current_process = new RTLIL::Process;
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current_process->name = $2;
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current_process = current_module->addProcess($2);
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current_process->attributes = attrbuf;
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current_module->processes[$2] = current_process;
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switch_stack.clear();
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switch_stack.push_back(¤t_process->root_case.switches);
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case_stack.clear();
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@ -1839,6 +1839,14 @@ void RTLIL::Module::add(RTLIL::Cell *cell)
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cell->module = this;
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}
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void RTLIL::Module::add(RTLIL::Process *process)
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{
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log_assert(!process->name.empty());
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log_assert(count_id(process->name) == 0);
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processes[process->name] = process;
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process->module = this;
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}
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void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
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{
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log_assert(refcount_wires_ == 0);
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@ -1895,6 +1903,13 @@ void RTLIL::Module::remove(RTLIL::Cell *cell)
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delete cell;
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}
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void RTLIL::Module::remove(RTLIL::Process *process)
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{
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log_assert(processes.count(process->name) != 0);
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processes.erase(process->name);
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delete process;
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}
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void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
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{
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log_assert(wires_[wire->name] == wire);
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@ -2120,11 +2135,19 @@ RTLIL::Memory *RTLIL::Module::addMemory(RTLIL::IdString name, const RTLIL::Memor
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return mem;
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}
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RTLIL::Process *RTLIL::Module::addProcess(RTLIL::IdString name)
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{
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RTLIL::Process *proc = new RTLIL::Process;
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proc->name = name;
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add(proc);
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return proc;
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}
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RTLIL::Process *RTLIL::Module::addProcess(RTLIL::IdString name, const RTLIL::Process *other)
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{
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RTLIL::Process *proc = other->clone();
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proc->name = name;
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processes[name] = proc;
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add(proc);
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return proc;
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}
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@ -2920,6 +2943,13 @@ RTLIL::Memory::Memory()
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#endif
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}
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RTLIL::Process::Process() : module(nullptr)
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{
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static unsigned int hashidx_count = 123456789;
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hashidx_count = mkhash_xorshift(hashidx_count);
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hashidx_ = hashidx_count;
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}
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RTLIL::Cell::Cell() : module(nullptr)
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{
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static unsigned int hashidx_count = 123456789;
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@ -1129,6 +1129,7 @@ struct RTLIL::Module : public RTLIL::AttrObject
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protected:
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void add(RTLIL::Wire *wire);
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void add(RTLIL::Cell *cell);
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void add(RTLIL::Process *process);
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public:
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RTLIL::Design *design;
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@ -1209,6 +1210,7 @@ public:
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// Removing wires is expensive. If you have to remove wires, remove them all at once.
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void remove(const pool<RTLIL::Wire*> &wires);
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void remove(RTLIL::Cell *cell);
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void remove(RTLIL::Process *process);
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void rename(RTLIL::Wire *wire, RTLIL::IdString new_name);
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void rename(RTLIL::Cell *cell, RTLIL::IdString new_name);
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@ -1228,6 +1230,7 @@ public:
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RTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other);
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RTLIL::Process *addProcess(RTLIL::IdString name);
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RTLIL::Process *addProcess(RTLIL::IdString name, const RTLIL::Process *other);
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// The add* methods create a cell and return the created cell. All signals must exist in advance.
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@ -1581,12 +1584,21 @@ struct RTLIL::SyncRule
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struct RTLIL::Process : public RTLIL::AttrObject
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{
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unsigned int hashidx_;
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unsigned int hash() const { return hashidx_; }
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protected:
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// use module->addProcess() and module->remove() to create or destroy processes
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friend struct RTLIL::Module;
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Process();
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~Process();
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public:
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RTLIL::IdString name;
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RTLIL::Module *module;
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RTLIL::CaseRule root_case;
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std::vector<RTLIL::SyncRule*> syncs;
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~Process();
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template<typename T> void rewrite_sigspecs(T &functor);
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template<typename T> void rewrite_sigspecs2(T &functor);
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RTLIL::Process *clone() const;
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@ -222,6 +222,7 @@ namespace RTLIL {
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struct Wire;
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struct Cell;
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struct Memory;
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struct Process;
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struct Module;
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struct Design;
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struct Monitor;
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@ -245,6 +246,7 @@ namespace hashlib {
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template<> struct hash_ops<RTLIL::Wire*> : hash_obj_ops {};
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template<> struct hash_ops<RTLIL::Cell*> : hash_obj_ops {};
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template<> struct hash_ops<RTLIL::Memory*> : hash_obj_ops {};
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template<> struct hash_ops<RTLIL::Process*> : hash_obj_ops {};
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template<> struct hash_ops<RTLIL::Module*> : hash_obj_ops {};
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template<> struct hash_ops<RTLIL::Design*> : hash_obj_ops {};
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template<> struct hash_ops<RTLIL::Monitor*> : hash_obj_ops {};
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@ -253,6 +255,7 @@ namespace hashlib {
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template<> struct hash_ops<const RTLIL::Wire*> : hash_obj_ops {};
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template<> struct hash_ops<const RTLIL::Cell*> : hash_obj_ops {};
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template<> struct hash_ops<const RTLIL::Memory*> : hash_obj_ops {};
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template<> struct hash_ops<const RTLIL::Process*> : hash_obj_ops {};
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template<> struct hash_ops<const RTLIL::Module*> : hash_obj_ops {};
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template<> struct hash_ops<const RTLIL::Design*> : hash_obj_ops {};
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template<> struct hash_ops<const RTLIL::Monitor*> : hash_obj_ops {};
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@ -275,7 +275,7 @@ struct BugpointPass : public Pass {
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if (mod->get_blackbox_attribute())
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continue;
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RTLIL::IdString removed_process;
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RTLIL::Process *removed_process = nullptr;
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for (auto process : mod->processes)
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{
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if (process.second->get_bool_attribute(ID::bugpoint_keep))
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@ -284,13 +284,12 @@ struct BugpointPass : public Pass {
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if (index++ == seed)
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{
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log_header(design, "Trying to remove process %s.%s.\n", log_id(mod), log_id(process.first));
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removed_process = process.first;
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removed_process = process.second;
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break;
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}
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}
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if (!removed_process.empty()) {
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delete mod->processes[removed_process];
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mod->processes.erase(removed_process);
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if (removed_process) {
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mod->remove(removed_process);
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return design_copy;
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}
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}
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@ -90,7 +90,7 @@ struct DeletePass : public Pass {
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pool<RTLIL::Wire*> delete_wires;
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pool<RTLIL::Cell*> delete_cells;
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pool<RTLIL::IdString> delete_procs;
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pool<RTLIL::Process*> delete_procs;
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pool<RTLIL::IdString> delete_mems;
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for (auto wire : module->selected_wires())
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@ -110,7 +110,7 @@ struct DeletePass : public Pass {
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for (auto &it : module->processes)
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if (design->selected(module, it.second))
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delete_procs.insert(it.first);
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delete_procs.insert(it.second);
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for (auto &it : delete_mems) {
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delete module->memories.at(it);
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@ -120,10 +120,8 @@ struct DeletePass : public Pass {
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for (auto &it : delete_cells)
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module->remove(it);
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for (auto &it : delete_procs) {
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delete module->processes.at(it);
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module->processes.erase(it);
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}
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for (auto &it : delete_procs)
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module->remove(it);
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module->remove(delete_wires);
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@ -209,7 +209,7 @@ struct ProcCleanPass : public Pass {
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extra_args(args, argidx, design);
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for (auto mod : design->modules()) {
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std::vector<RTLIL::IdString> delme;
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std::vector<RTLIL::Process *> delme;
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if (!design->selected(mod))
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continue;
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for (auto &proc_it : mod->processes) {
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@ -220,12 +220,11 @@ struct ProcCleanPass : public Pass {
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proc_it.second->root_case.actions.size() == 0) {
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if (!quiet)
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log("Removing empty process `%s.%s'.\n", log_id(mod), proc_it.second->name.c_str());
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delme.push_back(proc_it.first);
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delme.push_back(proc_it.second);
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}
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}
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for (auto &id : delme) {
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delete mod->processes[id];
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mod->processes.erase(id);
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for (auto proc : delme) {
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mod->remove(proc);
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}
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}
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