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bug fix and cleanups

This commit is contained in:
Miodrag Milanovic 2022-02-04 10:01:06 +01:00
parent 7ef6da4c7d
commit 6db23de7b1
3 changed files with 8 additions and 8 deletions
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2
kernel/fstdata.cc
View File

@ -174,7 +174,7 @@ static void reconstruct_clb_attimes(void *user_data, uint64_t pnt_time, fstHandl
void FstData::reconstruct_callback_attimes(uint64_t pnt_time, fstHandle pnt_facidx, const unsigned char *pnt_value, uint32_t /* plen */)
{
if (sample_times_ndx > sample_times.size()) return;
if (sample_times_ndx >= sample_times.size()) return;
uint64_t time = sample_times[sample_times_ndx];
// if we are past the timestamp

10
passes/sat/sim.cc
View File

@ -752,7 +752,7 @@ struct SimInstance
} else if (shared->sim_mode == SimulationMode::gate && !fst_val.is_fully_def()) { // FST data contains X
for(int i=0;i<fst_val.size();i++) {
if (fst_val[i]!=State::Sx && fst_val[i]!=sim_val[i]) {
log_warning("Signal '%s' in file '%s' in simulation '%s'\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
log_warning("Signal '%s' in file %s in simulation %s\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
retVal = true;
break;
}
@ -760,14 +760,14 @@ struct SimInstance
} else if (shared->sim_mode == SimulationMode::gold && !sim_val.is_fully_def()) { // sim data contains X
for(int i=0;i<sim_val.size();i++) {
if (sim_val[i]!=State::Sx && fst_val[i]!=sim_val[i]) {
log_warning("Signal '%s' in file '%s' in simulation '%s'\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
log_warning("Signal '%s' in file %s in simulation %s\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
retVal = true;
break;
}
}
} else {
if (fst_val!=sim_val) {
log_warning("Signal '%s' in file '%s' in simulation '%s'\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
log_warning("Signal '%s' in file %s in simulation '%s'\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
retVal = true;
}
}
@ -1048,9 +1048,9 @@ struct SimWorker : SimShared
fst->reconstructAllAtTimes(samples);
bool initial = true;
int cycle = 0;
log("Co-simulation from %zu%s to %zu%s\n", startCount, fst->getTimescaleString(), stopCount, fst->getTimescaleString());
log("Co-simulation from %lu%s to %lu%s\n", (unsigned long)startCount, fst->getTimescaleString(), (unsigned long)stopCount, fst->getTimescaleString());
for(auto &time : samples) {
log("Co-simulating cycle %d [%zu%s].\n", cycle, time, fst->getTimescaleString());
log("Co-simulating cycle %d [%lu%s].\n", cycle, (unsigned long)time, fst->getTimescaleString());
for(auto &item : inputs) {
std::string v = fst->valueAt(item.second, time);
top->set_state(item.first, Const::from_string(v));

4
tests/sat/grom.ys
View File

@ -1,9 +1,9 @@
read_verilog grom_computer.v grom_cpu.v alu.v ram_memory.v;
prep -top grom_computer;
sim -clock clk -reset reset -fst grom.fst -vcd grom.vcd -a -n 80
sim -clock clk -reset reset -fst grom.fst -vcd grom.vcd -n 80
sim -clock clk -r grom.fst -scope grom_computer -start 25ns -stop 100ns -sim-cmp
sim -clock clk -r grom.fst -scope grom_computer -stop 100ns -sim-gold
sim -clock clk -r grom.fst -scope grom_computer -n 10 -sim-gate -a
sim -clock clk -r grom.fst -scope grom_computer -n 10 -sim-gate