riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

memory_bram: Move init data swizzling before other swizzling. 

Fixes #2907.
This commit is contained in:
Marcelina Kościelnicka 2021-08-03 14:28:10 +02:00
parent ca8ad62696
commit 8733e1923a
1 changed files with 18 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
passes/memory/memory_bram.cc
View File

@ -798,6 +798,24 @@ grow_read_ports:;
for (int j = 0; j < i; j++)
mem.emulate_priority(j, i);
// Swizzle the init data. Do this before changing mem.width, so that get_init_data works.
bool cell_init = !mem.inits.empty();
vector<Const> initdata;
if (cell_init) {
Const initparam = mem.get_init_data();
initdata.reserve(mem.size);
for (int i = 0; i < mem.size; i++) {
std::vector<State> val;
for (auto idx : shuffle_map) {
if (idx == -1)
val.push_back(State::Sx);
else
val.push_back(initparam[mem.width * i + idx]);
}
initdata.push_back(Const(val));
}
}
// Now the big swizzle.
mem.width = GetSize(shuffle_map);
@ -837,24 +855,6 @@ grow_read_ports:;
port.srst_value = new_srst_value;
}
// Swizzle the init data.
bool cell_init = !mem.inits.empty();
vector<Const> initdata;
if (cell_init) {
Const initparam = mem.get_init_data();
initdata.reserve(mem.size);
for (int i = 0; i < mem.size; i++) {
std::vector<State> val;
for (auto idx : shuffle_map) {
if (idx == -1)
val.push_back(State::Sx);
else
val.push_back(initparam[mem.width * i + idx]);
}
initdata.push_back(Const(val));
}
}
// prepare variant parameters
dict<IdString, Const> variant_params;