riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

memory_share: Add wide port support.

This commit is contained in:
Marcelina Kościelnicka 2021-05-25 01:55:44 +02:00
parent 9d5d5a48b1
commit 47f958ce45
1 changed files with 6 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
passes/memory/memory_share.cc
View File

@ -143,6 +143,7 @@ struct MemoryShareWorker
bool cache_clk_enable = false;
bool cache_clk_polarity = false;
RTLIL::SigSpec cache_clk;
int cache_wide_log2 = 0;
bool changed = false;
@ -152,12 +153,14 @@ struct MemoryShareWorker
RTLIL::SigSpec addr = sigmap_xmux(port.addr);
if (port.clk_enable != cache_clk_enable ||
port.wide_log2 != cache_wide_log2 ||
(cache_clk_enable && (sigmap(port.clk) != cache_clk ||
port.clk_polarity != cache_clk_polarity)))
{
cache_clk_enable = port.clk_enable;
cache_clk_polarity = port.clk_polarity;
cache_clk = sigmap(port.clk);
cache_wide_log2 = port.wide_log2;
last_port_by_addr.clear();
if (cache_clk_enable)
@ -290,18 +293,21 @@ struct MemoryShareWorker
bool cache_clk_enable = false;
bool cache_clk_polarity = false;
RTLIL::SigSpec cache_clk;
int cache_wide_log2 = 0;
for (int i = 0; i < GetSize(mem.wr_ports); i++)
{
auto &port = mem.wr_ports[i];
if (port.clk_enable != cache_clk_enable ||
port.wide_log2 != cache_wide_log2 ||
(cache_clk_enable && (sigmap(port.clk) != cache_clk ||
port.clk_polarity != cache_clk_polarity)))
{
cache_clk_enable = port.clk_enable;
cache_clk_polarity = port.clk_polarity;
cache_clk = sigmap(port.clk);
cache_wide_log2 = port.wide_log2;
}
else if (i > 0 && considered_ports.count(i-1) && considered_ports.count(i))
considered_port_pairs.insert(i);