mirror of https://github.com/YosysHQ/yosys.git
opt_merge: Remove and reinsert init when connecting nets.
Mutating the SigMap by adding a new connection will throw off FfInitVals index. Work around this by removing the relevant init values from index whenever we connect nets, then re-add the new init value. Should fix #2920.
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@ -282,11 +282,12 @@ struct OptMergeWorker
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RTLIL::SigSpec other_sig = r.first->second->getPort(it.first);
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log_debug(" Redirecting output %s: %s = %s\n", it.first.c_str(),
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log_signal(it.second), log_signal(other_sig));
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Const init = initvals(other_sig);
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initvals.remove_init(it.second);
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initvals.remove_init(other_sig);
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module->connect(RTLIL::SigSig(it.second, other_sig));
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assign_map.add(it.second, other_sig);
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if (it.first == ID::Q && RTLIL::builtin_ff_cell_types().count(cell->type))
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initvals.remove_init(it.second);
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initvals.set_init(other_sig, init);
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}
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}
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log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());
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