riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

More verbose warnings

This commit is contained in:
Miodrag Milanovic 2022-03-18 14:47:35 +01:00
parent 0c5279b73d
commit 55eed8df57
2 changed files with 9 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
kernel/fstdata.cc
View File

@ -101,7 +101,8 @@ void FstData::extractVarNames()
case FST_HT_SCOPE: {
snum++;
std::string fst_scope_name = fstReaderPushScope(ctx, h->u.scope.name, (void *)(snum));
scopes.push_back(fst_scope_name);
if (h->u.scope.typ == FST_ST_VCD_MODULE)
scopes.push_back(fst_scope_name);
break;
}
case FST_HT_UPSCOPE: {

12
passes/sat/sim.cc
View File

@ -809,14 +809,16 @@ struct SimInstance
if (item.second==0) continue; // Ignore signals not found
Const fst_val = Const::from_string(shared->fst->valueOf(item.second));
Const sim_val = get_state(item.first);
if (sim_val.size()!=fst_val.size())
log_error("Signal '%s' size is different in gold and gate.\n", log_id(item.first));
if (sim_val.size()!=fst_val.size()) {
log_warning("Signal '%s.%s' size is different in gold and gate.\n", scope.c_str(), log_id(item.first));
continue;
}
if (shared->sim_mode == SimulationMode::sim) {
// No checks performed when using stimulus
} else if (shared->sim_mode == SimulationMode::gate && !fst_val.is_fully_def()) { // FST data contains X
for(int i=0;i<fst_val.size();i++) {
if (fst_val[i]!=State::Sx && fst_val[i]!=sim_val[i]) {
log_warning("Signal '%s' in file %s in simulation %s\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
log_warning("Signal '%s.%s' in file %s in simulation %s\n", scope.c_str(), log_id(item.first), log_signal(fst_val), log_signal(sim_val));
retVal = true;
break;
}
@ -824,14 +826,14 @@ struct SimInstance
} else if (shared->sim_mode == SimulationMode::gold && !sim_val.is_fully_def()) { // sim data contains X
for(int i=0;i<sim_val.size();i++) {
if (sim_val[i]!=State::Sx && fst_val[i]!=sim_val[i]) {
log_warning("Signal '%s' in file %s in simulation %s\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
log_warning("Signal '%s.%s' in file %s in simulation %s\n", scope.c_str(), log_id(item.first), log_signal(fst_val), log_signal(sim_val));
retVal = true;
break;
}
}
} else {
if (fst_val!=sim_val) {
log_warning("Signal '%s' in file %s in simulation '%s'\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
log_warning("Signal '%s.%s' in file %s in simulation '%s'\n", scope.c_str(), log_id(item.first), log_signal(fst_val), log_signal(sim_val));
retVal = true;
}
}