mirror of https://github.com/YosysHQ/yosys.git
memory_dff: Recognize read ports with reset / initial value.
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parent
24027b5446
commit
72d86c327e
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@ -60,11 +60,6 @@ struct MemoryDffWorker
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log("output FF has both set and reset, not supported.\n");
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return;
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}
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if (ff.has_srst || ff.has_arst || !ff.val_init.is_fully_undef()) {
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// TODO: not supported yet
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log("output FF has reset and/or init value, not supported yet.\n");
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return;
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}
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merger.remove_output_ff(bits);
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if (ff.has_en && !ff.pol_en)
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ff.sig_en = module->LogicNot(NEW_ID, ff.sig_en);
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@ -79,7 +74,6 @@ struct MemoryDffWorker
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port.en = ff.sig_en;
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else
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port.en = State::S1;
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#if 0
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if (ff.has_arst) {
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port.arst = ff.sig_arst;
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port.arst_value = ff.val_arst;
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@ -94,7 +88,6 @@ struct MemoryDffWorker
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port.srst = State::S0;
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}
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port.init_value = ff.val_init;
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#endif
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port.data = ff.sig_q;
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mem.emit();
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log("merged output FF to cell.\n");
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@ -0,0 +1,27 @@
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// expect-wr-ports 1
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// expect-rd-ports 1
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// expect-rd-clk \clk
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// expect-rd-en \re
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// expect-rd-arst-sig \reset
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// expect-rd-arst-val 8'01011010
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// expect-rd-init-val 8'00111100
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module top(input clk, input we, re, reset, input [7:0] addr, wdata, output reg [7:0] rdata);
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reg [7:0] bram[0:255];
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initial rdata = 8'h3c;
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always @(posedge clk) begin
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if (we)
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bram[addr] <= wdata;
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end
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always @(posedge clk, posedge reset) begin
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if (reset)
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rdata <= 8'h5a;
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else if (re)
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rdata <= bram[addr];
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end
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endmodule
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@ -1,6 +1,9 @@
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// expect-wr-ports 1
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// expect-rd-ports 1
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// expect-no-rd-clk
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// expect-rd-clk \clk
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// expect-rd-en \re
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// expect-rd-srst-sig \reset
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// expect-rd-srst-val 8'00000000
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module top(input clk, input we, re, reset, input [7:0] addr, wdata, output reg [7:0] rdata);
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@ -31,6 +31,30 @@ for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do
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grep -q "connect \\\\RD_CLK \\$(gawk '/expect-rd-clk/ { print $3; }' $f)\$" ${f%.v}.dmp ||
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{ echo " ERROR: Unexpected read clock."; false; }
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fi
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if grep -q expect-rd-en $f; then
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grep -q "connect \\\\RD_EN \\$(gawk '/expect-rd-en/ { print $3; }' $f)\$" ${f%.v}.dmp ||
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{ echo " ERROR: Unexpected read enable."; false; }
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fi
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if grep -q expect-rd-srst-sig $f; then
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grep -q "connect \\\\RD_SRST \\$(gawk '/expect-rd-srst-sig/ { print $3; }' $f)\$" ${f%.v}.dmp ||
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{ echo " ERROR: Unexpected read sync reset."; false; }
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fi
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if grep -q expect-rd-srst-val $f; then
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grep -q "parameter \\\\RD_SRST_VALUE $(gawk '/expect-rd-srst-val/ { print $3; }' $f)\$" ${f%.v}.dmp ||
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{ echo " ERROR: Unexpected read sync reset value."; false; }
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fi
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if grep -q expect-rd-arst-sig $f; then
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grep -q "connect \\\\RD_ARST \\$(gawk '/expect-rd-arst-sig/ { print $3; }' $f)\$" ${f%.v}.dmp ||
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{ echo " ERROR: Unexpected read async reset."; false; }
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fi
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if grep -q expect-rd-arst-val $f; then
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grep -q "parameter \\\\RD_ARST_VALUE $(gawk '/expect-rd-arst-val/ { print $3; }' $f)\$" ${f%.v}.dmp ||
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{ echo " ERROR: Unexpected read async reset value."; false; }
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fi
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if grep -q expect-rd-init-val $f; then
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grep -q "parameter \\\\RD_INIT_VALUE $(gawk '/expect-rd-init-val/ { print $3; }' $f)\$" ${f%.v}.dmp ||
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{ echo " ERROR: Unexpected read init value."; false; }
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fi
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if grep -q expect-no-rd-clk $f; then
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grep -q "connect \\\\RD_CLK 1'x\$" ${f%.v}.dmp ||
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{ echo " ERROR: Expected no read clock."; false; }
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