mirror of https://github.com/YosysHQ/yosys.git
dfflegalize: Refactor to use FfInitVals.
This commit is contained in:
Marcelina Kościelnicka
parent
abe4e9e607
commit
e98382f6e2
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@ -19,6 +19,7 @@
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/ffinit.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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@ -170,7 +171,7 @@ struct DffLegalizePass : public Pass {
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dict<SigBit, int> srst_used;
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SigMap sigmap;
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dict<SigBit, std::pair<State,SigBit>> initbits;
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FfInitVals initvals;
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int flip_initmask(int mask) {
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int res = mask & INIT_X;
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@ -303,13 +304,7 @@ struct DffLegalizePass : public Pass {
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return;
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}
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State initval = State::Sx;
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SigBit initbit;
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if (GetSize(sig_q) > 0 && initbits.count(sigmap(sig_q[0]))) {
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const auto &d = initbits.at(sigmap(sig_q[0]));
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initval = d.first;
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initbit = d.second;
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}
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State initval = initvals(sig_q[0]);
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FfInit initmask = INIT_X;
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if (initval == State::S0)
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@ -345,12 +340,8 @@ flip_dqi:
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sig_d = cell->module->NotGate(NEW_ID, sig_d[0]);
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SigBit new_q = SigSpec(cell->module->addWire(NEW_ID))[0];
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cell->module->addNotGate(NEW_ID, new_q, sig_q[0]);
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if (initbit.wire) {
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initbit.wire->attributes.at(ID::init)[initbit.offset] = State::Sx;
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initbit = new_q;
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new_q.wire->attributes[ID::init] = initval;
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initbits[new_q] = std::make_pair(initval, new_q);
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}
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initvals.remove_init(sig_q[0]);
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initvals.set_init(new_q, initval);
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sig_q = new_q;
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continue;
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}
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@ -484,15 +475,12 @@ unmap_enable:
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}
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log_warning("Emulating mismatched async reset and init with several FFs and a mux for %s.%s\n", log_id(cell->module->name), log_id(cell->name));
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if (initbit.wire)
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initbit.wire->attributes.at(ID::init)[initbit.offset] = State::Sx;
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initvals.remove_init(sig_q[0]);
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Wire *adff_q = cell->module->addWire(NEW_ID);
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Wire *dff_q = cell->module->addWire(NEW_ID);
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Wire *sel_q = cell->module->addWire(NEW_ID);
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dff_q->attributes[ID::init] = initval;
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initbits[SigBit(dff_q, 0)] = std::make_pair(initval, SigBit(dff_q, 0));
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sel_q->attributes[ID::init] = State::S0;
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initbits[SigBit(sel_q, 0)] = std::make_pair(State::S0, SigBit(sel_q, 0));
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initvals.set_init(SigBit(dff_q, 0), initval);
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initvals.set_init(SigBit(sel_q, 0), State::S0);
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Cell *cell_dff;
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Cell *cell_adff;
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Cell *cell_sel;
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@ -588,21 +576,15 @@ flip_dqisr:;
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}
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log_warning("Emulating async set + reset with several FFs and a mux for %s.%s\n", log_id(cell->module->name), log_id(cell->name));
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if (initbit.wire)
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initbit.wire->attributes.at(ID::init)[initbit.offset] = State::Sx;
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initvals.remove_init(sig_q[0]);
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Wire *adff0_q = cell->module->addWire(NEW_ID);
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Wire *adff1_q = cell->module->addWire(NEW_ID);
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Wire *sel_q = cell->module->addWire(NEW_ID);
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if (init0) {
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adff0_q->attributes[ID::init] = initval;
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initbits[SigBit(adff0_q, 0)] = std::make_pair(initval, SigBit(adff0_q, 0));
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}
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if (init1) {
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adff1_q->attributes[ID::init] = initval;
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initbits[SigBit(adff1_q, 0)] = std::make_pair(initval, SigBit(adff1_q, 0));
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}
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sel_q->attributes[ID::init] = initsel;
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initbits[SigBit(sel_q, 0)] = std::make_pair(initsel, SigBit(sel_q, 0));
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if (init0)
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initvals.set_init(SigBit(adff0_q, 0), initval);
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if (init1)
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initvals.set_init(SigBit(adff1_q, 0), initval);
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initvals.set_init(SigBit(sel_q, 0), initsel);
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Cell *cell_adff0;
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Cell *cell_adff1;
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Cell *cell_sel;
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@ -741,15 +723,12 @@ flip_dqisr:;
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// The only hope left is breaking down to adff + dff + dlatch + mux.
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log_warning("Emulating mismatched async reset and init with several latches and a mux for %s.%s\n", log_id(cell->module->name), log_id(cell->name));
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if (initbit.wire)
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initbit.wire->attributes.at(ID::init)[initbit.offset] = State::Sx;
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initvals.remove_init(sig_q[0]);
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Wire *adlatch_q = cell->module->addWire(NEW_ID);
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Wire *dlatch_q = cell->module->addWire(NEW_ID);
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Wire *sel_q = cell->module->addWire(NEW_ID);
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dlatch_q->attributes[ID::init] = initval;
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initbits[SigBit(dlatch_q, 0)] = std::make_pair(initval, SigBit(dlatch_q, 0));
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sel_q->attributes[ID::init] = State::S0;
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initbits[SigBit(sel_q, 0)] = std::make_pair(State::S0, SigBit(sel_q, 0));
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initvals.set_init(SigBit(dlatch_q, 0), initval);
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initvals.set_init(SigBit(sel_q, 0), State::S0);
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Cell *cell_dlatch;
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Cell *cell_adlatch;
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Cell *cell_sel;
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@ -797,21 +776,15 @@ flip_dqisr:;
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}
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log_warning("Emulating async set + reset with several latches and a mux for %s.%s\n", log_id(cell->module->name), log_id(cell->name));
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if (initbit.wire)
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initbit.wire->attributes.at(ID::init)[initbit.offset] = State::Sx;
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initvals.remove_init(sig_q[0]);
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Wire *adlatch0_q = cell->module->addWire(NEW_ID);
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Wire *adlatch1_q = cell->module->addWire(NEW_ID);
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Wire *sel_q = cell->module->addWire(NEW_ID);
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if (init0) {
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adlatch0_q->attributes[ID::init] = initval;
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initbits[SigBit(adlatch0_q, 0)] = std::make_pair(initval, SigBit(adlatch0_q, 0));
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}
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if (init1) {
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adlatch1_q->attributes[ID::init] = initval;
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initbits[SigBit(adlatch1_q, 0)] = std::make_pair(initval, SigBit(adlatch1_q, 0));
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}
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sel_q->attributes[ID::init] = initsel;
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initbits[SigBit(sel_q, 0)] = std::make_pair(initsel, SigBit(sel_q, 0));
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if (init0)
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initvals.set_init(SigBit(adlatch0_q, 0), initval);
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if (init1)
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initvals.set_init(SigBit(adlatch1_q, 0), initval);
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initvals.set_init(SigBit(sel_q, 0), initsel);
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Cell *cell_adlatch0;
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Cell *cell_adlatch1;
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Cell *cell_sel;
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@ -1294,35 +1267,7 @@ unrecognized:
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for (auto module : design->selected_modules())
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{
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sigmap.set(module);
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initbits.clear();
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for (auto wire : module->wires())
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{
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if (wire->attributes.count(ID::init) == 0)
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continue;
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SigSpec wirebits = sigmap(wire);
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Const initval = wire->attributes.at(ID::init);
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for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++)
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{
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SigBit bit = wirebits[i];
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State val = initval[i];
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if (val != State::S0 && val != State::S1 && bit.wire != nullptr)
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continue;
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if (initbits.count(bit)) {
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if (initbits.at(bit).first != val)
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log_error("Conflicting init values for signal %s (%s = %s != %s).\n",
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log_signal(bit), log_signal(SigBit(wire, i)),
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log_signal(val), log_signal(initbits.at(bit).first));
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continue;
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}
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initbits[bit] = std::make_pair(val,SigBit(wire,i));
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}
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}
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initvals.set(&sigmap, module);
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if (mince || minsrst) {
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ce_used.clear();
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@ -1365,7 +1310,7 @@ unrecognized:
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}
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sigmap.clear();
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initbits.clear();
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initvals.clear();
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ce_used.clear();
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srst_used.clear();
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}
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