mirror of https://github.com/YosysHQ/yosys.git
clkbufmap: improve input pad handling.
- allow inserting only the input pad cell - do not insert the usual buffer if the input pad already acts as a buffer
This commit is contained in:
Marcelina Kościelnicka
parent
802671b22e
commit
32d2cc8c28
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@ -34,33 +34,34 @@ void split_portname_pair(std::string &port1, std::string &port2)
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}
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struct ClkbufmapPass : public Pass {
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ClkbufmapPass() : Pass("clkbufmap", "insert global buffers on clock networks") { }
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ClkbufmapPass() : Pass("clkbufmap", "insert clock buffers on clock networks") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" clkbufmap [options] [selection]\n");
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log("\n");
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log("Inserts global buffers between nets connected to clock inputs and their drivers.\n");
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log("Inserts clock buffers between nets connected to clock inputs and their drivers.\n");
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log("\n");
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log("In the absence of any selection, all wires without the 'clkbuf_inhibit'\n");
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log("attribute will be considered for global buffer insertion.\n");
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log("attribute will be considered for clock buffer insertion.\n");
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log("Alternatively, to consider all wires without the 'buffer_type' attribute set to\n");
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log("'none' or 'bufr' one would specify:\n");
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log(" 'w:* a:buffer_type=none a:buffer_type=bufr %%u %%d'\n");
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log("as the selection.\n");
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log("\n");
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log(" -buf <celltype> <portname_out>:<portname_in>\n");
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log(" Specifies the cell type to use for the global buffers\n");
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log(" Specifies the cell type to use for the clock buffers\n");
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log(" and its port names. The first port will be connected to\n");
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log(" the clock network sinks, and the second will be connected\n");
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log(" to the actual clock source. This option is required.\n");
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log(" to the actual clock source.\n");
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log("\n");
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log(" -inpad <celltype> <portname_out>:<portname_in>\n");
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log(" If specified, a PAD cell of the given type is inserted on\n");
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log(" clock nets that are also top module's inputs (in addition\n");
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log(" to the global buffer).\n");
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log(" to the clock buffer, if any).\n");
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log("\n");
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log("At least one of -buf or -inpad should be specified.\n");
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}
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void module_queue(Design *design, Module *module, std::vector<Module *> &modules_sorted, pool<Module *> &modules_processed) {
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@ -78,7 +79,7 @@ struct ClkbufmapPass : public Pass {
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing CLKBUFMAP pass (inserting global clock buffers).\n");
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log_header(design, "Executing CLKBUFMAP pass (inserting clock buffers).\n");
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std::string buf_celltype, buf_portname, buf_portname2;
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std::string inpad_celltype, inpad_portname, inpad_portname2;
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@ -109,8 +110,8 @@ struct ClkbufmapPass : public Pass {
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extra_args(args, argidx, design);
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}
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if (buf_celltype.empty())
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log_error("The -buf option is required.\n");
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if (buf_celltype.empty() && inpad_celltype.empty())
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log_error("Either the -buf option or -inpad option is required.\n");
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// Cell type, port name, bit index.
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pool<pair<IdString, pair<IdString, int>>> sink_ports;
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@ -118,6 +119,16 @@ struct ClkbufmapPass : public Pass {
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dict<pair<IdString, pair<IdString, int>>, pair<IdString, int>> inv_ports_out;
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dict<pair<IdString, pair<IdString, int>>, pair<IdString, int>> inv_ports_in;
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// If true, use both ther -buf and -inpad cell for input ports that are clocks.
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bool buffer_inputs = true;
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Module *inpad_mod = design->module(RTLIL::escape_id(inpad_celltype));
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if (inpad_mod) {
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Wire *buf_wire = inpad_mod->wire(RTLIL::escape_id(buf_portname));
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if (buf_wire && buf_wire->get_bool_attribute(ID::clkbuf_driver))
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buffer_inputs = false;
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}
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// Process submodules before module using them.
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std::vector<Module *> modules_sorted;
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pool<Module *> modules_processed;
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@ -242,19 +253,30 @@ struct ClkbufmapPass : public Pass {
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// Clock network not yet buffered, driven by one of
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// our cells or a top-level input -- buffer it.
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log("Inserting %s on %s.%s[%d].\n", buf_celltype.c_str(), log_id(module), log_id(wire), i);
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RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(buf_celltype));
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Wire *iwire = module->addWire(NEW_ID);
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cell->setPort(RTLIL::escape_id(buf_portname), mapped_wire_bit);
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cell->setPort(RTLIL::escape_id(buf_portname2), iwire);
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if (wire->port_input && !inpad_celltype.empty() && module->get_bool_attribute(ID::top)) {
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Wire *iwire = nullptr;
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RTLIL::Cell *cell = nullptr;
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bool is_input = wire->port_input && !inpad_celltype.empty() && module->get_bool_attribute(ID::top);
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if (!buf_celltype.empty() && (!is_input || buffer_inputs)) {
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log("Inserting %s on %s.%s[%d].\n", buf_celltype.c_str(), log_id(module), log_id(wire), i);
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cell = module->addCell(NEW_ID, RTLIL::escape_id(buf_celltype));
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iwire = module->addWire(NEW_ID);
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cell->setPort(RTLIL::escape_id(buf_portname), mapped_wire_bit);
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cell->setPort(RTLIL::escape_id(buf_portname2), iwire);
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}
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if (is_input) {
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log("Inserting %s on %s.%s[%d].\n", inpad_celltype.c_str(), log_id(module), log_id(wire), i);
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RTLIL::Cell *cell2 = module->addCell(NEW_ID, RTLIL::escape_id(inpad_celltype));
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cell2->setPort(RTLIL::escape_id(inpad_portname), iwire);
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if (iwire) {
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cell2->setPort(RTLIL::escape_id(inpad_portname), iwire);
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} else {
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cell2->setPort(RTLIL::escape_id(inpad_portname), mapped_wire_bit);
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cell = cell2;
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}
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iwire = module->addWire(NEW_ID);
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cell2->setPort(RTLIL::escape_id(inpad_portname2), iwire);
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}
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buffered_bits[mapped_wire_bit] = make_pair(cell, iwire);
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if (iwire)
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buffered_bits[mapped_wire_bit] = make_pair(cell, iwire);
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if (wire->port_input) {
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input_bits.insert(i);
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@ -1,5 +1,7 @@
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read_verilog <<EOT
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module clkbuf (input i, (* clkbuf_driver *) output o); endmodule
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module inbuf (input i, output o); endmodule
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module clkinbuf (input i, (* clkbuf_driver *) output o); endmodule
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module dff ((* clkbuf_sink *) input clk, input d, output q); endmodule
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module dffe ((* clkbuf_sink *) input c, input d, e, output q); endmodule
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module latch (input e, d, output q); endmodule
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@ -105,3 +107,80 @@ select -assert-count 0 w:clk1 %a %co t:clkbuf %i
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select -assert-count 0 w:clk2 %a %co t:clkbuf %i
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select -assert-count 0 top/t:clkbuf
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select -assert-count 2 sub/t:clkbuf
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# ----------------------
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design -load ref
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clkbufmap -buf clkbuf o:i -inpad inbuf o:i
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select -assert-count 3 top/t:clkbuf
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select -assert-count 3 sub/t:clkbuf
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select -assert-count 2 top/t:inbuf
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select -assert-count 0 sub/t:inbuf
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select -set clk1 w:clk1 %a %co t:inbuf %i
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select -assert-count 1 @clk1
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select -assert-count 1 @clk1 %x:+[o] %co t:clkbuf %i
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select -set clk1b @clk1 %x:+[o] %co t:clkbuf %i
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select -assert-count 1 @clk1b %x:+[o] %co c:s* %i
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select -assert-count 1 @clk1b %x:+[o] %co c:s0 %i
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select -set clk2 w:clk2 %a %co t:inbuf %i
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select -assert-count 1 @clk2
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select -assert-count 1 @clk2 %x:+[o] %co t:clkbuf %i
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select -set clk2b @clk2 %x:+[o] %co t:clkbuf %i
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select -assert-count 1 @clk2b %x:+[o] %co c:s* %i
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select -assert-count 1 @clk2b %x:+[o] %co c:s1 %i
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select -set clk5 w:clk5 %a %ci t:clkbuf %i
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select -assert-count 1 @clk5
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select -assert-count 1 @clk5 %x:+[o] %co c:s5 %i
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select -assert-count 1 @clk5 %x:+[i] %ci c:s3 %i
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select -set sclk4 w:sclk4 %a %ci t:clkbuf %i
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select -assert-count 1 @sclk4
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select -assert-count 1 @sclk4 %x:+[o] %co c:s11 %i
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select -assert-count 1 @sclk4 %x:+[i] %ci c:s7 %i
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select -set sclk8 w:sclk8 %a %ci t:clkbuf %i
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select -assert-count 1 @sclk8
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select -assert-count 1 @sclk8 %x:+[o] %co c:s13 %i
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select -assert-count 1 @sclk8 %x:+[i] %ci c:s12 %i
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# ----------------------
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design -load ref
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clkbufmap -inpad inbuf o:i
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select -assert-count 2 top/t:inbuf
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select -assert-count 0 sub/t:inbuf
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select -set clk1 w:clk1 %a %co t:inbuf %i
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select -assert-count 1 @clk1
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select -assert-count 1 @clk1 %x:+[o] %co c:s* %i
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select -assert-count 1 @clk1 %x:+[o] %co c:s0 %i
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select -set clk2 w:clk2 %a %co t:inbuf %i
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select -assert-count 1 @clk2
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select -assert-count 1 @clk2 %x:+[o] %co c:s* %i
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select -assert-count 1 @clk2 %x:+[o] %co c:s1 %i
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# ----------------------
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design -load ref
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clkbufmap -buf clkbuf o:i -inpad clkinbuf o:i
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select -assert-count 1 top/t:clkbuf
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select -assert-count 3 sub/t:clkbuf
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select -assert-count 2 top/t:clkinbuf
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select -assert-count 0 sub/t:clkinbuf
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select -set clk1 w:clk1 %a %co t:clkinbuf %i
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select -assert-count 1 @clk1
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select -assert-count 1 @clk1 %x:+[o] %co c:s* %i
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select -assert-count 1 @clk1 %x:+[o] %co c:s0 %i
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select -set clk2 w:clk2 %a %co t:clkinbuf %i
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select -assert-count 1 @clk2
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select -assert-count 1 @clk2 %x:+[o] %co c:s* %i
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select -assert-count 1 @clk2 %x:+[o] %co c:s1 %i
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select -set clk5 w:clk5 %a %ci t:clkbuf %i
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select -assert-count 1 @clk5
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select -assert-count 1 @clk5 %x:+[o] %co c:s5 %i
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select -assert-count 1 @clk5 %x:+[i] %ci c:s3 %i
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select -set sclk4 w:sclk4 %a %ci t:clkbuf %i
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select -assert-count 1 @sclk4
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select -assert-count 1 @sclk4 %x:+[o] %co c:s11 %i
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select -assert-count 1 @sclk4 %x:+[i] %ci c:s7 %i
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select -set sclk8 w:sclk8 %a %ci t:clkbuf %i
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select -assert-count 1 @sclk8
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select -assert-count 1 @sclk8 %x:+[o] %co c:s13 %i
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select -assert-count 1 @sclk8 %x:+[i] %ci c:s12 %i
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