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Merge pull request #2244 from antmicro/logic 

Add logic type support to parameters
This commit is contained in:
clairexen 2020-07-09 18:39:30 +02:00 committed by GitHub
parent 03e28f7ab4 b422f2e4d0
commit 802671b22e
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GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 31 additions and 7 deletions
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17
frontends/verilog/verilog_parser.y
View File

@ -1337,8 +1337,6 @@ param_signed:
param_integer:
TOK_INTEGER {
if (astbuf1->children.size() != 1)
frontend_verilog_yyerror("Internal error in param_integer - should not happen?");
astbuf1->children.push_back(new AstNode(AST_RANGE));
astbuf1->children.back()->children.push_back(AstNode::mkconst_int(31, true));
astbuf1->children.back()->children.push_back(AstNode::mkconst_int(0, true));
@ -1347,16 +1345,19 @@ param_integer:
param_real:
TOK_REAL {
if (astbuf1->children.size() != 1)
frontend_verilog_yyerror("Parameter already declared as integer, cannot set to real.");
astbuf1->children.push_back(new AstNode(AST_REALVALUE));
}
param_logic:
TOK_LOGIC {
// SV LRM 6.11, Table 6-8: logic -- 4-state, user-defined vector size, unsigned
astbuf1->is_signed = false;
astbuf1->is_logic = true;
}
param_range:
range {
if ($1 != NULL) {
if (astbuf1->children.size() != 1)
frontend_verilog_yyerror("integer/real parameters should not have a range.");
astbuf1->children.push_back($1);
}
};
@ -1365,8 +1366,10 @@ param_integer_type: param_integer param_signed
param_range_type: type_vec param_signed param_range
param_implicit_type: param_signed param_range
param_integer_vector_type: param_logic param_signed param_range
param_type:
param_integer_type | param_real | param_range_type | param_implicit_type |
param_integer_type | param_integer_vector_type | param_real | param_range_type | param_implicit_type |
hierarchical_type_id {
astbuf1->is_custom_type = true;
astbuf1->children.push_back(new AstNode(AST_WIRETYPE));

6
tests/various/integer_range_bad_syntax.ys Normal file
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@ -0,0 +1,6 @@
logger -expect error "syntax error, unexpected" 1
read_verilog -sv <<EOT
module test_integer_range();
parameter integer [31:0] a = 0;
endmodule
EOT

6
tests/various/integer_real_bad_syntax.ys Normal file
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@ -0,0 +1,6 @@
logger -expect error "syntax error, unexpected TOK_REAL" 1
read_verilog -sv <<EOT
module test_integer_real();
parameter integer real a = 0;
endmodule
EOT

9
tests/various/logic_param_simple.ys Normal file
View File

@ -0,0 +1,9 @@
read_verilog -sv <<EOT
module test_logic_param();
parameter logic a = 0;
parameter logic [31:0] e = 0;
parameter logic signed b = 0;
parameter logic unsigned c = 0;
parameter logic unsigned [31:0] d = 0;
endmodule
EOT