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abc9: uniquify blackboxes like whiteboxes (#2695)
* abc9_ops: uniquify blackboxes too * abc9_ops: update comment * abc9_ops: allow bypass for param-less blackboxes * Add tests
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@ -189,8 +189,6 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
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derived_type = inst_module->derive(design, cell->parameters);
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derived_module = design->module(derived_type);
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}
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if (derived_module->get_blackbox_attribute(true /* ignore_wb */))
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continue;
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if (derived_module->get_bool_attribute(ID::abc9_flop)) {
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if (!dff_mode)
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@ -799,14 +797,12 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
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if (!box_module->get_bool_attribute(ID::abc9_box))
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continue;
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if (!cell->parameters.empty())
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// At this stage of the ABC9 flow, all modules must be nonparametric, because ABC itself requires concrete netlists, and the presence of
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// parameters implies a non-concrete netlist. This error needs some explaining, because there are (at least) two ways to get this:
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// 1) You have an (* abc9_box *) parametric whitebox but due to a bug somewhere this hasn't been monomorphised into a concrete blackbox.
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// This is a bug, and a bug report would be welcomed.
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// 2) You have an (* abc9_box *) parametric blackbox (e.g. to store associated cell data) but want to provide timing data for ABC9.
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// This is not supported due to the presence of parameters. If you want to store associated cell data for a box, one approach could be
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// to techmap the parameters to constant module inputs, and then after ABC9 use _TECHMAP_CONSTVAL_XX_ to retrieve the values again.
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log_error("Black box '%s' is marked (* abc9_box *) and has parameters, which is forbidden in prep_xaiger\n", log_id(cell_name));
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{
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// At this stage of the ABC9 flow, all modules must be nonparametric, because ABC itself requires concrete netlists, and the presence of
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// parameters implies a non-concrete netlist. This means an (* abc9_box *) parametric module but due to a bug somewhere this hasn't been
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// uniquified into a concrete parameter-free module. This is a bug, and a bug report would be welcomed.
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log_error("Not expecting parameters on module '%s' marked (* abc9_box *)\n", log_id(cell_name));
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}
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log_assert(box_module->get_blackbox_attribute());
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cell->attributes[ID::abc9_box_seq] = box_count++;
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@ -90,7 +90,7 @@ $_DFF_N_ ff4(.C(clk), .D(1'b1), .Q(z));
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endmodule
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EOT
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simplemap
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equiv_opt abc9 -lut 4 -dff
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equiv_opt -assert abc9 -lut 4 -dff
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design -load postopt
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cd abc9_test038
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select -assert-count 3 t:$_DFF_N_
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@ -99,3 +99,58 @@ clean
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select -assert-count 2 a:init
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select -assert-count 1 w:w a:init %i
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select -assert-count 1 c:ff4 %co c:ff4 %d %a a:init %i
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# Check that non-dangling ABC9 black-boxes are preserved
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design -reset
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read_verilog -specify <<EOT
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(* abc9_box, blackbox *)
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module mux_with_param(input I0, I1, S, output O);
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parameter P = 0;
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specify
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(I0 => O) = P;
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(I1 => O) = P;
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(S => O) = P;
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endspecify
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endmodule
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module abc9_test039(output O);
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mux_with_param #(.P(1)) m (
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.I0(1'b1),
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.I1(1'b1),
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.O(O),
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.S(1'b0)
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);
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endmodule
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EOT
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abc9 -lut 4
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cd abc9_test039
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select -assert-count 1 t:mux_with_param
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# Check that dangling ABC9 black-boxes are swept away
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design -reset
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read_verilog -specify <<EOT
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(* abc9_box, blackbox *)
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module mux_with_param(input I0, I1, S, output O);
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parameter P = 0;
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specify
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(I0 => O) = P;
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(I1 => O) = P;
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(S => O) = P;
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endspecify
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endmodule
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module abc9_test040(output O);
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wire w;
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mux_with_param #(.P(1)) m (
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.I0(1'b1),
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.I1(1'b1),
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.O(w),
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.S(1'b0)
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);
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endmodule
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EOT
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abc9 -lut 4
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cd abc9_test040
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select -assert-count 0 t:mux_with_param
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