riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
6,563 Commits 76 Branches 48 Tags 62 MiB
Commit Graph

1167 Commits

Author SHA1 Message Date
Andrew Zonenberg 3618ca2218 Fixed typo in last commit 2017-08-14 10:45:39 -07:00
Andrew Zonenberg 4da1a327c0 Finished initial GP_COUNT8/14/8_ADV/14_ADV sim models. Don't support clock divide, but do everything else. 2017-08-14 10:45:39 -07:00
Andrew Zonenberg 4504dd78e9 Fixed typo in COUNT8 model 2017-08-14 10:45:39 -07:00
Andrew Zonenberg 60dd5dba7b Moved GP_POR out of digital cells b/c it has delays 2017-08-14 10:45:39 -07:00
Andrew Zonenberg f55d4cc2fd Improved cells_sim_digital model for GP_COUNT8 2017-08-14 10:45:39 -07:00
Andrew Zonenberg fe3a932cfa Refactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digital 2017-08-14 10:45:39 -07:00
Clifford Wolf 8a69759306 Add techlibs/xilinx/lut2lut.v 2017-07-10 12:09:05 +02:00
Clifford Wolf 621787a9e0 Fix some c++ clang compiler errors 2017-07-03 19:38:30 +02:00
Clifford Wolf 5c1c126374 Apply minor coding style changes to coolrunner2 target 2017-07-03 19:35:40 +02:00
Clifford Wolf 6afee022ad Merge pull request #352 from rqou/master 
Initial Coolrunner-II support
 2017-07-03 19:33:36 +02:00
Robert Ou b102c0e254 coolrunner2: Add a few more primitives 
These cannot be inferred yet, but add them to cells_sim.v for now
 2017-06-25 23:58:28 -07:00
Robert Ou 36b75dfcb7 coolrunner2: Initial mapping of latches 2017-06-25 23:58:28 -07:00
Robert Ou 4af5baab21 coolrunner2: Initial mapping of DFFs 
All DFFs map to either FDCP (matches Xilinx) or a custom FDCP_N
(negative-edge triggered)
 2017-06-25 23:58:28 -07:00
Robert Ou 1eb5dee799 coolrunner2: Remove redundant INVERT_PTC 2017-06-25 23:58:28 -07:00
Robert Ou ffff001008 coolrunner2: Remove debug prints 2017-06-25 23:58:28 -07:00
Robert Ou 5798105d47 coolrunner2: Correctly handle $_NOT_ after $sop 2017-06-25 23:58:28 -07:00
Robert Ou 908ce3fdce coolrunner2: Also construct the XOR cell in the macrocell 2017-06-25 23:58:28 -07:00
Robert Ou a64b56648d coolrunner2: Initial techmapping for $sop 2017-06-25 23:58:22 -07:00
Andrew Zonenberg cbdddc3af9 greenpak4_counters: Changed generation of primitive names so that the absorbed register's name is included 2017-06-24 14:54:07 -07:00
Robert Ou 6e0fb889fa coolrunner2: Initial commit 2017-06-24 07:22:56 -07:00
Clifford Wolf e7a984a4df Add dff2ff.v techmap file 2017-05-31 11:45:58 +02:00
Andrew Zonenberg 184bd148c9 greenpak4_counters: Added support for parallel output from GP_COUNTx cells 2017-05-22 19:39:55 -07:00
Clifford Wolf 05cdd58c8d Add $_ANDNOT_ and $_ORNOT_ gates 2017-05-17 09:08:29 +02:00
Larry Doolittle 2021ddecb3 Squelch trailing whitespace 2017-04-12 15:11:09 +02:00
dh73 c27dcc1e47 Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs 2017-04-05 23:01:29 -05:00
Clifford Wolf f3324ed0cc Merge branch 'master' of github.com:cliffordwolf/yosys 2017-02-25 13:08:27 +01:00
Clifford Wolf 5f1d0b1024 Add $live and $fair cell types, add support for s_eventually keyword 2017-02-25 10:36:39 +01:00
Andrew Zonenberg 6fed2dc996 Merge https://github.com/cliffordwolf/yosys 2017-02-14 08:29:37 -08:00
Clifford Wolf 2a311c2c38 Fix double-call of log_pop() in synth_greenpak4 2017-02-14 11:57:54 +01:00
Andrew Zonenberg 0d7e71f7ab Merge https://github.com/cliffordwolf/yosys 2017-02-08 22:12:29 -08:00
Clifford Wolf 3928482a3c Add $cover cell type and SVA cover() support 2017-02-04 14:14:26 +01:00
Andrew Zonenberg 27a626ce98 greenpak4: Added POUT to GP_COUNTx cells 2017-01-01 00:56:20 -08:00
Andrew Zonenberg ada98844b9 greenpak4: Added INT pin to GP_SPI 2016-12-21 11:35:29 +08:00
Andrew Zonenberg 6b526e9382 greenpak4: removed unused MISO pin from GP_SPI 2016-12-21 11:33:32 +08:00
Andrew Zonenberg 638f3e3b12 greenpak4: Removed SPI_BUFFER parameter 2016-12-20 13:07:49 +08:00
Andrew Zonenberg 073e8df9f1 greenpak4: replaced MOSI/MISO with single one-way SDAT pin 2016-12-20 12:34:56 +08:00
Andrew Zonenberg d4a05b499e greenpak4: Changed port names on GP_SPI for clarity 2016-12-20 10:30:38 +08:00
Andrew Zonenberg eb80ec84aa greenpak4: Initial implementation of GP_SPI cell 2016-12-20 09:58:02 +08:00
Andrew Zonenberg de1d81511a greenpak4: Updated GP_DCMP cell model 2016-12-17 12:01:22 +08:00
Andrew Zonenberg 7cdba8432c greenpak: Fixes to GP_DCMP* blocks. Added GP_CLKBUF. 2016-12-16 15:14:20 +08:00
Andrew Zonenberg bea6e2f11f greenpak4: Initial version of GP_DCMP skeleton (not yet usable). Changed interface to GP_DCMPMUX 2016-12-15 15:19:35 +08:00
Andrew Zonenberg 3690aa556c greenpak4: More fixups of GP_DCMPx cells 2016-12-15 07:19:08 +08:00
Andrew Zonenberg 3491d33863 greenpak4: And another typo :( 2016-12-15 07:17:07 +08:00
Andrew Zonenberg ea787e6be3 greenpak4: Fixed another typo 2016-12-15 07:16:26 +08:00
Andrew Zonenberg 58da621ac3 greenpak4: Fixed typo 2016-12-15 07:15:38 +08:00
Andrew Zonenberg 262f8f913c greenpak4: Cleaned up trailing spaces in cells_sim 2016-12-14 14:14:45 +08:00
Andrew Zonenberg c77e6e6114 greenpak4: Added GP_DCMPREF / GP_DCMPMUX 2016-12-14 14:14:26 +08:00
Andrew Zonenberg c3c2983d12 Added GP_PWRDET block, BANDWIDTH_KHZ parameter to GP_ABUF 2016-12-11 10:04:00 +08:00
Andrew Zonenberg 8f3d1f8fcf greenpak4: Added support for inferred input/output inverters on latches 2016-12-10 19:58:32 +08:00
Andrew Zonenberg c53a33143e greenpak4: Can now techmap inferred D latches (without set/reset or output inverter) 2016-12-10 18:46:36 +08:00
Andrew Zonenberg 797c03997e greenpak4: Inverted D latch cells now have nQ instead of Q as output port name for consistency 2016-12-10 13:57:37 +08:00
Andrew Zonenberg 8767cdcac9 Added GP_DLATCH and GP_DLATCHI 2016-12-05 23:49:06 -08:00
Andrew Zonenberg 981f014301 Initial implementation of techlib support for GreenPAK latches. Instantiation only, no behavioral inference yet. 2016-12-05 21:22:41 -08:00
Andrew Zonenberg e6ab00d419 Updated help text for synth_greenpak4 2016-12-05 20:11:37 -08:00
Clifford Wolf e9d73d2ee0 Indenting fixes in gowin sim cell lib 2016-11-08 18:54:00 +01:00
Clifford Wolf 3db2ac4e00 Added hex constant support to write_verilog 2016-11-03 12:13:23 +01:00
Clifford Wolf 81bdf0ad0f iCE40 flow is not experimental anymore 2016-11-01 11:32:02 +01:00
Clifford Wolf cae5131bac Added initial version of "synth_gowin" 2016-11-01 11:31:13 +01:00
Andrew Zonenberg 1cca1563c6 Fixed typo in last commit 2016-10-18 20:46:49 -07:00
Andrew Zonenberg e78fa157a3 greenpak4: Added GP_PGEN cell definition 2016-10-18 20:42:44 -07:00
Andrew Zonenberg 091d32b563 Added GLITCH_FILTER parameter to GP_DELAY 2016-10-18 19:53:19 -07:00
Andrew Zonenberg a818472f0c greenpak4: added model for GP_EDGEDET block 2016-10-18 19:33:26 -07:00
Andrew Zonenberg d6feb4b43e greenpak4: Changed parameters for GP_SYSRESET 2016-10-16 22:53:43 -07:00
Clifford Wolf bdc316db50 Added $anyseq cell type 2016-10-14 15:24:03 +02:00
Clifford Wolf 53655d173b Added $global_clock verilog syntax support for creating $ff cells 2016-10-14 12:33:56 +02:00
Clifford Wolf 8ebba8a35f Added $ff and $_FF_ cell types 2016-10-12 01:18:39 +02:00
Clifford Wolf 76352c99c9 Added "prep -nokeepdc" 2016-09-30 17:02:52 +02:00
Clifford Wolf 2ee9bf10d0 Added "prep -nomem" 2016-08-30 23:57:24 +02:00
Clifford Wolf 6f41e5277d Removed $aconst cell type 2016-08-30 19:09:56 +02:00
Clifford Wolf eae390ae17 Removed $predict again 2016-08-28 21:35:33 +02:00
Clifford Wolf d77a914683 Added "wreduce -memx" 2016-08-20 12:52:50 +02:00
Clifford Wolf 15ef608453 Added memory_memx pass, "memory -memx", and "prep -memx" 2016-08-19 19:48:26 +02:00
Clifford Wolf 5d90a5b905 Added greenpak4_dffinv 2016-08-15 09:33:06 +02:00
Andrew Zonenberg 0b0ba96488 greenpak4: Changed name of inverted output ports for consistency 2016-08-14 00:30:45 -07:00
Andrew Zonenberg 3b9756c6a3 greenpak4: Added GP_DFFxI cells 2016-08-14 00:11:44 -07:00
Andrew Zonenberg 2b062c48cb greenpak4: Renamed ports for better consistency (see azonenberg/openfpga:#6) 2016-08-13 22:27:58 -07:00
whitequark 0515809448 synth_greenpak4: use attrmvcp to move LOC from wires to cells. 2016-08-10 20:09:35 +00:00
Clifford Wolf 4056312987 Added $anyconst and $aconst 2016-07-27 15:41:22 +02:00
Clifford Wolf 5c166e76e5 Added $initstate cell type and vlog function 2016-07-21 14:23:22 +02:00
Clifford Wolf d7763634b6 After reading the SV spec, using non-standard predict() instead of expect() 2016-07-21 13:34:33 +02:00
Clifford Wolf 721f1f5ecf Added basic support for $expect cells 2016-07-13 16:56:17 +02:00
Andrew Zonenberg 52a738a544 Added GP_DAC cell 2016-07-11 22:45:55 -07:00
Andrew Zonenberg baae472b83 Removed VOUT port of GP_BANDGAP 2016-07-11 22:45:42 -07:00
Andrew Zonenberg 8619d33114 Removed splitnets in prep for new gp4par parser 2016-07-11 22:42:25 -07:00
Clifford Wolf cdb58f68ab Added "prep -auto-top" and "synth -auto-top" 2016-07-11 11:40:55 +02:00
whitequark c0645839fe greenpak4: add GP_COUNT{8,14}_ADV cells. 2016-07-10 15:46:46 +00:00
Clifford Wolf 21659847a7 Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiations 2016-07-08 14:41:36 +02:00
Clifford Wolf df5ebfa0a0 Improved ice40_ffinit error reporting 2016-06-30 09:58:13 +02:00
Clifford Wolf ca91bccb6b Added "deminout" 2016-06-19 13:08:16 +02:00
Clifford Wolf 95757efb25 Improved support for $sop cells 2016-06-17 16:31:16 +02:00
Clifford Wolf 52bb1b968d Added $sop cell type and "abc -sop" 2016-06-17 13:50:09 +02:00
Clifford Wolf 99edf24966 Added "nlutmap -assert" 2016-06-09 11:47:41 +02:00
Clifford Wolf 52b0b4e31e Do not run "wreduce" in "prep -ifx" 2016-06-08 12:14:32 +02:00
Clifford Wolf 2032e6d8e4 Added "proc_mux -ifx" 2016-06-06 17:15:50 +02:00
Andrew Zonenberg 47eace0b9f Added GP_DELAY cell 2016-05-07 21:29:26 -07:00
Andrew Zonenberg 41bbad4e4c Fixed typo in port name 2016-05-07 21:14:42 -07:00
Andrew Zonenberg b5171541cd Fixed extra semicolon 2016-05-07 21:14:18 -07:00
Andrew Zonenberg 85ee88b0ee Fixed typo in parameter name 2016-05-07 21:14:00 -07:00
Andrew Zonenberg a0c19aae55 Added simulation timescale declaration 2016-05-07 21:13:47 -07:00
Clifford Wolf 6fe3d5a1cf Added synth_ice40 support for latches via logic loops 2016-05-06 23:02:37 +02:00
Clifford Wolf 126da0ad3d Fixed ice40_opt lut unmapping, added "ice40_opt -unlut" 2016-05-06 14:32:32 +02:00
Andrew Zonenberg 2096a05ec2 Changed order of passes for better handling of INIT attributes on "output reg" FFs 2016-05-04 17:13:54 -07:00
Andrew Zonenberg dee1c27a19 Renamed module parameter 2016-05-04 17:03:45 -07:00
Andrew Zonenberg a613f171ae Refactored synth_greenpak4 to use iopadmap for mapping GP_IOBUF/GP_OBUFT cells instead of extract 2016-05-04 15:55:16 -07:00
Andrew Zonenberg deb1eccab5 Fixed incorrect signal naming in GP_IOBUF 2016-05-04 08:06:18 -07:00
Andrew Zonenberg dcee3256d5 Added tri-state I/O extraction for GreenPak 2016-05-03 22:53:29 -07:00
Andrew Zonenberg 66095153fd Added GreenPak I/O buffer cells 2016-05-03 22:03:04 -07:00
Andrew Zonenberg 9fc9d5f1fb Added comment to clarify GP_ABUF cell 2016-05-02 20:29:39 -07:00
Andrew Zonenberg 79460208c9 Added GP_ABUF cell 2016-05-02 20:27:41 -07:00
Andrew Zonenberg 134e093e4e Added GP_PGA cell 2016-04-27 23:07:21 -07:00
Andrew Zonenberg d57c85111f Merge https://github.com/cliffordwolf/yosys 2016-04-24 22:11:56 -07:00
Andrew Zonenberg 349d717202 Removed VIN_BUF_EN 2016-04-24 17:01:21 -07:00
Andrew Zonenberg 6e215f374d Renamed VOUT to OUT on GP_ACMP cell 2016-04-23 22:53:49 -07:00
Andrew Zonenberg 512486dcf3 Added GP_ACMP cell 2016-04-23 22:33:36 -07:00
Clifford Wolf 09ffebb995 Added "prep -flatten" and "synth -flatten" 2016-04-24 00:48:33 +02:00
Clifford Wolf 77aa2031e7 Converted "prep" to ScriptPass 2016-04-24 00:48:06 +02:00
Clifford Wolf c9c5192cd6 Run clean after splitnets in synth_greenpak4 2016-04-23 23:09:45 +02:00
Clifford Wolf 34195f281f Merge https://github.com/azonenberg/yosys 2016-04-23 10:33:32 +02:00
Clifford Wolf f85cfa5666 Added "shregmap" to synth_greenpak4 2016-04-23 10:31:19 +02:00
Clifford Wolf a24021ea20 Converted synth_greenpak4 to ScriptPass 2016-04-23 10:27:33 +02:00
Andrew Zonenberg 0cbe70eaa4 Fixed typo 2016-04-22 19:08:19 -07:00
Andrew Zonenberg ab11f2aa70 Merge https://github.com/cliffordwolf/yosys 2016-04-22 19:07:55 -07:00
Clifford Wolf 0bc95f1e04 Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
Andrew Zonenberg d90c1e9522 Added GP_VREF cell 2016-04-20 20:48:19 -07:00
Andrew Zonenberg d0aaf8d262 Added GP_SHREG cell 2016-04-13 23:13:51 -07:00
Andrew Zonenberg cdefa60367 Refactoring: alphabetized cells_sim 2016-04-13 23:13:39 -07:00
Andrew Zonenberg f1679936fe Fixed missing semicolon 2016-04-09 01:18:02 -07:00
Andrew Zonenberg 58d8715681 Added GP_RCOSC cell 2016-04-09 01:17:13 -07:00
Andrew Zonenberg 01a5f71187 Fixed assertion failure for non-inferrable counters in some cases 2016-04-06 23:42:22 -07:00
Andrew Zonenberg 48c10d90f4 Added second divider to GP_RINGOSC 2016-04-06 23:10:34 -07:00
Andrew Zonenberg 1df559c706 Added GP_RINGOSC primitive 2016-04-06 22:40:25 -07:00
Andrew Zonenberg c2b909c051 Added GP_POR 2016-04-04 21:46:07 -07:00
Andrew Zonenberg c01ff05fab Added GP_BANDGAP cell 2016-04-04 16:56:43 -07:00
Andrew Zonenberg 34667ded53 Removed more debug prints 2016-04-01 23:41:03 -07:00
Andrew Zonenberg 87e7cd9fbd Removed forgotten debug code 2016-04-01 23:39:32 -07:00
Andrew Zonenberg 2386885f22 Added GreenPak inverter support 2016-04-01 21:18:29 -07:00
Andrew Zonenberg 6dbcf50fa1 Added support for inferring counters with asynchronous resets. Fixed use-after-free in inference pass. 2016-04-01 18:07:59 -07:00
Andrew Zonenberg f277267916 Merge https://github.com/cliffordwolf/yosys 2016-04-01 00:03:00 -07:00
Andrew Zonenberg 736a998a75 DFFINIT is now correctly called for all kinds of flipflop, not just DFF 2016-03-31 23:16:45 -07:00
Andrew Zonenberg 7498ff8041 Fixed incorrect port name in cells_map.v 2016-03-31 22:51:22 -07:00
Clifford Wolf 2553319081 Added ScriptPass helper class for script-like passes 2016-03-31 11:16:34 +02:00
Andrew Zonenberg c04a3d2763 Fixed typo (wasn't written in 2012) 2016-03-30 23:58:45 -07:00
Clifford Wolf ec93680bd5 Renamed opt_share to opt_merge 2016-03-31 08:52:49 +02:00
Clifford Wolf 1d0f0d668a Renamed opt_const to opt_expr 2016-03-31 08:46:56 +02:00
Clifford Wolf d31c968d76 Fixed typo in greenpak4_counters.cc 2016-03-31 08:00:59 +02:00
Andrew Zonenberg 984561c034 Renamed counters pass to greenpak4_counters 2016-03-30 22:52:01 -07:00
Andrew Zonenberg 1ae33344f4 Added initial implementation of "counters" pass to synth_greenpak4. Can only infer non-resettable down counters for now. 2016-03-30 22:40:14 -07:00
Andrew Zonenberg 94a6923e7d Updated tech lib for greenpak4 counter with some clarifications 2016-03-30 20:30:25 -07:00
Andrew Zonenberg 489caf32c5 Initial work on greenpak4 counter extraction. Doesn't work but a decent start 2016-03-30 01:07:20 -07:00
Andrew Zonenberg 3ea6026648 Added splitnets to synth_greenpak4 2016-03-29 20:02:59 -07:00
Clifford Wolf 19c20235b5 Added more cell help messages 2016-03-29 15:14:43 +02:00
Clifford Wolf 8c8b2e72b1 Fixed indenting in techlibs/greenpak4/gp_dff.lib 2016-03-29 13:44:14 +02:00
Andrew Zonenberg 75f0030458 Added keep constraint to GP_SYSRESET cell 2016-03-28 23:16:43 -07:00
Andrew Zonenberg ea9cc03092 Added GP_SYSRESET block 2016-03-28 22:49:46 -07:00
Andrew Zonenberg 3197b6c372 Added GP_COUNT8/GP_COUNT14 cells 2016-03-26 23:29:02 -07:00
Andrew Zonenberg 31a7567aff Changed GP_LFOSC parameter configuration 2016-03-26 14:13:52 -07:00
Andrew Zonenberg 44fd3cd149 Added GP_LFOSC cell 2016-03-26 13:42:53 -07:00
Andrew Zonenberg af15b92c86 Renamed GP4_V* cells to GP_V* for consistency 2016-03-26 13:42:41 -07:00
Clifford Wolf b4bf787f10 Added GP_DFFS, GP_DFFR, and GP_DFFSR 2016-03-23 08:46:10 +01:00
Clifford Wolf 456c10f16e Added GP_DFF INIT parameter 2016-03-23 08:12:54 +01:00
Clifford Wolf ca8f8e30f2 Improvements in synth_greenpak4, added -part option 2016-03-21 09:44:52 +01:00
Clifford Wolf ff5c61b120 Added black box modules for all the 7-series design elements (as listed in ug953) 2016-03-19 11:09:10 +01:00
Clifford Wolf a75f94ec4a Run dffsr2dff in synth_xilinx 2016-02-13 08:20:19 +01:00
Clifford Wolf 0ccfb88728 Work around DDR dout sim glitches in ice40 SB_IO sim model 2016-02-07 11:19:48 +01:00
Clifford Wolf d69395ca08 Added dffsr2dff 2016-02-02 17:19:01 +01:00
Clifford Wolf bd10927f45 Progress in cell library documentation 2016-02-01 13:58:10 +01:00
Clifford Wolf 17372d8abd Added "abc -luts" option, Improved Xilinx logic mapping 2016-02-01 12:40:32 +01:00
Clifford Wolf 2ee608246f Re-run ice40_opt in "synth_ice40 -abc2" 2015-12-22 12:19:11 +01:00
Clifford Wolf 3102ffbb83 Improvements in ice40_opt 2015-12-22 12:18:38 +01:00
Clifford Wolf 8bf452c364 Bugfix in ice40_ffinit 2015-12-22 12:18:06 +01:00
Clifford Wolf ec93d258a4 Improved ice40_ffinit 2015-12-22 11:15:25 +01:00
Clifford Wolf f1b959dc69 Run opt_const before check in default scripts 2015-12-22 11:15:05 +01:00
Clifford Wolf 494e5f24f9 Added "synth_ice40 -abc2" 2015-12-08 11:16:26 +01:00
Clifford Wolf 4d0a6dac7b Merge pull request #108 from cseed/master 
Added LO to ICESTORM_LC for LUT cascade route.
 2015-12-07 03:32:20 +01:00
Cotton Seed 9f5b6e4cbc Added LO to ICESTORM_LC for LUT cascade route. 2015-12-06 17:24:48 -05:00
Clifford Wolf 0793f1b196 Added ice40_ffinit pass 2015-11-26 18:11:06 +01:00
Clifford Wolf 8ff229a3ea Fixed WE/RE usage in iCE40 BRAM mapping 2015-11-24 10:51:34 +01:00
Clifford Wolf 3ad742056b Fixed iCE40 SB_IO OUTPUT_ENABLE vs. outena_q handling 2015-11-06 17:02:16 +01:00
Clifford Wolf 864808992b Bugfix in Xilinx LUT mapping 2015-10-30 13:58:03 +01:00
Clifford Wolf bbcbf739e6 Progress on cell help messages 2015-10-20 16:49:11 +02:00
Clifford Wolf 5d1c0ce7c0 Progress on cell help messages 2015-10-17 02:35:19 +02:00
Clifford Wolf 25c1f6e605 Added "prep" command 2015-10-14 22:46:41 +02:00
Clifford Wolf 87adb523aa Added more cell descriptions 2015-10-14 20:30:59 +02:00
Clifford Wolf 7d3a3a3173 Added first help messages for cell types 2015-10-14 16:27:42 +02:00
Clifford Wolf f42218682d Added examples/ top-level directory 2015-10-13 15:41:20 +02:00
Clifford Wolf 924d9d6e86 Added read-enable to memory model 2015-09-25 12:23:11 +02:00
Clifford Wolf 598a475724 Added nlutmap 2015-09-18 21:57:34 +02:00
Clifford Wolf 745d56149d Renamed GreenPAK4 cells, improved GP4 DFF mapping 2015-09-18 12:00:37 +02:00
Clifford Wolf d9cecabb87 Fixed copy&paste typo in synth_greenpak4 2015-09-16 09:39:31 +02:00
Clifford Wolf c5352f45c3 Added GreenPAK4 skeleton 2015-09-16 09:28:37 +02:00
Clifford Wolf 99ccb3180d Fixed ice40 handling of negclk RAM40 2015-09-10 17:35:19 +02:00
Clifford Wolf c475deec6c Switched to Python 3 2015-08-22 09:59:33 +02:00
Clifford Wolf 9596fe74de Another bugfix for ice40 and xilinx brams_init make rules 2015-08-16 21:39:34 +02:00
Clifford Wolf aedcfd6fd3 Fixed Makefile rules for generated share files 2015-08-16 21:15:07 +02:00
Clifford Wolf d5b1a90b33 Added $tribuf and $_TBUF_ sim models 2015-08-16 13:05:32 +02:00
Clifford Wolf 9c33172ece Added tribuf command 2015-08-16 12:55:25 +02:00
Clifford Wolf ff50bc2ac3 Added $tribuf and $_TBUF_ cell types 2015-08-16 12:54:52 +02:00
Larry Doolittle 6c00704a5e Another block of spelling fixes 
Smaller this time
 2015-08-14 23:27:05 +02:00
Clifford Wolf e4ef000b70 Adjust makefiles to work with out-of-tree builds 
This is based on work done by Larry Doolittle
 2015-08-12 15:04:44 +02:00
Clifford Wolf c43f38c81b Improved handling of "keep" attributes in hierarchical designs in opt_clean 2015-08-12 14:10:14 +02:00
Marcus Comstedt c9e56bc428 Added iCE40 WARMBOOT cell 2015-08-06 22:58:17 +02:00
Clifford Wolf 8d6d5c30d9 Added WORDS parameter to $meminit 2015-07-31 10:40:09 +02:00
Clifford Wolf 516e8828f2 Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle) 2015-07-27 22:44:01 +02:00
Clifford Wolf c6ca4780e2 iCE40 DFF sim models: init Q regs to 0 2015-07-20 13:05:18 +02:00
Clifford Wolf 54588a276a Avoid tristate warning for blackbox ice40/cells_sim.v 2015-07-18 11:59:04 +02:00
Clifford Wolf 85aaf08e53 Improved liberty file test case 2015-07-06 17:45:56 +02:00
Clifford Wolf f0c9a099d2 Added "synth -nofsm" 2015-07-02 15:25:38 +02:00
Clifford Wolf 6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf df0163cd2b iCE40: set min bram efficiency to 2% 2015-06-20 09:31:19 +02:00
Clifford Wolf ed128b82d7 Added "synth -nordff -noalumacc" 2015-06-15 17:07:40 +02:00
Clifford Wolf 9500b564ac synth_ice40 now flattens by default 2015-06-09 20:28:17 +02:00
Clifford Wolf 09ef279b60 Added iCE40 PLL cells 2015-05-31 13:10:43 +02:00
Clifford Wolf c329233f0d Added output args to synth_ice40 2015-05-26 17:08:53 +02:00
Clifford Wolf 313f570fcc improved ice40 SB_IO sim model 2015-05-23 10:17:03 +02:00
Clifford Wolf 264eb8eb6e Added ice40 SB_IO sim model 2015-05-23 09:30:24 +02:00
Clifford Wolf 61512b6f41 Verific build fixes 2015-05-17 08:19:52 +02:00
Clifford Wolf 9d067fecea ice40_opt bugfix 2015-04-27 11:36:13 +02:00
Clifford Wolf 310fde197e iCE40: SB_CARRY const fold -> unmap SB_LUT 2015-04-27 10:27:50 +02:00
Clifford Wolf 794d22969d Added simplemap $lut support 2015-04-27 10:16:07 +02:00
Clifford Wolf 8d4a675f91 Added iCE40 const folding support for SB_CARRY 2015-04-27 08:38:14 +02:00
Clifford Wolf 752851954b Initialization support for all iCE40 bram modes 2015-04-26 08:39:31 +02:00
Clifford Wolf b4d7a590e8 initialized iCE40 brams (mode 0) 2015-04-25 20:44:51 +02:00
Clifford Wolf 4cc4400514 improved iCE40 SB_RAM40_4K simulation model 2015-04-25 20:01:37 +02:00
Clifford Wolf 82a4722f46 More iCE40 bram improvements 2015-04-25 18:04:57 +02:00
Clifford Wolf 687f5a5b12 iCE40 bram progress 2015-04-24 15:38:11 +02:00
Clifford Wolf 308a59aa18 iCE40 bram tests and fixes 2015-04-24 08:32:07 +02:00
Clifford Wolf d6f7698f59 Added ice40 bram support 2015-04-24 00:06:50 +02:00
Clifford Wolf 1277d1bcb8 iCE40: Added SB_RAM40_4K{,NR,NW,NRNW}* models 2015-04-19 21:37:40 +02:00
Clifford Wolf 49ef830464 added sync reset to ice40 test_ffs.sh 2015-04-18 09:41:31 +02:00
Clifford Wolf f564a65851 Added ice40 test_arith 2015-04-18 09:33:34 +02:00
Clifford Wolf f78fa718be Added ice40 SB_CARRY support 2015-04-18 09:33:08 +02:00
Clifford Wolf 661b647559 Added mapping of synchronous set/reset to iCE40 flow 2015-04-17 11:54:25 +02:00
Clifford Wolf 31755ed1cf Changed ice40 ICESTORM_CARRYCONST port name 2015-04-16 12:09:14 +02:00
Clifford Wolf dc30b034f7 Fixed "dff2dffe -direct-match" 2015-04-16 11:47:59 +02:00
Clifford Wolf 3e9e6e1c22 Added simple ice40 dff tests 2015-04-16 11:31:15 +02:00
Clifford Wolf 0d344a23d3 improved ice40 dff cell mapping 2015-04-16 11:30:56 +02:00
Clifford Wolf 4529c56cc6 use "hierarchy -auto-top" in synth_ice40 2015-04-14 13:45:15 +02:00
Clifford Wolf 06ce496f8d more cells in ice40 cell library 2015-04-14 13:44:43 +02:00
Clifford Wolf 3481f46d1e Improved xilinx "bram1" test 2015-04-09 17:12:12 +02:00
Clifford Wolf 7319951145 Added memory_bram "make_outreg" feature 2015-04-09 16:08:54 +02:00
Clifford Wolf 229825e1b8 Xilinx DRAMS: RAM64X1D, RAM128X1D 2015-04-09 13:37:07 +02:00
Clifford Wolf b00cad81d7 Towards DRAM support in Xilinx flow 2015-04-09 08:17:14 +02:00
Clifford Wolf 8520b7fbe0 Added support for initialized xilinx brams 2015-04-06 17:07:10 +02:00
Clifford Wolf d19866615b Added Xilinx test case for initialized brams 2015-04-06 13:27:11 +02:00
Clifford Wolf 4389d9306e Added Xilinx bram black-box modules 2015-04-06 08:44:30 +02:00
Clifford Wolf 95944eb69e make all vector-size related integer params in $mem sim model signed 
this fixes iverilog crashes such as the following:
warning: verinum::as_long() truncated 32 bits to 31, returns 2147483647
draw_net_input.c:711: Error: malloc() ran out of memory.
 2015-04-05 17:26:53 +02:00
Clifford Wolf 706631225e Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types 2015-04-05 09:45:14 +02:00
Clifford Wolf c52a4cdeed Added "dffinit", Support for initialized Xilinx DFF 2015-04-04 19:00:15 +02:00
Clifford Wolf e468d4cc60 Fixes in cmos_cells.v 2015-03-25 09:00:41 +01:00
Clifford Wolf 42d5d94a5d Added very first version of "synth_ice40" 2015-03-05 20:37:55 +01:00
Clifford Wolf b005eedf36 Added $assume cell type 2015-02-26 18:04:10 +01:00
Clifford Wolf 4d34d031f9 Added "stat" to "synth" and "synth_xilinx" 2015-02-15 13:25:15 +01:00
Clifford Wolf 881dcd8af9 Added final checks to "synth" and "synth_xilinx" 2015-02-15 13:00:00 +01:00
Clifford Wolf ec05242c27 Smaller default parameters in $mem simlib model 2015-02-15 00:20:05 +01:00
Clifford Wolf dcf2e24240 Added $meminit support to "memory" command 2015-02-14 12:55:03 +01:00
Clifford Wolf 910556560f Added $meminit cell type 2015-02-14 10:23:03 +01:00
Clifford Wolf 04cb947d6a Added "check" command 2015-02-13 14:34:51 +01:00
Clifford Wolf d58c3eca3a Some test related fixes 
(incl. removal of three bad test cases)
 2015-02-12 17:45:44 +01:00
Clifford Wolf 853e949c0e Disabled (unused) Xilinx tristate buffers 2015-02-04 16:33:59 +01:00
Clifford Wolf bebbf2e5a4 no support for 6-series xilinx devices 2015-02-01 23:06:44 +01:00
Clifford Wolf 3cbfa3815e Removed old XST-based xilinx examples 2015-02-01 17:10:46 +01:00
Clifford Wolf 816fe6bbe0 Added Xilinx example for Basys3 board 2015-02-01 17:09:34 +01:00
Clifford Wolf 1b159bc955 Added missing ports and parameters to xilinx brams 2015-02-01 15:42:59 +01:00
Clifford Wolf 1df81f92ce Added "make mklibyosys", some minor API changes 2015-02-01 13:38:46 +01:00
Clifford Wolf bedd46338f Added "fsm -encfile" 2015-01-30 22:46:53 +01:00
Clifford Wolf 909a95182b Fixed xilinx FDSE sim model 2015-01-24 11:03:22 +01:00
Clifford Wolf e13a45ae61 Added $equiv cell type 2015-01-19 11:55:05 +01:00
Clifford Wolf d29d26f882 Various cleanups in xilinx techlib 2015-01-18 19:43:54 +01:00
Clifford Wolf 8d295730e5 Refactoring of memory_bram and xilinx brams 2015-01-18 19:05:29 +01:00
Clifford Wolf 279a18c9a3 Added synth_xilinx -retime -flatten 2015-01-17 20:47:18 +01:00
Clifford Wolf 7031231145 Added MUXCY and XORCY support to synth_xilinx 2015-01-17 15:39:54 +01:00
Clifford Wolf 3ed4e34380 Added cells.lib 2015-01-16 15:50:42 +01:00
Clifford Wolf dff8bd3b2a Added dff2dffe to synth_xilinx 2015-01-16 15:49:15 +01:00
Clifford Wolf 7bde74cd2a Added more FF types to xilinx/cells.v 2015-01-16 15:24:54 +01:00
Clifford Wolf 6b09153320 Fixed xilinx bram clock inverted config 2015-01-16 15:11:56 +01:00
Clifford Wolf fd8c8d4fd3 Added FF cells to xilinx/cells_sim.v 2015-01-16 14:59:40 +01:00
Clifford Wolf b197279f3c Added Xilinx MUXF7 and MUXF8 support 2015-01-15 13:50:04 +01:00
Clifford Wolf 153d3dd4e0 Various cleanups in synth_xilinx command 2015-01-13 13:20:32 +01:00
Clifford Wolf 1d96277f5d Added add_share_file Makefile macro 2015-01-08 00:23:18 +01:00
Clifford Wolf 38dfc5c580 added minimalistic xilinx sim models 2015-01-08 00:05:11 +01:00
Clifford Wolf d1e38693d5 More Xilinx bram cleanups 2015-01-07 01:59:36 +01:00
Clifford Wolf 584c5f3937 Cleanups in xilinx bram descriptions 2015-01-07 01:28:18 +01:00
Clifford Wolf 08c13f635c Xilinx RAMB36/RAMB18 memory_bram support complete 2015-01-06 23:54:33 +01:00
Clifford Wolf ec2eef89fa Towards Xilinx bram support 2015-01-06 23:21:52 +01:00
Clifford Wolf 7cc5192125 small fix in xilinx/brams.v 2015-01-06 17:21:18 +01:00
Clifford Wolf 9474928672 Towards Xilinx bram support 2015-01-06 15:26:33 +01:00
Clifford Wolf 4a0b3a5423 Various small improvements to synth_xilinx 2015-01-06 14:37:50 +01:00
Clifford Wolf 081e1a49f8 Towards Xilinx bram support 2015-01-06 14:26:51 +01:00
Clifford Wolf 9c7f47bbd5 Towards Xilinx bram support 2015-01-06 13:33:51 +01:00
Clifford Wolf 9ea2511fe8 Towards Xilinx bram support 2015-01-05 13:59:04 +01:00
Clifford Wolf 8898897f7b Towards Xilinx bram support 2015-01-04 14:23:30 +01:00
Clifford Wolf a7e43ae3d9 Progress in memory_bram 2015-01-03 10:57:01 +01:00
Clifford Wolf 90f4017703 Added proper clkpol support to memory_bram 2015-01-02 22:57:08 +01:00
Clifford Wolf 474831643c New $mem simlib model 2015-01-02 17:11:31 +01:00
Clifford Wolf 327a5d42b6 Progress in memory_bram 2014-12-31 22:50:08 +01:00
Clifford Wolf 94e6b70736 Added memory_bram (not functional yet) 2014-12-31 16:53:53 +01:00
Clifford Wolf ba43cf5807 Fixed simlib entries for $memrd and $memwr 2014-12-30 13:33:29 +01:00
Clifford Wolf c64b1de11d Fixed build with SMALL=1 2014-12-30 11:41:24 +01:00
Clifford Wolf 4aa9fbbf3f Improvements in simplemap api, added $ne $nex $eq $eqx support 2014-12-24 10:49:24 +01:00
Clifford Wolf 72f500c950 Removed UTF-8 chars from techmap.v 2014-12-12 12:44:16 +01:00
Clifford Wolf f1764b4fe9 Added $dffe cell type 2014-12-08 10:50:19 +01:00
Clifford Wolf fad9cec47b Added $_DFFE_??_ cell types 2014-12-08 10:43:38 +01:00
Clifford Wolf 74ef92b9c8 Added "abc" label in synth script 2014-10-31 03:46:27 +01:00
Clifford Wolf ab28491f27 Added "opt -full" alias for all more aggressive optimizations 2014-10-31 03:36:51 +01:00
Clifford Wolf c3e779a65f Added $_BUF_ cell type 2014-10-03 10:12:28 +02:00
Clifford Wolf f9a307a50b namespace Yosys 2014-09-27 16:17:53 +02:00
Clifford Wolf 4888d61c65 Improvements in "synth" script 2014-09-18 12:57:55 +02:00
Clifford Wolf 6644e27cd4 Fixed $macc simlib model for zero-config 2014-09-16 08:19:35 +02:00
Clifford Wolf 7815f81c32 Added "synth" command 2014-09-14 16:09:06 +02:00
Clifford Wolf 923bbbeaf0 Using alumacc in techmap.v 2014-09-14 14:50:15 +02:00
Clifford Wolf 44b5bd4b63 Fixed simlib $macc model for xilinx xsim 2014-09-08 17:09:39 +02:00
Clifford Wolf fcb46138ce Simplified $fa undef model 2014-09-08 16:59:39 +02:00
Clifford Wolf 6dc07eb1f2 Fixes and cleanups for blackbox.v 2014-09-08 13:31:04 +02:00
Clifford Wolf af0c8873bb Added $lcu cell type 2014-09-08 13:31:04 +02:00
Clifford Wolf d46bac3305 Added "$fa" cell type 2014-09-08 12:15:39 +02:00
Clifford Wolf dd887cc025 Using maccmap for $macc and $mul techmap 2014-09-07 18:24:08 +02:00
Clifford Wolf 9329a76818 Various bug fixes (related to $macc model testing) 2014-09-06 20:30:46 +02:00
Clifford Wolf fa64942018 Added $macc SAT model 2014-09-06 19:44:11 +02:00
Clifford Wolf bff4706b62 Added $macc simlib model (also use as techmap rule for now) 2014-09-06 17:59:12 +02:00
Clifford Wolf 8927aa6148 Removed $bu0 cell type 2014-09-04 02:07:52 +02:00
Clifford Wolf 635b922afe Undef-related fixes in simlib $alu model 2014-09-02 23:21:59 +02:00
Clifford Wolf c38283dbd0 Small bug fixes in $not, $neg, and $shiftx models 2014-09-02 17:48:41 +02:00
Clifford Wolf 9923762461 Fixed "test_cell -simlib all" 2014-09-01 15:37:56 +02:00
Clifford Wolf 8649b57b6f Added $lut support in test_cell, techmap, satgen 2014-08-31 17:43:31 +02:00
Clifford Wolf 4724d94fbc Added $alu cell type 2014-08-30 18:59:05 +02:00
Clifford Wolf eb571cba6a Replaced $__alu CO/CS outputs with full-width CO output 2014-08-30 15:12:39 +02:00
Clifford Wolf a92a68ce52 Using "via_celltype" in $mul carry-save-acc implementation 2014-08-18 14:30:20 +02:00
Clifford Wolf 6f33fc3e87 Performance fix for new $__lcu techmap rule 2014-08-18 00:27:54 +02:00
Clifford Wolf 4b3834e0cc Replaced recursive lcu scheme with bk adder 2014-08-18 00:03:33 +02:00
Clifford Wolf 976bda7102 Multiply using a carry-save accumulator 2014-08-16 21:07:29 +02:00
Clifford Wolf 47c2637a96 Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_ 2014-08-16 18:29:39 +02:00
Clifford Wolf 1ddf150c35 Changes in techmap $__alu interface 2014-08-16 16:01:58 +02:00
Clifford Wolf b64b38eea2 Renamed $lut ports to follow A-Y naming scheme 2014-08-15 14:18:40 +02:00
Clifford Wolf f092b50148 Renamed $_INV_ cell type to $_NOT_ 2014-08-15 14:11:40 +02:00
Clifford Wolf 5602cbde9f Simplified $__arraymul techmap rule 2014-08-14 20:53:21 +02:00
Clifford Wolf 13f2f36884 RIP $safe_pmux 2014-08-14 11:39:46 +02:00
Clifford Wolf 7e758d5fbb Added techmap support for actual lookahead carry unit 2014-08-13 18:40:57 +02:00
Clifford Wolf 9a065509ac Preparations for lookahead ALU support in techmap.v 2014-08-13 16:36:30 +02:00
Clifford Wolf c27120fcbc New interface for $__alu in techmap.v 2014-08-13 13:04:28 +02:00
Clifford Wolf 312ee00c9e Added adff2dff.v (for techmap -share_map) 2014-08-07 16:14:38 +02:00
Clifford Wolf 014a41fcf3 Implemented recursive techmap 2014-08-03 12:40:43 +02:00
Clifford Wolf 1202f7aa4b Renamed "stdcells.v" to "techmap.v" 2014-07-31 02:32:00 +02:00
Clifford Wolf 41555cde10 Reorganized stdcells.v (no actual code change, just moved and indented stuff) 2014-07-31 02:21:06 +02:00
Clifford Wolf 2541489105 Added techmap CONSTMAP feature 2014-07-30 22:04:30 +02:00
Clifford Wolf 6c05badc43 New techmap default rules for $shr $sshr $shl $sshl 2014-07-30 18:49:12 +02:00
Clifford Wolf 2145e57ef0 Bugfix in simlib.v for iverilog 2014-07-29 19:23:31 +02:00
Clifford Wolf 397b00252d Added $shift and $shiftx cell types (needed for correct part select behavior) 2014-07-29 16:35:13 +02:00
Clifford Wolf b17d6531c8 Added "make PRETTY=1" 2014-07-24 17:15:01 +02:00
Clifford Wolf f1ca93a0a3 Fixed simlib.v model for $mem 2014-07-17 16:48:36 +02:00
Clifford Wolf dcdd5c11b4 Updated simlib to new $mem/$memwr interface 2014-07-16 11:46:40 +02:00
Clifford Wolf 7370ae01e9 Added SIMLIB_NOLUT to simlib.v 2014-04-02 21:28:33 +02:00
Clifford Wolf e24797add0 Added SIMLIB_NOSR to simlib.v 2014-04-02 21:06:55 +02:00
Clifford Wolf d4a1b0af5b Added support for dlatchsr cells 2014-03-31 14:14:40 +02:00
Clifford Wolf 7aa2d746b7 Merged addition of SED makefile variable from github.com/Siesh1oo/yosys 
(see https://github.com/cliffordwolf/yosys/pull/28)
 2014-03-11 14:42:58 +01:00
Clifford Wolf 973507d85b Fixes for improved techmap of shifts with large B inputs 2014-03-06 13:33:12 +01:00
Clifford Wolf 8406e7f7b6 Strictly zero-extend unsigned A-inputs of shift operations in techmap 2014-03-06 12:15:44 +01:00
Clifford Wolf d7f29bb23f Improved techmap of shift with wide B inputs 2014-03-06 12:14:20 +01:00
Clifford Wolf fc3b3c4ec3 Added $slice and $concat cell types 2014-02-07 17:44:57 +01:00
Clifford Wolf a6750b3753 Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem) 2014-02-03 13:01:45 +01:00
Clifford Wolf ed8ad99960 More changes to techlibs/common/simlib.v for LEC 2014-01-31 11:21:29 +01:00
Clifford Wolf 6a7d7e847d Added test comments to techlibs/cmos/cmos_cells.lib 2014-01-29 10:51:02 +01:00
Clifford Wolf a86f33653d Major rewrite of techlibs/common/simlib.v for LEC (cadance conformal) 2014-01-29 00:36:03 +01:00
Clifford Wolf 1e67099b77 Added $assert cell 2014-01-19 14:03:40 +01:00
Clifford Wolf 3d7a1491aa Fixed $lut simlib model for a wider range of tools 2014-01-18 19:31:40 +01:00
Clifford Wolf 2fbaaaca7a More changes to simlib to make it friendlier to a wider range of tools 2014-01-18 19:13:43 +01:00
Clifford Wolf 4a9e133fab Fixed a type in $mem model in simlib.v 2014-01-18 18:54:50 +01:00
Clifford Wolf bef17eeb10 Removed cases of trailing comma in stdcells.v 2014-01-18 15:36:17 +01:00
Clifford Wolf 5b96675696 Added $bu0 cell to simlib.v 2014-01-18 15:35:15 +01:00
Clifford Wolf db9cf544b8 Added techlibs/common/pmux2mux.v 2014-01-17 20:06:15 +01:00
Clifford Wolf b3b00f1bf4 Various small cleanups in stdcells.v techmap code 2013-12-31 15:41:40 +01:00
Clifford Wolf c69c416d28 Added $bu0 cell (for easy correct $eq/$ne mapping) 2013-12-28 12:02:14 +01:00
Clifford Wolf 369bf81a70 Added support for non-const === and !== (for miter circuits) 2013-12-27 14:20:15 +01:00
Clifford Wolf 76f7c10cfc Using simplemap mappers from techmap 2013-11-24 23:31:14 +01:00
Clifford Wolf 1afe6589df Renamed stdcells_sim.v to simcells.v and fixed blackbox.v 2013-11-24 20:44:00 +01:00
Clifford Wolf 20175afd29 Added "techmap -share_map" option 2013-11-24 19:50:25 +01:00
Clifford Wolf ae798d3fd5 Fixed xilinx/example_sim_counter test bench 2013-11-24 17:55:46 +01:00
Clifford Wolf 532091afcb Added more generic _TECHMAP_ wire mechanism to techmap pass 2013-11-23 15:58:06 +01:00
Clifford Wolf 1c4a6411af Updated abc 2013-11-21 22:39:10 +01:00
Clifford Wolf 0c91f890c9 Install simlib in datdir 2013-11-19 23:05:46 +01:00
Clifford Wolf 97f2979bba Added commented-out osu025 maping commands to cmos techmap example 2013-11-18 12:01:00 +01:00
Clifford Wolf e5b974fa2a Cleanups and bugfixes in response to new internal cell checker 2013-11-11 00:39:45 +01:00
Clifford Wolf 404b46674b Fixed techmap of $reduce_xnor with multi-bit outputs 2013-11-07 00:58:06 +01:00
Clifford Wolf b41740060b Fixed techmap of $gt and $ge with multi-bit outputs 2013-11-06 22:59:45 +01:00
Clifford Wolf 6fcbc79b5c Improved width extension with regard to undef propagation 2013-11-06 21:05:11 +01:00
Clifford Wolf 0b4a64ac6a Added DFFSR cell to techlibs/cmos/cmos_cells.lib 2013-10-31 12:27:35 +01:00
James Walmsley 40b3551b45 [EXAMPLES] Ported the mojo counter example to Zynq ZED board. 
Will be adding a tutorial on this to verilog.james.walms.co.uk in a few days.
 2013-10-27 21:48:39 +01:00
Clifford Wolf 88cd2eadf5 Cleanups in xilinx examples 2013-10-27 09:58:53 +01:00
Clifford Wolf 4a3669d871 Added synth_xilinx command 2013-10-27 09:51:06 +01:00
Clifford Wolf 90b016716b Moved simple xilinx counter sim example to subdir 2013-10-27 09:30:17 +01:00
Clifford Wolf 02f321b6fc Xilinx mojo_counter example is now working 2013-10-27 08:21:56 +01:00
Clifford Wolf d635f8adaa Renamed techlibs/xilinx7 to techlibs/xilinx 2013-10-26 22:29:40 +02:00
Clifford Wolf 4007b41d40 Improved xilinx mojo_counter example 2013-10-26 22:28:42 +02:00
Clifford Wolf b934a2d209 Added another xilinx example (not funcional yet) 2013-10-26 17:22:29 +02:00
Clifford Wolf 0836a1f2ba Bugfix in dffsr techmap rules 2013-10-18 13:24:44 +02:00
Clifford Wolf 8197169f8d Added techmap rules for $sr, $dffsr and $dlatch 2013-10-18 12:29:21 +02:00
Clifford Wolf e0f693cbb0 Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_ 2013-10-18 12:13:34 +02:00
Clifford Wolf 5998c101a4 Added $sr, $dffsr and $dlatch cell types 2013-10-18 11:56:16 +02:00
Clifford Wolf 5745d3de9a Added map, par and bitgen to xlinx7 example 2013-10-16 10:57:18 +02:00
Clifford Wolf 288ba9618a Moved common techlib files to techlibs/common 2013-09-15 11:52:57 +02:00
Clifford Wolf 2c9bd23801 Added spice testbench to techlibs/cmos 2013-09-14 13:29:11 +02:00
Clifford Wolf bbe5aa446b Added spice backend 2013-09-14 11:23:45 +02:00
Clifford Wolf 6685ad436e Added mapping to techlibs/xilinx7 testbench (exposes EDIF backend todos) 2013-08-27 13:12:26 +02:00
Clifford Wolf 5059b31660 Added simple xilinx7 technology mapping files 2013-08-22 20:31:04 +02:00
Clifford Wolf a860efa8ac Implemented same div-by-zero behavior as found in other synthesis tools 2013-08-15 21:00:06 +02:00
Clifford Wolf c8763301b4 Added $div and $mod technology mapping 2013-08-09 17:09:24 +02:00
Clifford Wolf ad9bbcbf40 Added $lut cells and abc lut mapping support 2013-07-23 16:19:34 +02:00
Clifford Wolf 7daeee340a Fixed shift ops with large right hand side 2013-07-09 18:59:59 +02:00
Clifford Wolf 0c6ffc4c65 More fixes for bugs found using xsthammer 2013-06-13 11:18:45 +02:00
Clifford Wolf 7f3f25841e More sign-extension related fixes 2013-06-10 21:04:04 +02:00
Clifford Wolf 29d6ebd961 Implemented technology mapping for multipliers (using array multiplier) 2013-06-03 12:48:44 +02:00
Clifford Wolf 32dbf7752d Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v 2013-04-07 16:42:29 +02:00
Clifford Wolf d60fbaf664 Added EXTRA_TARGETS Makefile variable 2013-03-28 16:53:40 +01:00
Clifford Wolf 26f2439551 Tiny bugfix in simlib.v 2013-03-26 19:06:28 +01:00
Clifford Wolf 6960df7285 Fixed stdcells.v for $adff with undef reset value 2013-03-24 10:43:05 +01:00
Clifford Wolf 11789db206 More support code for $sr cells 2013-03-14 11:15:00 +01:00
Clifford Wolf 6543917fb8 added .gitignore files 2013-01-05 11:19:11 +01:00
Clifford Wolf 7764d0ba1d initial import 2013-01-05 11:13:26 +01:00