mirror of https://github.com/YosysHQ/yosys.git
coolrunner2: Initial mapping of latches
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4af5baab21
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@ -2,5 +2,6 @@
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OBJS += techlibs/coolrunner2/synth_coolrunner2.o
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OBJS += techlibs/coolrunner2/coolrunner2_sop.o
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$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_latch.v))
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$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_sim.v))
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$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/xc2_dff.lib))
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@ -0,0 +1,19 @@
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module $_DLATCH_P_(input E, input D, output Q);
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LDCP _TECHMAP_REPLACE_ (
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.D(D),
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.G(E),
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.Q(Q),
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.PRE(1'b0),
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.CLR(1'b0)
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);
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endmodule
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module $_DLATCH_N_(input E, input D, output Q);
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LDCP_N _TECHMAP_REPLACE_ (
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.D(D),
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.G(E),
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.Q(Q),
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.PRE(1'b0),
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.CLR(1'b0)
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);
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endmodule
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@ -94,3 +94,43 @@ module FDCP_N (C, PRE, CLR, D, Q);
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Q <= D;
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end
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endmodule
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module LDCP (G, PRE, CLR, D, Q);
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parameter INIT = 0;
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input G, PRE, CLR, D;
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output reg Q;
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initial begin
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Q <= INIT;
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end
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always @* begin
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if (CLR == 1)
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Q <= 0;
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else if (G == 1)
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Q <= D;
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else if (PRE == 1)
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Q <= 1;
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end
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endmodule
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module LDCP_N (G, PRE, CLR, D, Q);
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parameter INIT = 0;
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input G, PRE, CLR, D;
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output reg Q;
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initial begin
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Q <= INIT;
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end
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always @* begin
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if (CLR == 1)
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Q <= 0;
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else if (G == 0)
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Q <= D;
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else if (PRE == 1)
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Q <= 1;
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end
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endmodule
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@ -145,6 +145,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
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{
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run("opt -fast -full");
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run("techmap");
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run("techmap -map +/coolrunner2/cells_latch.v");
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run("dfflibmap -prepare -liberty +/coolrunner2/xc2_dff.lib");
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}
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@ -160,6 +161,8 @@ struct SynthCoolrunner2Pass : public ScriptPass
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run("dfflibmap -liberty +/coolrunner2/xc2_dff.lib");
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run("dffinit -ff FDCP Q INIT");
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run("dffinit -ff FDCP_N Q INIT");
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run("dffinit -ff LDCP Q INIT");
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run("dffinit -ff LDCP_N Q INIT");
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run("iopadmap -bits -inpad IBUF O:I -outpad IOBUFE I:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE E:I:IO -tinoutpad IOBUFE E:O:I:IO");
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}
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