coolrunner2: Initial mapping of latches

This commit is contained in:
Robert Ou 2017-06-25 20:58:45 -07:00
parent 4af5baab21
commit 36b75dfcb7
4 changed files with 63 additions and 0 deletions

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@ -2,5 +2,6 @@
OBJS += techlibs/coolrunner2/synth_coolrunner2.o
OBJS += techlibs/coolrunner2/coolrunner2_sop.o
$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_latch.v))
$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_sim.v))
$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/xc2_dff.lib))

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@ -0,0 +1,19 @@
module $_DLATCH_P_(input E, input D, output Q);
LDCP _TECHMAP_REPLACE_ (
.D(D),
.G(E),
.Q(Q),
.PRE(1'b0),
.CLR(1'b0)
);
endmodule
module $_DLATCH_N_(input E, input D, output Q);
LDCP_N _TECHMAP_REPLACE_ (
.D(D),
.G(E),
.Q(Q),
.PRE(1'b0),
.CLR(1'b0)
);
endmodule

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@ -94,3 +94,43 @@ module FDCP_N (C, PRE, CLR, D, Q);
Q <= D;
end
endmodule
module LDCP (G, PRE, CLR, D, Q);
parameter INIT = 0;
input G, PRE, CLR, D;
output reg Q;
initial begin
Q <= INIT;
end
always @* begin
if (CLR == 1)
Q <= 0;
else if (G == 1)
Q <= D;
else if (PRE == 1)
Q <= 1;
end
endmodule
module LDCP_N (G, PRE, CLR, D, Q);
parameter INIT = 0;
input G, PRE, CLR, D;
output reg Q;
initial begin
Q <= INIT;
end
always @* begin
if (CLR == 1)
Q <= 0;
else if (G == 0)
Q <= D;
else if (PRE == 1)
Q <= 1;
end
endmodule

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@ -145,6 +145,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
{
run("opt -fast -full");
run("techmap");
run("techmap -map +/coolrunner2/cells_latch.v");
run("dfflibmap -prepare -liberty +/coolrunner2/xc2_dff.lib");
}
@ -160,6 +161,8 @@ struct SynthCoolrunner2Pass : public ScriptPass
run("dfflibmap -liberty +/coolrunner2/xc2_dff.lib");
run("dffinit -ff FDCP Q INIT");
run("dffinit -ff FDCP_N Q INIT");
run("dffinit -ff LDCP Q INIT");
run("dffinit -ff LDCP_N Q INIT");
run("iopadmap -bits -inpad IBUF O:I -outpad IOBUFE I:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE E:I:IO -tinoutpad IOBUFE E:O:I:IO");
}